Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET)

We have demonstrated the method of threshold voltage (VT) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET. Single WFM shared gate N1 CFET was used to study and emphasize the VT tunability of the proposed Ge content method. The result reveals that the Ge mole fraction influences VTP of 5 mV/Ge%, and a close result can also be obtained from the energy band configuration of Si1-xGex. Additionally, the single WFM shared gate N1 CFET inverter with VT adjusted by the Ge content method presents a well-designed voltage transfer curve, and its inverter transient response is also presented. Furthermore, the designed CFET inverter is used to construct a well-behaved 6T-SRAM with a large SNM of ~120 mV at VDD of 0.5 V.


Introduction
The semiconductor logic device architectures continue to progress, and innovation is driving Moore's law scaling. Given the transition from planar metal oxide semiconductor field-effect transistor (MOSFET) to three-dimensional FinFET and following stacked nanosheet gate-all-around FET (GAAFETs), the complementary FET (CFET) has been recently proposed as a candidate architecture for the beyond technology node [1][2][3][4]. However, due to shrinking gate length (L G ), insufficient space for filling multiple work function metal (WFM), which is used for obtaining the desirable device's threshold voltage (V T ), has become a challenging problem. Since the gate stack also uses space on the sidewalls under the replacement metal gate (RMG) process [5][6][7], the issue could worsen on stacked nanosheet GAAFETs and become more severe with CFETs. That is because the vertical spacing between the channels must also simultaneously be considered for stacked architectures [8]. As for CFETs, the dual WFM gates should be achieved in the same area but in different layers, which increases the issue's complexity to a greater extent [1,9].
To maintain the flexibility of multi-V T for balancing low power consumption and high performance, volume-less (also called zero-thickness) methods for VT adjustment are needed. Some research focused on finding methods to reduce the thickness of gate stacks while not losing the V T stability [6,7]. Others proposed an alternative way of using a dipole layer to adjust V T due to its role as an intrinsic fixed charge in gate stacks [10,11]. However, the incorporation of the dipole layer may cause an increase of interface trap density [12,13], which would deteriorate the reliability of the device. Furthermore, the dipole layer may also bring the degradation of mobility [10,13]. This paper proposes another alternative method for adjusting V T by controlling the Ge content in the Si 1-x Ge x channel. Si 1-x Ge x is used in strain engineering for hole mobility improvement due to its compatibility in the Si CMOS process [14]. On the other hand, Si 1-x Ge x was proposed to lower PMOS V T by band engineering [15]. In addition, a FinFET CMOS technology of Si channel. Si1-xGex is used in strain engineering for hole mobility improvement due to its compatibility in the Si CMOS process [14]. On the other hand, Si1-xGex was proposed to lower PMOS VT by band engineering [15]. In addition, a FinFET CMOS technology of Si NMOS-SiGe PMOS with common WFM was demonstrated [16]. Additionally, decreasing VT was found in Si1-xGex PMOS with increasing Ge content [17]. These studies showed that the Si1-xGex possesses the potential to influence VT. Therefore, in this work, we discuss the methodology of VT adjustment by varying Ge content in the SiGe channel and demonstrate the VT adjustment method on the single WFM shared gate CFET as N1 technology using Sentaurus technology computer-aided design (TCAD). The process on the SiGe channel would have no occupation on the spacing for high-k metal gates and gate contact filling. On the other hand, the SiGe channel with Ge content of less than 50% has already been used in today's semiconductor technology; hence, the proposed method is compatible with the manufacturing technology. In addition, we present the inverter characteristics of the designed N1 CFET and further use it to construct a 6T-SRAM. Figure 1a displays a bird's eye view of the N1 CFET architecture in this study. The Synopsys TCAD simulator was employed for the 3-D simulations [18]. The simulation parameters, including gate length (LG = 12 nm), channel thickness (Wch = 6 nm), gate oxide thickness (Tox = 2 nm, HfO2), channel vertical pitch (Pvertical = 14 nm), spacer length (Lsp = 4 nm), and source/drain contact length (LC = 20 nm), are based on the prediction of the 1 nm node logic device in the international roadmap for devices and system (IRDS) 2020 [19]. In the meantime, the architecture designs are also referred from the experimental CFET structure proposed by Intel [1], which stacked the two-channel NMOS on top of the three-channel PMOS on a Si-on-insulator (SOI) substrate. The PMOS is designed to have a longer contact gate pitch (CGP) than the NMOS to separate the source contacts of NMOS and PMOS as the electrodes of GND and VDD for the CFET inverter, respectively. As shown in Figure 1b, the contact of Vin is shared by the NMOS gate and the PMOS gate. In addition, Vout is shared by the NMOS drain and PMOS drain. GND and VDD are used for the sources of NMOS and PMOS, respectively. Tungsten is used as the contact metal for all the electrodes. Afterward, SiO2 is used as fill for oxide passivation, side-wall spacer, In the meantime, the architecture designs are also referred from the experimental CFET structure proposed by Intel [1], which stacked the two-channel NMOS on top of the three-channel PMOS on a Si-on-insulator (SOI) substrate. The PMOS is designed to have a longer contact gate pitch (CGP) than the NMOS to separate the source contacts of NMOS and PMOS as the electrodes of GND and V DD for the CFET inverter, respectively. As shown in Figure 1b, the contact of V in is shared by the NMOS gate and the PMOS gate. In addition, V out is shared by the NMOS drain and PMOS drain. GND and V DD are used for the sources of NMOS and PMOS, respectively. Tungsten is used as the contact metal for all the electrodes. Afterward, SiO 2 is used as fill for oxide passivation, side-wall spacer, and filler of nanosheets inter-spacing. The structural simulation parameters of the N1 CFET simulation are shown in Table 1. To increase the accuracy of the simulation in this study, the I D -V G transfer characteristics of the CFET with L G of 75 nm were calibrated to the experimental result from [1]. The following physical models were considered and coupled in the TCAD simulation:

Device Structure and Simulation Methodology
1.
The drift-diffusion model was included with the coupled Possion's and continuity equations to determine the electrostatic potential and carrier transport.

2.
The density gradient model was included to correct the quantum confinement effect in the drift-diffusion model due to the highly scaled dimension [20].

5.
The doping-dependent, transverse field dependence, and high-field saturation mobility models were included to consider impurity scattering, interfacial surface roughness scattering, and coulomb scattering degradations.

6.
A ballistic mobility model was considered for quasi-ballistic transport.
The calibration result is shown in Figure 2. The simulation of the following inverter transient response and the 6T-SRAM were achieved using "mixed-mode" in SDEVICE of Sentaurus TCAD. and filler of nanosheets inter-spacing. The structural simulation parameters of the N1 CFET simulation are shown in Table 1. To increase the accuracy of the simulation in this study, the ID-VG transfer characteristics of the CFET with LG of 75 nm were calibrated to the experimental result from [1]. The following physical models were considered and coupled in the TCAD simulation: 1. The drift-diffusion model was included with the coupled Possion's and continuity equations to determine the electrostatic potential and carrier transport. 2. The density gradient model was included to correct the quantum confinement effect in the drift-diffusion model due to the highly scaled dimension [20]. 3. The doping-concentration-dependent Shockley-Read-Hall (SRH) recombination model was included for the generation-recombination mechanism. 4. The Slotboom bandgap narrowing model was included for doping-concentration-dependent bandgap correction [21]. 5. The doping-dependent, transverse field dependence, and high-field saturation mobility models were included to consider impurity scattering, interfacial surface roughness scattering, and coulomb scattering degradations. 6. A ballistic mobility model was considered for quasi-ballistic transport.
The calibration result is shown in Figure 2. The simulation of the following inverter transient response and the 6T-SRAM were achieved using "mixed-mode" in SDEVICE of Sentaurus TCAD.

Results and Discussion
First, to demonstrate the V T tunability of changing the Ge mole fraction (x) in the Si 1-x Ge x channel for N1 CFET, we analyzed the electrical characteristics of PMOS and NMOS on the Si 1-x Ge x composition in the CFET structure. Figure 3a,b show the I D -V G transfer curves of PMOS and NMOS, respectively, in CFET structure with V D = ±0.6 V. For the individual electrical characteristics of NMOS and PMOS, only the targeted MOS's corresponding gate, source, and drain were contacted, and the remaining contact was floating. For example, while extracting the electrical characteristics of the NMOS, the V in (gate of the NMOS), GND (source of the NMOS), and V out (drain of the NMOS) were contacted. In addition, V DD was floating. The mole-fraction-dependent material, Si 1-x Ge x , is set as the channel material for both PMOS and NMOS; that is, the channel is Si if x = 0 and Ge if x = 1. As the Ge mole fraction varies from 0 to 0.5, the I D -V G curves of both PMOS and NMOS shift to the right. However, by comparison, PMOS shows a more noticeable shift on V T . As for NMOS, the shift is relatively negligible. Due to the excellent gate control ability benefitting from the GAA structure, as the x ranged from 0 to 0.5, the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) are nearly unchanged for both NMOS and PMOS. The SS and DIBL are not shown in the figure.

Results and Discussion
First, to demonstrate the VT tunability of changing the Ge mole fraction (x) in the Si1-xGex channel for N1 CFET, we analyzed the electrical characteristics of PMOS and NMOS on the Si1-xGex composition in the CFET structure. Figure 3a,b show the ID-VG transfer curves of PMOS and NMOS, respectively, in CFET structure with VD = ±0.6 V. For the individual electrical characteristics of NMOS and PMOS, only the targeted MOS's corresponding gate, source, and drain were contacted, and the remaining contact was floating. For example, while extracting the electrical characteristics of the NMOS, the Vin (gate of the NMOS), GND (source of the NMOS), and Vout (drain of the NMOS) were contacted. In addition, VDD was floating. The mole-fraction-dependent material, Si1-xGex, is set as the channel material for both PMOS and NMOS; that is, the channel is Si if x = 0 and Ge if x = 1. As the Ge mole fraction varies from 0 to 0.5, the ID-VG curves of both PMOS and NMOS shift to the right. However, by comparison, PMOS shows a more noticeable shift on VT. As for NMOS, the shift is relatively negligible. Due to the excellent gate control ability benefitting from the GAA structure, as the x ranged from 0 to 0.5, the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) are nearly unchanged for both NMOS and PMOS. The SS and DIBL are not shown in the figure.
(a) (b) The VT shift quantified relative to the VT of x = 0 is shown in Figure 4. VT was extracted by the conductance method. VTN has only a 33 mV difference as x increases from 0 to 0.5, whereas the absolute value of VTP decreases linearly with a slope of approximately 5 mV/Ge%. This is because while the electron affinity is 4.05 eV for Si and 4.00 eV for Ge, which are very close, the energy band gaps (Eg) differ, 1.12 eV for Si and 0.66 eV for Ge [17], as shown by the energy band diagrams of Si, SiGe, and Ge in Figure 5. That gap results in the valence band energy (Ev) being pulled toward the vacuum level as the Ge incorporates into the Si channel, whereas the conduction band energy (Ec) remains at nearly the same level.  The V T shift quantified relative to the V T of x = 0 is shown in Figure 4. V T was extracted by the conductance method. V TN has only a 33 mV difference as x increases from 0 to 0.5, whereas the absolute value of V TP decreases linearly with a slope of approximately 5 mV/Ge%. This is because while the electron affinity is 4.05 eV for Si and 4.00 eV for Ge, which are very close, the energy band gaps (E g ) differ, 1.12 eV for Si and 0.66 eV for Ge [17], as shown by the energy band diagrams of Si, SiGe, and Ge in Figure 5. That gap results in the valence band energy (E v ) being pulled toward the vacuum level as the Ge incorporates into the Si channel, whereas the conduction band energy (E c ) remains at nearly the same level.   The Eg of Si1-xGex can be expressed as follows [22]: Since the Eg narrowing of Si1-xGex is mainly attributed to Ev offset, the VTP is more sensitive to the Ge content than VTN. In addition, as can be seen from Equation (1), if we neglect the contribution of Ec changing and the trivial quadratic term, the Eg would have a rate of change of approximately 4.1 meV with respect to the Ge x, which is also very close to the simulation result of the VTP shift.
On the other hand, the adjustment of the threshold voltage by varying Ge content in CFET might result in a change in charge carrier mobility. As shown in Figure 6, we analyzed the effective hole mobility and saturation current (Isat) of PMOS. We focus only on PMOS and hole mobility since VTN is not sensitive to varying Ge mole fractions. The Isat was extracted at VD = VG-VT = 0.6 V. By increasing the Ge mole fraction in Si1-xGex p-channel, the effective hole mobility and Isat are both enhanced linearly. The effective hole mobility increases by 112%, and Isat increases by 115% as the Ge mole fraction increases from 0 to 0.5. For Ge mole fraction higher than 0.5, the hole mobility and Isat would be much higher. As a result, it might not be suitable to adjust VT with Ge mole fraction higher than 0.5.   The Eg of Si1-xGex can be expressed as follows [22]: Since the Eg narrowing of Si1-xGex is mainly attributed to Ev offset, the VTP is more sensitive to the Ge content than VTN. In addition, as can be seen from Equation (1), if we neglect the contribution of Ec changing and the trivial quadratic term, the Eg would have a rate of change of approximately 4.1 meV with respect to the Ge x, which is also very close to the simulation result of the VTP shift.
On the other hand, the adjustment of the threshold voltage by varying Ge content in CFET might result in a change in charge carrier mobility. As shown in Figure 6, we analyzed the effective hole mobility and saturation current (Isat) of PMOS. We focus only on PMOS and hole mobility since VTN is not sensitive to varying Ge mole fractions. The Isat was extracted at VD = VG-VT = 0.6 V. By increasing the Ge mole fraction in Si1-xGex p-channel, the effective hole mobility and Isat are both enhanced linearly. The effective hole mobility increases by 112%, and Isat increases by 115% as the Ge mole fraction increases from 0 to 0.5. For Ge mole fraction higher than 0.5, the hole mobility and Isat would be much higher. As a result, it might not be suitable to adjust VT with Ge mole fraction higher than 0.5. The E g of Si 1-x Ge x can be expressed as follows [22]: E g = 1.12 − 0.41x + 0.008x 2 , x < 0.85, 300 K (1) Since the E g narrowing of Si 1-x Ge x is mainly attributed to E v offset, the V TP is more sensitive to the Ge content than V TN . In addition, as can be seen from Equation (1), if we neglect the contribution of E c changing and the trivial quadratic term, the E g would have a rate of change of approximately 4.1 meV with respect to the Ge x, which is also very close to the simulation result of the V TP shift.
On the other hand, the adjustment of the threshold voltage by varying Ge content in CFET might result in a change in charge carrier mobility. As shown in Figure 6, we analyzed the effective hole mobility and saturation current (I sat ) of PMOS. We focus only on PMOS and hole mobility since V TN is not sensitive to varying Ge mole fractions. The I sat was extracted at V D = V G -V T = 0.6 V. By increasing the Ge mole fraction in Si 1-x Ge x p-channel, the effective hole mobility and I sat are both enhanced linearly. The effective hole mobility increases by 112%, and I sat increases by 115% as the Ge mole fraction increases from 0 to 0.5. For Ge mole fraction higher than 0.5, the hole mobility and I sat would be much higher. As a result, it might not be suitable to adjust V T with Ge mole fraction higher than 0.5. As the VTP is much more adjustable by varying the Ge content, it is justifiable to use Si as the channel material of NMOS and adjust only the VT by changing x in the Si1-xGex pchannel for designing the N1 CFET inverter. By performing a single WFM (for adjusting VTN) and Ge content method (for adjusting VTP) together on CFETs, we could relieve the lack of spacing for dual WFM. Therefore, we then tuned the work function of the shared gate of the N1 CFET to let the Si NMOS possess an expected VTN. In this case, we set the work function to 4.49 eV to let VTN = 0.25 V. Subsequently, we varied the x of the Si1-xGex PMOS to match VTP and VTN. Notice that the ID-VG curves in Figure 3 are with the N1 CFET, whose work function of the shared gate was set. As can be seen from Figure 3, the PMOS with Si0.7Ge0.3 has a VTP of −0.25 V, which matches the Si NMOS. Figure 7 shows the ID-VD output characteristics of the Si0.7Ge0.3 PMOS and the Si NMOS in the N1 CFET structure with VG ranging from ±0.2 to ±0.8 V at a step of ±0.1 V. Their output currents are comparable, though the PMOS has a longer CGP which may lead to a more significant total resistance. That implies the design of more stacks of PMOS than NMOS can overcome the degradation.  As the V TP is much more adjustable by varying the Ge content, it is justifiable to use Si as the channel material of NMOS and adjust only the V T by changing x in the Si 1-x Ge x p-channel for designing the N1 CFET inverter. By performing a single WFM (for adjusting V TN ) and Ge content method (for adjusting V TP ) together on CFETs, we could relieve the lack of spacing for dual WFM. Therefore, we then tuned the work function of the shared gate of the N1 CFET to let the Si NMOS possess an expected V TN . In this case, we set the work function to 4.49 eV to let V TN = 0.25 V. Subsequently, we varied the x of the Si 1-x Ge x PMOS to match V TP and V TN . Notice that the I D -V G curves in Figure 3 are with the N1 CFET, whose work function of the shared gate was set. As can be seen from Figure 3, the PMOS with Si 0 . 7 Ge 0 . 3 has a V TP of −0.25 V, which matches the Si NMOS. Figure 7 shows the I D -V D output characteristics of the Si 0 . 7 Ge 0 . 3 PMOS and the Si NMOS in the N1 CFET structure with V G ranging from ±0.2 to ±0.8 V at a step of ±0.1 V. Their output currents are comparable, though the PMOS has a longer CGP which may lead to a more significant total resistance. That implies the design of more stacks of PMOS than NMOS can overcome the degradation. As the VTP is much more adjustable by varying the Ge content, it is justifiable to use Si as the channel material of NMOS and adjust only the VT by changing x in the Si1-xGex pchannel for designing the N1 CFET inverter. By performing a single WFM (for adjusting VTN) and Ge content method (for adjusting VTP) together on CFETs, we could relieve the lack of spacing for dual WFM. Therefore, we then tuned the work function of the shared gate of the N1 CFET to let the Si NMOS possess an expected VTN. In this case, we set the work function to 4.49 eV to let VTN = 0.25 V. Subsequently, we varied the x of the Si1-xGex PMOS to match VTP and VTN. Notice that the ID-VG curves in Figure 3 are with the N1 CFET, whose work function of the shared gate was set. As can be seen from Figure 3, the PMOS with Si0.7Ge0.3 has a VTP of −0.25 V, which matches the Si NMOS. Figure 7 shows the ID-VD output characteristics of the Si0.7Ge0.3 PMOS and the Si NMOS in the N1 CFET structure with VG ranging from ±0.2 to ±0.8 V at a step of ±0.1 V. Their output currents are comparable, though the PMOS has a longer CGP which may lead to a more significant total resistance. That implies the design of more stacks of PMOS than NMOS can overcome the degradation.   Figure 8a,b show the analysis of the electrical characteristics including V TP and subthreshold swing (SS) of Si 1-x Ge x PMOS with different L G from 12 nm to 6 nm. As L G values shrink down to below 8 nm, the assumption of the 5 mV/Ge% V TP relation would become unsuitable. The assumption shows a deviation of less than 4%, with L G ranging from 12 nm to 8 nm. However, the deviation becomes larger than 10% with L G values of 7 nm and below. In Figure 7b, SS would increase with a higher Ge mole fraction, but the increase is ignorable with L G of 12 nm and 11 nm. As the L G becomes smaller, the increase of SS with respect to Ge mole fraction would then get more obvious, but still acceptable when L G is larger than 8 nm. However, at L G smaller than 8 nm, SS becomes no longer suitable. In conclusion, the proposed Ge content method for adjusting V T can be applied on CFET device with L G scaled down to 8 nm.
Nanomaterials 2022, 12, x 7 of 11 unsuitable. The assumption shows a deviation of less than 4%, with LG ranging from 12 nm to 8 nm. However, the deviation becomes larger than 10% with LG values of 7 nm and below. In Figure 7b, SS would increase with a higher Ge mole fraction, but the increase is ignorable with LG of 12 nm and 11 nm. As the LG becomes smaller, the increase of SS with respect to Ge mole fraction would then get more obvious, but still acceptable when LG is larger than 8 nm. However, at LG smaller than 8 nm, SS becomes no longer suitable. In conclusion, the proposed Ge content method for adjusting VT can be applied on CFET device with LG scaled down to 8 nm.
(a) (b) The N1 CFET inverter constructed with Si1-xGex PMOS and Si NMOS was also analyzed. Figure 9a shows the voltage transfer curves of the N1 CFET inverter with x of the Si1-xGex PMOS varying from 0 to 0.5 and the VDD of 0.6 V. The switching thresholds (VM) of the VTCs were extracted as the voltage where VIN = VOUT, as shown in Figure 9b. The VM of the N1 CFET inverter at VDD of 0.5, 0.6, and 0.7 V increase monotonically with increasing x of the Si1-xGex PMOS. The dotted lines represent where the VM equals VDD/2; in this case, the N1 CFET inverter with x = 0.3 has the VM nearly VDD/2 for all three VDD due to the VT and current matching. Figure 10 presents the transient response of the designed N1 CFET inverter with Si0.7Ge0.3 PMOS and Si NMOS under a ~14GHz operation. The transient response was performed with fan-out of 3 (FO3) and without load capacitance. The designed N1 CFET inverter exhibits propagation delay times from low to high (τplh) and from high to low (τphl) of ~1.27 ps and ~17.3ps, respectively. The propagation delay times were extracted at 0.5VDD. The designed N1 CFET inverter exhibits propagation delay times from low to high (τ plh ) and from high to low (τ phl ) of~1.27 ps and~17.3 ps, respectively. The propagation delay times were extracted at 0.5 V DD .   Moreover, the designed N1 CFET inverter with Si0.7Ge0.3 PMOS and Si NMOS was used to build a 6T-SRAM cell. The 6T-SRAM cell was constructed with two N1 CFET inverters and two NMOS access transistors. The butterfly curves of the 6T-SRAM built with N1 CFET inverters at VDD of 0.5, 0.6, and 0.7 V are shown in Figure 11. Excellent stability is present with a large static noise margin (SNM) of ~120 mV as VDD down to 0.5 V, and the SNM values are ~140 and ~155 mV at VDD of 0.6 and 0.7 V, respectively. Moreover, the designed N1 CFET inverter with Si 0 . 7 Ge 0 . 3 PMOS and Si NMOS was used to build a 6T-SRAM cell. The 6T-SRAM cell was constructed with two N1 CFET inverters and two NMOS access transistors. The butterfly curves of the 6T-SRAM built with N1 CFET inverters at V DD of 0.5, 0.6, and 0.7 V are shown in Figure 11. Excellent stability is present with a large static noise margin (SNM) of~120 mV as V DD down to 0.5 V, and the SNM values are~140 and~155 mV at V DD of 0.6 and 0.7 V, respectively. Nanomaterials 2022, 12, x 9 of 11 Figure 11. The butterfly curves of the 6T-SRAM cell, which was constructed with two designed N1 CFET inverters and two NMOS access transistors. The SNM of ~120 mV as VDD down to 0.5 V is obtained.

Conclusions
In this study, we proposed the VT adjustment method by controlling Ge content in the SiGe channel and demonstrated it on N1 CFET by TCAD simulation. The PMOS shows a high sensitivity on the Ge mole fraction since the incorporation of Ge pulls Ev towards the vacuum level but has little effect on Ec. The simulation result shows the VTP has a change rate of approximately 5 mV/Ge%, which is close to that derived from the Eg relation. The N1 CFET designed by the Ge content method presents a good VTC and nearly VDD/2 VM. Well-performing inverter transient response is also presented. In addition, the 6T-SRAM shows a large SNM of ~120 mV as VDD down to 0.5 V. With the help of the  Figure 11. The butterfly curves of the 6T-SRAM cell, which was constructed with two designed N1 CFET inverters and two NMOS access transistors. The SNM of~120 mV as V DD down to 0.5 V is obtained.

Conclusions
In this study, we proposed the V T adjustment method by controlling Ge content in the SiGe channel and demonstrated it on N1 CFET by TCAD simulation. The PMOS shows a high sensitivity on the Ge mole fraction since the incorporation of Ge pulls E v towards the vacuum level but has little effect on E c . The simulation result shows the V TP has a change rate of approximately 5 mV/Ge%, which is close to that derived from the E g relation. The N1 CFET designed by the Ge content method presents a good VTC and nearly V DD /2 V M . Well-performing inverter transient response is also presented. In addition, the 6T-SRAM shows a large SNM of~120 mV as V DD down to 0.5 V. With the help of the proposed Ge content method, the V T tuning flexibility can be significantly improved for the highly scaled device.

Data Availability Statement:
The data presented in this study are available on request from the corresponding author.