Effect of Back-Gate Voltage on the High-Frequency Performance of Dual-Gate MoS2 Transistors

As an atomically thin semiconductor, 2D molybdenum disulfide (MoS2) has demonstrated great potential in realizing next-generation logic circuits, radio-frequency (RF) devices and flexible electronics. Although various methods have been performed to improve the high-frequency characteristics of MoS2 RF transistors, the impact of the back-gate bias on dual-gate MoS2 RF transistors is still unexplored. In this work, we study the effect of back-gate control on the static and RF performance metrics of MoS2 high-frequency transistors. By using high-quality chemical vapor deposited bilayer MoS2 as channel material, high-performance top-gate transistors with on/off ratio of 107 and on-current up to 179 μA/μm at room temperature were realized. With the back-gate modulation, the source and drain contact resistances decrease to 1.99 kΩ∙μm at Vbg = 3 V, and the corresponding on-current increases to 278 μA/μm. Furthermore, both cut-off frequency and maximum oscillation frequency improves as the back-gate voltage increases to 3 V. In addition, a maximum intrinsic fmax of 29.7 GHz was achieved, which is as high as 2.1 times the fmax without the back-gate bias. This work provides significant insights into the influence of back-gate voltage on MoS2 RF transistors and presents the potential of dual-gate MoS2 RF transistors for future high-frequency applications.


Introduction
Since the first exfoliation of atomically thin graphene [1], two dimensional (2D) materials have demonstrated a wide range of remarkable properties for applications in future ubiquitous electronics [2,3]. Compared to bulk materials, their atomic-scale thickness provides a greater degree of electrostatic control, demonstrating the possibility of ultra-short channel devices with low power consumption [4]. As the most widely studied 2D material, graphene has shown great potential for device applications including high-frequency electronics, flexible electronics, spintronics, nanoelectromechanical systems, and energy storage due to its unique physical properties [5][6][7][8][9][10][11][12]. However, graphene does not have a band gap to limit its application in digital logic devices, and it also limits the maximum oscillation frequency of graphene radio-frequency (RF) transistors. Although band gap can be opened in graphene by artificial nanostructuring, chemical functionalization, etc., those processes add extra complexities with respect to practical applications [13]. Alternatively, another class of 2D material, called transition metal dichalcogenides (TMDCs) (MoS 2 , WS 2 , MoSe 2 , and WSe 2 ), not only exhibits many graphene-like properties, such as mechanical flexibility, electrical properties, chemical stability, and the absence of dangling bonds, but also possesses a substantial band gap. TMDCs benefit from a rich pool of elements, and thus they can significantly adjust their electrical properties from metal to semiconductor by forming different compounds. A distinct feature of TMDC semiconductors is that the corresponding energy band structure changes from an indirect band gap to a direct band gap when the material thickness decreases from bulk material to monolayer. They show a wide range of bandgap modulation capability because of rich choices of chemical components, which enables the electronic application of various kinds. As the most studied TMDC material, MoS 2 has a non-zero band gap structure similar to bulk silicon, making it an ideal choice for making next-generation electronic and optoelectronic applications [4,[14][15][16][17][18][19][20].
With technological advancements, the high-frequency performance of MoS 2 devices has attracted tremendous attention [16,18,[21][22][23][24]. The high-frequency performance of MoS 2 RF transistors has been improved through optimizing structure such as self-aligned gate, embedded gate and edge-contacted, etc. [24][25][26]. In 2014, exfoliated MoS 2 RF transistors with self-aligned gate demonstrated intrinsic cut-off frequency f T of 42 GHz and maximum oscillation frequency f max of 50 GHz were reported [25]. In 2015, Krasnozhon et al. introduced edge-contacted in exfoliated trilayer MoS 2 RF transistors, obtaining a high extrinsic f T of 6 GHz and intrinsic f T of 25 GHz [26]. In 2017, with an optimized embedded gate structure, chemical vapor deposition (CVD) monolayer MoS 2 transistors with extrinsic f T of 3.3 GHz and f max of 9.8 GHz were fabricated [24]. In 2018, based on high-quality CVD bilayer MoS 2 , high-frequency MoS 2 transistors with extrinsic maximum oscillation frequency of 23 GHz were demonstrated [16]. Gigahertz frequency mixer and amplifier based on MoS 2 high-frequency transistors were also constructed for potential RF circuit applications [16,27]. Those works demonstrated the potential of 2D MoS 2 for future novel high-frequency electronics. Although the high-frequency performance of MoS 2 RF transistors has made exciting advances, its cutoff frequency and maximum oscillation frequency are still lower than those of modern Si transistors, and the high-frequency performance of dual-gate MoS 2 transistors has not yet been reported.
In this dual-gate structure, the source and drain contact resistances can be modulated via the back-gate voltage, and the influence of the contact resistance on the direct-current (DC) and high-frequency performance of the device can be clearly resolved [28]. Bolshakov et al. presented a near-ideal subthreshold swing of~60 mV/dec and a high field effect mobility of 100 cm 2 /Vs based on dual-gate MoS 2 transistors with sub−10 nm top-gate dielectrics [29]. Lee [31]. The dual-gate structure could also be used to investigate the effect of different dielectric interface on the device performance [32]. In addition, based on the dualgate structure, graphene RF transistors with improved high-frequency performance by reducing the contact resistance using electrostatic doping have been demonstrated [33,34]. Thus, the influence of back-gate voltage on the high-frequency performance of MoS 2 RF transistors needs further investigation, which is of great significance for further improving the RF performance of MoS 2 transistors.
In this study, we fabricated dual-gate MoS 2 RF transistors with a top-gate length of 190 nm based on the CVD grown bilayer MoS 2 . The static and high-frequency characteristics of dual-gate devices were systematically investigated. The contact resistances of the fabricated dual-gate devices under different back-gate voltages were extracted. A clear modulation of contact resistance R c under the electrostatic doping of back-gate was demonstrated. Both DC and RF performance were improved under the electrostatic doping of back-gate. The electrical measurement of our dual-gate high-frequency MoS 2 transistors at V bg = 3 V demonstrated a large current density of 278 µA/µm, a high intrinsic cut-off frequency of 19 GHz and maximum oscillation frequency of 29.7 GHz.

Materials and Methods
Chemical-vapor-deposited bilayer MoS 2 was used as the channel material in the dualgate MoS 2 RF transistors as it has higher carrier mobility, lower contact resistance and Nanomaterials 2021, 11, 1594 3 of 11 improved low-frequency noise when compared with CVD monolayer MoS 2 [16,27,35]. Additionally, the CVD method is one of the most promising methods for synthesizing large areas and high-quality MoS 2 . The CVD bilayer MoS 2 films were grown on soda-limesilica glass substrates with 1.4 g sulfur and 1.5 mg MoO 3 as the precursors at atmospheric pressure. The details about the CVD bilayer growth process, material imaging and crystal structure characterization have been reported in our previous works [16,27]. After the CVD growth process, bilayer MoS 2 films were transferred onto highly resistive Si substrates with atomic-layer-deposited (ALD) 20-nm HfLaO. Here, high-resistance Si was used as the back-gate electrode and ALD HfLaO as the back-gate dielectric. As reported in previous work [16,36,37], HfLaO with high dielectric constant could provide improved interface quality and better electrostatic control with the MoS 2 channel, which is helpful for improving the DC and RF performance of the MoS 2 transistors. Figure 1 illustrates the fabrication process of dual-gate MoS 2 transistors. The fabrication of the MoS 2 devices typically starts after the MoS 2 films are transferred on top of the HfLaO/Si substrates. Figure 2a presents the MoS 2 films on HfLaO/Si substrates after being transferred. Then, as shown in Figure 1b, 20/60 nm Ni/Au metal stacks were deposited by electron beam evaporation (EBE) as the source and drain contact electrodes of MoS 2 dual-gate transistors. In this process, the samples were loaded into the E-beam evaporator (ALPHA-PLUSCO.Ltd., Ebeam-500S Pohang, Korea), and it was waited until the system reaches the pressure lower than 9 × 10 −6 torr to start the deposition. The deposition rate of 20 nm Ni and 60 nm Au was used as 1 Å/s for both materials. The electrical isolation between different transistors was achieved by performing O 2 plasma etching for 30 s under an RF power of 50 W with a mixed gas flow of 20 sccm O 2 and 80 sccm Ar.

Materials and Methods
Chemical-vapor-deposited bilayer MoS2 was used as the channel material in the dual-gate MoS2 RF transistors as it has higher carrier mobility, lower contact resistance and improved low-frequency noise when compared with CVD monolayer MoS2 [16,27,35]. Additionally, the CVD method is one of the most promising methods for synthesizing large areas and high-quality MoS2. The CVD bilayer MoS2 films were grown on soda-lime-silica glass substrates with 1.4 g sulfur and 1.5 mg MoO3 as the precursors at atmospheric pressure. The details about the CVD bilayer growth process, material imaging and crystal structure characterization have been reported in our previous works [16,27]. After the CVD growth process, bilayer MoS2 films were transferred onto highly resistive Si substrates with atomic-layer-deposited (ALD) 20-nm HfLaO. Here, high-resistance Si was used as the back-gate electrode and ALD HfLaO as the back-gate dielectric. As reported in previous work [16,36,37], HfLaO with high dielectric constant could provide improved interface quality and better electrostatic control with the MoS2 channel, which is helpful for improving the DC and RF performance of the MoS2 transistors. Figure  1 illustrates the fabrication process of dual-gate MoS2 transistors. The fabrication of the MoS2 devices typically starts after the MoS2 films are transferred on top of the HfLaO/Si substrates. Figure 2a presents the MoS2 films on HfLaO/Si substrates after being transferred. Then, as shown in Figure1b, 20/60 nm Ni/Au metal stacks were deposited by electron beam evaporation (EBE) as the source and drain contact electrodes of MoS2 dual-gate transistors. In this process, the samples were loaded into the E-beam evaporator (ALPHA-PLUSCO.Ltd., Ebeam-500S Pohang, Korea), and it was waited until the system reaches the pressure lower than 9 × 10 −6 torr to start the deposition. The deposition rate of 20 nm Ni and 60 nm Au was used as 1 Ǻ/s for both materials. The electrical isolation between different transistors was achieved by performing O2 plasma etching for 30 s under an RF power of 50 W with a mixed gas flow of 20 sccm O2 and 80 sccm Ar. The top gate dielectric of the transistors is an important medium for static control of the channel through the top gate electrode, and it has a very important influence on the static and high-frequency performance of the device. The top-gate dielectric is similar to the substrate dielectric, which will scatter the MoS2 channel carriers, and the dielectric defects will also capture and release channel electrons. Because of the lack of dangling bonds on the surface of 2D materials, growing high-quality dielectrics on top of MoS2 has always been a challenging process [38,39], due to the adsorption of the ALD precursors with an exposure dose of 800 μC/cm . Then, the pattern was developed in a 3:1 ratio of isopropyl alcohol (IPA) to methyl isobutyl ketone (MIBK) for 50 s, rinsed with IPA for 60 s, and dried with nitrogen gas. After the EBE deposition of electrodes, lift-off was performed in a beaker of acetone heated to 50 °C for 30 min. Then, the sample was rinsed with IPA and dried with a nitrogen flow. Figure 2b-d display the top scanning electron microscope (SEM) views of the dual-gate MoS2 RF transistors with 190 nm top-gate length. The width of the two-fingers top-gate is 30 μm.  Figure 3a,c show the transfer characteristics of the dual-gate MoS2 transistor from both the back and top-gate configuration. High on/off ratios greater than 10 7 were achieved for both the back and top-gate modulation. Compared to graphene transistors, this superior on/off ratio is due to the larger band gap [40].  The top gate dielectric of the transistors is an important medium for static control of the channel through the top gate electrode, and it has a very important influence on the static and high-frequency performance of the device. The top-gate dielectric is similar to the substrate dielectric, which will scatter the MoS 2 channel carriers, and the dielectric defects will also capture and release channel electrons. Because of the lack of dangling bonds on the surface of 2D materials, growing high-quality dielectrics on top of MoS 2 has always been a challenging process [38,39], due to the adsorption of the ALD precursors on a 2D MoS 2 surface often being more difficult than on conventional semiconductors with a 3D lattice, where plenty of dangling bonds are able help the adsorption during the ALD process. In this work, a two-step seed and growth processes were used in the formation of high-k topgate dielectrics. First, a 2-nm Al layer was deposited on the MoS 2 surface by EBE and then naturally oxidized in the air to form a 6-nm Al 2 O 3 layer. Then, 11 nm of HfO 2 was deposited by ALD using O 3 as the O source and tetrakis-ethylmethylaminohafnium (TEMAHf) as the Hf source. Finally, the top-gate metal was formed with 20 nm Ni/60 nm Au metal stack by EBE. In the above fabrication process, the patterns of the source, drain and gate electrodes were written using electron beam lithography. In this process, poly(methylmethacrylate) (PMMA) 950 A4 was spin-coated on the substrates at 3000 rpm for 60 s and baked at 180 • C for 180 s. The electron beam was set to a 3 nA current with an exposure dose of 800 µC/cm 2 . Then, the pattern was developed in a 3:1 ratio of isopropyl alcohol (IPA) to methyl isobutyl ketone (MIBK) for 50 s, rinsed with IPA for 60 s, and dried with nitrogen gas. After the EBE deposition of electrodes, lift-off was performed in a beaker of acetone heated to 50 • C for 30 min. Then, the sample was rinsed with IPA and dried with a nitrogen flow.  Figure 3a,c show the transfer characteristics of the dual-gate MoS 2 transistor from both the back and top-gate configuration. High on/off ratios greater than 10 7 were achieved for both the back and top-gate modulation. Compared to graphene transistors, this superior on/off ratio is due to the larger band gap [40]. Figure 3b,d show the output characteristics under varied back and top-gate voltages. The gate voltages were varied from −3 V to 3 V with a 0.5 V step. Maximum on-current densities were observed at V ds = 4 V are 277 µA/µm and 179 µA/µm for back-gate and top-gate modulation, respectively. The achieved maximum on-current density from back-gate is about 1.6 times the magnitude of that from the top-gate. This comes from the different configuration of back-gate and top-gate devices. As shown in Figure 1d, it can be seen that the highly resistive Si substrate has global control over the entire bilayer MoS 2 film. Since the channel carriers in the bilayer MoS 2 films accumulate with increasing back-gate voltage, it can be assumed that the bilayer MoS 2 is electrically doped under the effect of the back-gate voltage, which further leads to a reduction in the contact resistance between the source/drain (Ni/Au) and the bilayer MoS 2 film. In the case of top-gate configuration, the gate can only modulate the MoS 2 films underneath the gate metal [28,33,34]. In addition to the different gate structures, the different top and bottom dielectric layer may also play a critical role in determining the difference of DC measurement [19,32,41] and which need further investigation. In addition, a field-effect mobility of 15.8 cm 2 /Vs was obtained from back-gate measurement by using the relation µ FE = g m L WC ox V ds , where the back-gate capacitance C ox is 0.8 µF/cm 2 .   Figure 4a shows the transfer curves of a dual-gate MoS2 transistor with sweeping topgate voltage at varied back-gate voltages. With the back-gate voltage increasing from 0 V to 3 V, the on-current density increases from 166 to 278 μΑ/μm, and the threshold voltage Vth negatively shifts from 1.1 to 0.1 V. To estimate contact resistances of dual-gate MoS2 transistors under different back-gate voltages, an interpolation method reported in previous work was adopted [35,42]. In this interpolation method, contact resistances at different Vbg were extracted by extrapolating the drain-to-source resistance vs. 1/(Vtg − Vth), which contains the contribution from metal/MoS2 contact and the regions between topgate and source/drain electrodes. The dependence of the contact resistances versus Vbg is   Figure 4a shows the transfer curves of a dual-gate MoS 2 transistor with sweeping topgate voltage at varied back-gate voltages. With the back-gate voltage increasing from 0 V to 3 V, the on-current density increases from 166 to 278 µA/µm, and the threshold voltage V th negatively shifts from 1.1 to 0.1 V. To estimate contact resistances of dual-gate MoS 2 transistors under different back-gate voltages, an interpolation method reported in previous work was adopted [35,42]. In this interpolation method, contact resistances at different V bg were extracted by extrapolating the drain-to-source resistance vs. 1/(V tg − V th ), which contains the contribution from metal/MoS 2 contact and the regions between top-gate and source/drain electrodes. The dependence of the contact resistances versus V bg is shown in Figure 4b. The extracted contact resistance is 5.5 kΩ·µm at V bg = 0 V, and decreases to 1.99 kΩ·µm at V bg = 3 V. The reduced R c and increased on-current at larger V bg can be attributed to the increased electrostatic doping carriers of bilayer MoS 2 in both the MoS 2 /metal contact region and channel region [28,31,33,34]. can be attributed to the increased electrostatic doping carriers of bilayer MoS2 in both the MoS2/metal contact region and channel region [28,31,33,34].

RF Characterization
The high-frequency performance of dual-gate MoS2 transistors can be evaluated by the cutoff frequency (fT) and the maximum frequency of oscillation (fmax), which can be obtained from the measured S-parameters [43,44]. The cutoff frequency is where the shortcircuit current gain |h21| equals unity. The short-circuit current gain |h21| can be defined as: Similarly, the maximum frequency of oscillation was found when the unilateral power gain U was unity, where the U can be defined as: where K is the stability factor and  (1) and (2). As shown in Figure 5a,c, the fT and fmax of the 190 nm MoS2 RF transistors with back-gate floating were 4.6 and 11.9 GHz, respectively. The achieved fT of 4.6 GHz and fmax of 11.9 GHz were also further verified using Gummel's method [45] and maximum available power gain (MAG) [46], as shown in Figure 5b,d. The obtained cut-off frequency and maximum oscillation frequency were consistent with our previous reported work [16], demonstrating the potential of CVD bilayer MoS2 for large-scale highfrequency circuit applications [27,35].

RF Characterization
The high-frequency performance of dual-gate MoS 2 transistors can be evaluated by the cutoff frequency (f T ) and the maximum frequency of oscillation (f max ), which can be obtained from the measured S-parameters [43,44]. The cutoff frequency is where the short-circuit current gain |h 21 | equals unity. The short-circuit current gain |h 21 | can be defined as: Similarly, the maximum frequency of oscillation was found when the unilateral power gain U was unity, where the U can be defined as: where K is the stability factor and K = 1+|S 11 . On-chip microwave measurements from 100 MHz to 30 GHz of the dual-gate MoS 2 RF transistors were carried out using vector network analyzers (N5225A, Agilent (Keysight), Colorado Springs, CA, USA). Before the S-parameter measurement, the on-chip measurement system was calibrated according to the short-open-load-through (SOLT) method using standard impedance calibration samples. Then S parameters of the MoS 2 transistors were measured, and the short-circuit current gain and the unilateral power gain can be calculated by Equations (1) and (2). As shown in Figure 5a,c, the f T and f max of the 190 nm MoS 2 RF transistors with back-gate floating were 4.6 and 11.9 GHz, respectively. The achieved f T of 4.6 GHz and f max of 11.9 GHz were also further verified using Gummel's method [45] and maximum available power gain (MAG) [46], as shown in Figure 5b,d. The obtained cut-off frequency and maximum oscillation frequency were consistent with our previous reported work [16], demonstrating the potential of CVD bilayer MoS 2 for large-scale high-frequency circuit applications [27,35]. Although the implementation of the standard calibration method can move the measurement reference plane from the internal receiver of the vector network analyzer to the tip of the ground-signal-ground (GSG) probe, the parasitic capacitance, inductance, and resistance of the test electrodes also have a significant effect on the obtained S-parameters [27,47]. To eliminate the influence of the test electrodes on the measured S-parameters and to obtain the intrinsic RF performance of the MoS2 RF transistor, this work uses the standard "open" and "short" structures for de-embedding [25]. Then, the measured S-parameters were converted to Y-parameters, and the de-embedding process was performed under the following equation: Although the implementation of the standard calibration method can move the measurement reference plane from the internal receiver of the vector network analyzer to the tip of the ground-signal-ground (GSG) probe, the parasitic capacitance, inductance, and resistance of the test electrodes also have a significant effect on the obtained S-parameters [27,47]. To eliminate the influence of the test electrodes on the measured S-parameters and to obtain the intrinsic RF performance of the MoS 2 RF transistor, this work uses the standard "open" and "short" structures for de-embedding [25]. Then, the measured S-parameters were converted to Y-parameters, and the de-embedding process was performed under the following equation: , where Y DUT stands for the Y-parameter of the measured transistors. The short-circuit current gain, unilateral power gain, and maximum available power gain versus frequency after de-embedding of the MoS 2 transistors with gate length of 190 nm are shown in Figure 6. Intrinsic f T and f max of 18 and 14.1 GHz were achieved, respectively. To improve the high-frequency performance of MoS2 RF transistors, we can derive the dependence of fT and fmax on the physical parameters of the device through the smallsignal equivalent circuit model, and write them as Equations (3) and (4). To improve the high-frequency performance of MoS 2 RF transistors, we can derive the dependence of f T and f max on the physical parameters of the device through the small-signal equivalent circuit model, and write them as Equations (3) and (4).
where g m is the transconductance and represents the channel current controlling capability of the gate voltage, g ds is the output conductance, C gs and C gd is the gate-to-source and gateto-drain capacitance, respectively. R s , R d and R g are the source, drain, and gate resistances. From Equations (3) and (4), we can see that g m , g ds , R s and R d play an important role in the high-frequency performance of RF transistors. Therefore, back-gate modulation could be an effective approach for improving the high-frequency performance of MoS 2 RF transistors. Figure 7 shows the intrinsic and extrinsic cut-off frequency and maximum oscillation frequency of the device as a function of the back-gate voltage. As shown in Figure 7a,c, when the back-gate voltage changes from 0 V to 3 V, the extrinsic and intrinsic cut-off frequencies before and after de-embedding increase from 4.6 to 6 GHz and from 18 to 19 GHz, respectively, demonstrating an obtained peak f T increase as the increase of back-gate voltage. The improvement of f T can be attributed to the reduced contact resistance thus improve transconductance and on-current with increasing V bg , as shown in Figure 4. From the intrinsic f T of 19 GHz at V bg =3 V, a saturation velocity of 2.3 × 10 6 cm/s is obtained, which is comparable with previously reported works [16,25]. Similarly, when the back-gate increases from 0 to 3 V, the extrinsic and intrinsic maximum oscillation frequencies before and after de-embedding increase from 12 to 27 GHz and from 13.4 to 29.7 GHz, respectively. Because the dependence of f max on output conductance is more sensitive, the increase of f max with increasing V bg is larger than f T [34]. Furthermore, a comparison between reported MoS 2 RF transistors with comparable gate length [22][23][24] is listed in Table 1, below, demonstrating the advantage of dual-gate MoS 2 RF transistors.

Conclusions
In summary, for the first time, a systematic investigation of a dual-gate MoS 2 RF transistor based on CVD bilayer MoS 2 was performed. Improved on-current and contact resistance performance by optimizing the back-gate voltage were demonstrated. A high on-current of 278 µA/µm and a low contact resistance of 1.99 kΩ·µm were achieved at V bg = 3 V. The cut-off frequency and maximum oscillation frequency can be improved by back-gate modulation. Extrinsic and intrinsic cutoff frequency of 6 and 19 GHz were demonstrated for a gate length of 190 nm at V bg = 3 V. The intrinsic maximum oscillation frequency can become 2.1 times as high as the f max without a back-gate bias. The results presented here indicate that tuning the back-gate voltage provides an effective way to boost f T and f max and give an insight into the high-frequency performance of MoS 2 RF transistors.