Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related μFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole μFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.


Introduction
Metal-oxide Thin film transistors (TFTs)  have drawn considerable attention due to their high mobility, low fabrication temperature, and simple fabrication process, making them suitable for advanced display [1][2][3][4][5][6] and monolithic three-dimensional (3D) integrated circuit (IC) [15][16][17][18][19][20][21] on amorphous inter-metal-dielectric (IMD) of a Si chip. To reach low DC power consumption, both high performance n-and p-type TFTs are necessary to form the complementary metal-oxide-semiconductor (CMOS) logic. Although high-performance n-TFTs with high field-effect mobility (µ FE ), sharp subthreshold swing (SS), and large on-current/off-current (I ON /I OFF ) values [12][13][14][15] have been reported, achieving reasonable performance p-TFTs is much more challenging [16,17,36,37]. Moreover, a top-gate structure is more suitable than a conventional bottom-gate device for high integration density and easy fabrication [24][25][26]. Previously, we have reported the bottom-gate SnO p-TFT, which has higher µ FE than Cu 2 O p-TFT [16,17]. In the current study, we further used the SnO channel to fabricate top-gate coplanar nanosheet p-TFT. Because the gate insulator was deposited after the SnO layer, the deposition and post-annealing conditions are crucial to device performance. This is because the p-type SnO is highly sensitive to oxygen partial pressure (O pp ) and annealing temperature, and can be easily oxidized into oxygen-rich Sn 2 O 3 , Sn 3 O 4 , or SnO 2 [27][28][29]. Moreover, the weak Sn-O bond enthalpy [38] facilitates Sn diffusion into high-dielectric-constant (high-κ) HfO 2 insulator at elevated temperature, Nanomaterials 2021, 11, 92 2 of 11 thus degrading device performance. In this study, the above challenges were successfully overcome, and high-performance top-gate nanosheet SnO p-TFT was achieved with high µ FE of 4.4 cm 2 /Vs, large I ON /I OFF of 1.2 × 10 5 , and sharp SS of 526 mV/decade, indicating a high potential for future monolithic 3D and brain-mimicking IC applications [15,[17][18][19][20][21].

Materials and Methods
The coplanar top-gate nanosheet SnO p-TFTs were fabricated on the Si wafer with a 500-nm-thick SiO 2 IMD layer on Si wafer. The 7-nm-thick nanosheet SnO layer was deposited through reactive sputtering with 50 W DC power from a Sn target under O pp values of 14.2%, 25%, and 33.3% ambient, respectively. All the SnO p-TFT samples were annealed under 200 • C in N 2 ambient for 45 min. Next, 40-nm high work-function Ni was deposited using an e-gun evaporator for the Schottky-barrier source and drain electrodes [39,40]. Subsequently, 50-nm HfO 2 gate dielectric was deposited by e-beam evaporation with a rate of 0.2 Å/sec. HfO 2 post-annealing was performed in N 2 ambient at 100 • C and 200 • C. Finally, 50-nm gate electrode Al was deposited and patterned. The transistor's length and width were 50 and 400 µm, respectively. The current-voltage characteristics of top-gate SnO p-TFT were measured through the HP4155B parameter analyzer and a probe station. The field-effect mobility values (µ FE ), subthreshold slope (SS) and on-current/off-current (I ON /I OFF ) values were extracted at a standard and small V DS = −0.1 V. The cross-sectional image of device structure was obtained from FEI Talos F200X high-resolution transmission electron microscope (TEM). The surface roughness of HfO 2 films were obtained via Atomic Force Microscope (AFM) using DIMENSION 3100. The X-ray photoelectron spectroscopy (XPS) analyses of HfO 2 films and SnO films were executed by Thermo Nexsa. The secondary ion mass spectrometry (SIMS) depth profiles of Sn, Hf and O atoms were obtained by CAMECA IMS-6fE7. Figure 1a illustrates the top-view photograph of top-gate nanosheet SnO p-TFT, where the light-reflective Al metal-gate is on the top of the device. Figure 1b depicts the crosssectional transmission electron microscope (TEM) image of the device structure with top Al-metal-gate, HfO 2 gate-dielectric, and p-type channel SnO on SiO 2 IMD. The thickness of Al, HfO 2 , and nanosheet SnO is 50, 50, and 7 nm, respectively. Nanomaterials 2021, 11, x FOR PEER REVIEW 2 of 11 dized into oxygen-rich Sn2O3, Sn3O4, or SnO2 [27][28][29]. Moreover, the weak Sn-O bond enthalpy [38] facilitates Sn diffusion into high-dielectric-constant (high-κ) HfO2 insulator at elevated temperature, thus degrading device performance. In this study, the above challenges were successfully overcome, and high-performance top-gate nanosheet SnO p-TFT was achieved with high μFE of 4.4 cm 2 /Vs, large ION/IOFF of 1.2 × 10 5 , and sharp SS of 526 mV/decade, indicating a high potential for future monolithic 3D and brain-mimicking IC applications [15,[17][18][19][20][21].

Materials and Methods
The coplanar top-gate nanosheet SnO p-TFTs were fabricated on the Si wafer with a 500-nm-thick SiO2 IMD layer on Si wafer. The 7-nm-thick nanosheet SnO layer was deposited through reactive sputtering with 50 W DC power from a Sn target under Opp values of 14.2%, 25%, and 33.3% ambient, respectively. All the SnO p-TFT samples were annealed under 200 °C in N2 ambient for 45 min. Next, 40-nm high work-function Ni was deposited using an e-gun evaporator for the Schottky-barrier source and drain electrodes [39,40]. Subsequently, 50-nm HfO2 gate dielectric was deposited by e-beam evaporation with a rate of 0.2 Å/sec. HfO2 post-annealing was performed in N2 ambient at 100 °C and 200 °C. Finally, 50-nm gate electrode Al was deposited and patterned. The transistor's length and width were 50 and 400 μm, respectively. The current-voltage characteristics of top-gate SnO p-TFT were measured through the HP4155B parameter analyzer and a probe station. The field-effect mobility values (μFE), subthreshold slope (SS) and on-current/offcurrent (ION/IOFF) values were extracted at a standard and small VDS = −0.1 V. The crosssectional image of device structure was obtained from FEI Talos F200X high-resolution transmission electron microscope (TEM). The surface roughness of HfO2 films were obtained via Atomic Force Microscope (AFM) using DIMENSION 3100. The X-ray photoelectron spectroscopy (XPS) analyses of HfO2 films and SnO films were executed by Thermo Nexsa. The secondary ion mass spectrometry (SIMS) depth profiles of Sn, Hf and O atoms were obtained by CAMECA IMS-6fE7.  The O pp is critical for top-gate nanosheet SnO p-TFT, where the SnO channel was made by sputtering from a metal Sn target under different O pp conditions. This is because the SnO can be oxidized into oxygen-rich SnO 2 [16]. The O pp can be expressed as follows:

Results
where P O 2 and P Ar are the pressures of O 2 and Ar in a sputtering system, respectively. For comparison, the O pp values were adjusted to 14.2%, 25% and 33.3% during sputtering. Figure 2a, [12][13][14], which lowers the hole µ FE under negative V GS . The Opp is critical for top-gate nanosheet SnO p-TFT, where the SnO channel was made by sputtering from a metal Sn target under different Opp conditions. This is because the SnO can be oxidized into oxygen-rich SnO2 [16]. The Opp can be expressed as follows: where and are the pressures of O2 and Ar in a sputtering system, respectively. For comparison, the Opp values were adjusted to 14.2%, 25% and 33.3% during sputtering. Figure 2a,b show the drain-source current versus gate-source voltage (|IDS|-VGS) and μFE-VGS characteristics of top-gate nanosheet SnO p-TFT devices, respectively, under different Opp values. The top-gate p-type SnO device exhibits the highest ION and the lowest leakage IOFF at the 25% Opp condition. The device with the best ION and IOFF is also consistent with the highest μFE. The μFE values were 1.5, 4.4 and 2.6 cm 2 /Vs at Opp of 14.2%, 25% and 33.3%, respectively. Here the μFE values were obtained at the standard and a small VDS of −0.1 V. Such abnormal μFE on Opp is ascribed to the following reasons. The device μFE increases with the increase in Opp from 14.2% to 25% due to the increased oxygen content in SnOx, with x ≤ 1, and device performance degrades at a high Opp of 33.3% owing to the formation of oxygen-rich SnOx, with x > 1. Under high Opp, SnOx becomes n-type electron-conductive SnO2 [12][13][14], which lowers the hole μFE under negative VGS. The device integrity in top-gate nanosheet SnO p-TFT is also dependent on HfO2 annealing temperature. To avoid plasma damage to the SnO channel layer, the high-κ HfO2 gate dielectric was deposited using an e-beam evaporator and subjected to post-annealing at 100 and 200 °C for 30 min under N2 ambient. Here the SnO layers were deposited under 25% Opp and annealed at 200 °C under N2 ambient. Subsequently, the HfO2 were deposited and annealed at 100 °C or 200 °C under the N2 ambient. The |IDS|-VGS and μFE-VGS characteristics of SnO p-TFTs with 100 and 200 °C post-annealing are shown in Figure 3a, b, respectively. The ION/IOFF and μFE values of the SnO p-TFT at 100 °C post-annealing are 1.2 × 10 5 and 4.4 cm 2 /Vs, respectively, which are much better than those obtained at 200 °C: 4.6 × 10 2 and 1.44 cm 2 /Vs, respectively. The ION/IOFF is even better than previous bottomgate SnO p-TFT [16] possibly due to the thinner SnO channel used in this study, which slightly degrades the μFE. A thin channel layer is needed to fully deplete the conductive oxide semiconductor SnO, similar to the low IOFF using ultra-thin body Si-on-Insulator  Figure 3a, b, respectively. The I ON /I OFF and µ FE values of the SnO p-TFT at 100 • C postannealing are 1.2 × 10 5 and 4.4 cm 2 /Vs, respectively, which are much better than those obtained at 200 • C: 4.6 × 10 2 and 1.44 cm 2 /Vs, respectively. The I ON /I OFF is even better than previous bottom-gate SnO p-TFT [16] possibly due to the thinner SnO channel used in this study, which slightly degrades the µ FE . A thin channel layer is needed to fully deplete the conductive oxide semiconductor SnO, similar to the low I OFF using ultra-thin body Si-on-Insulator (SOI) and Fin field-effect transistor (FinFET). However, the small sub-10 (SOI) and Fin field-effect transistor (FinFET). However, the small sub-10 nm-scale channel thickness can increase the interface roughness scattering and decrease the mobility.
(a) (b) To investigate the mechanism of such annealing temperature dependence, Figure 4a, b plot the IDS versus drain-source voltage (IDS-VDS) and the gate-source current versus gatesource voltage (|IGS|-VGS) characteristics of top-gate SnO p-TFTs, respectively, at annealing temperatures of 100 and 200 °C. The p-TFT device at 100 °C annealing shows higher |IDS| than that at 200 °C annealing, corresponding to the higher μFE (Figure 3b). In normal case, a high post-annealing temperature of high-κ gate dielectric is necessary to reduce the gate leakage current and improve the device performance. However, the measured |IGS| of HfO2/SnO p-TFT annealed at 200 °C shows one order of magnitude higher gate leakage than that in the device annealed at 100 °C. The as-deposited HfO2 layer without annealing has too high gate leakage current due to defect conduction [41] and unsuitable for device application. To decrease the defect-conductive leakage current, even higher annealing temperature is required for metal-gate/high-κ/Si CMOS [39,42,43].  To further inspect the unusual annealing temperature dependence on device performance, material analysis of atomic force microscope (AFM), X-ray photoelectron spectroscopy To investigate the mechanism of such annealing temperature dependence, Figure 4a,b plot the I DS versus drain-source voltage (I DS -V DS ) and the gate-source current versus gate-source voltage (|I GS |-V GS ) characteristics of top-gate SnO p-TFTs, respectively, at annealing temperatures of 100 and 200 • C. The p-TFT device at 100 • C annealing shows higher |I DS | than that at 200 • C annealing, corresponding to the higher µ FE (Figure 3b). In normal case, a high post-annealing temperature of high-κ gate dielectric is necessary to reduce the gate leakage current and improve the device performance. However, the measured |I GS | of HfO 2 /SnO p-TFT annealed at 200 • C shows one order of magnitude higher gate leakage than that in the device annealed at 100 • C. The as-deposited HfO 2 layer without annealing has too high gate leakage current due to defect conduction [41] and unsuitable for device application. To decrease the defect-conductive leakage current, even higher annealing temperature is required for metal-gate/high-κ/Si CMOS [39,42,43]. To investigate the mechanism of such annealing temperature dependence, Figure 4a, b plot the IDS versus drain-source voltage (IDS-VDS) and the gate-source current versus gatesource voltage (|IGS|-VGS) characteristics of top-gate SnO p-TFTs, respectively, at annealing temperatures of 100 and 200 °C. The p-TFT device at 100 °C annealing shows higher |IDS| than that at 200 °C annealing, corresponding to the higher μFE (Figure 3b). In normal case, a high post-annealing temperature of high-κ gate dielectric is necessary to reduce the gate leakage current and improve the device performance. However, the measured |IGS| of HfO2/SnO p-TFT annealed at 200 °C shows one order of magnitude higher gate leakage than that in the device annealed at 100 °C. The as-deposited HfO2 layer without annealing has too high gate leakage current due to defect conduction [41] and unsuitable for device application. To decrease the defect-conductive leakage current, even higher annealing temperature is required for metal-gate/high-κ/Si CMOS [39,42,43].  To further inspect the unusual annealing temperature dependence on device performance, material analysis of atomic force microscope (AFM), X-ray photoelectron spectroscopy To further inspect the unusual annealing temperature dependence on device performance, material analysis of atomic force microscope (AFM), X-ray photoelectron spectroscopy (XPS), and secondary ion mass spectrometry (SIMS) were performed. In Figure S1, the surface roughness of the 50 nm HfO 2 films annealed at 100 • C, 200 • C and 400 • C were analyzed through AFM. The root mean square values of surface roughness show slightly decrease along with the increasement of the annealing temperature. The HfO 2 dielectric Nanomaterials 2021, 11, 92 5 of 11 with different annealing temperatures were also analyzed by XPS. As shown in Figure  S2, the binding energies of Hf-O and non-lattice O were 530 eV and 531.3 eV, respectively. The peak intensity of non-lattice O was related to the defects in HfO 2 dielectric, which decreased with increasing post-annealing temperature. From the AFM and XPS analysis, the good device performance at 100 • C annealing is not related to the tiny difference of HfO 2 layer.
To further investigate the O pp effect on chemical composition of the SnO layer, the XPS analyses on channel SnO were performed at the O pp of 14.2%, 25% and 33.3%. The HfO 2 layer of HfO 2 /SnO stack were etched before the XPS analysis. The XPS data are depicted in Figure 5. The XPS spectra can be deconvolved into three curves from the Sn 2+  (XPS), and secondary ion mass spectrometry (SIMS) were performed. In Figure S1, the surface roughness of the 50 nm HfO2 films annealed at 100 °C, 200 °C and 400 °C were analyzed through AFM. The root mean square values of surface roughness show slightly decrease along with the increasement of the annealing temperature. The HfO2 dielectric with different annealing temperatures were also analyzed by XPS. As shown in Figure S2, the binding energies of Hf-O and non-lattice O were 530 eV and 531.3 eV, respectively. The peak intensity of nonlattice O was related to the defects in HfO2 dielectric, which decreased with increasing postannealing temperature. From the AFM and XPS analysis, the good device performance at 100 °C annealing is not related to the tiny difference of HfO2 layer. To further investigate the Opp effect on chemical composition of the SnO layer, the XPS analyses on channel SnO were performed at the Opp of 14.2%, 25% and 33.3%. The HfO2 layer of HfO2/SnO stack were etched before the XPS analysis. The XPS data are depicted in Figure 5. The XPS spectra can be deconvolved into three curves from the Sn 2+ O, Sn 4+ O2 and Sn 0 signals, with their corresponding energies of 486.8, 486 and 484.4 eV, respectively. The composition x values of SnOx deposited at Opp = 14.2%, 25% and 33.3% were 0.8, 0.95 and 1.3, respectively, which explains well the measured electrical data in Figure 2.  Increasing the annealing temperature from 100 to 400 °C led to significant Sn diffusion from SnO into HfO2. This is attributed to the weak Sn-O band enthalpy [38], even though it also leads to high hole mobility [15,16]: The charged Sn 2+ can diffuse into HfO2, create vacancies at elevated temperatures, and, together with charged O 2− ions, allow HfOx diffusion into the SnO layer at 200 °C annealing temperature. The inter-diffusion of Sn and Hf atoms and the formed vacancies and charged ions further degrade the HfO2 gate-dielectric and HfO2/SnO interface that cause poor |IGS|, μFE, ION, and IOFF. The amount of Hf diffusion into the SnO layer at 400 °C annealing temperature can be calculated by the area within SnO layer in Figure 6c, which is 1.15 times higher than the HfO2/SnO annealed at 200 °C. The Sn atoms diffused into HfO2 layer at 400 °C were 1.14 times more than the HfO2/SnO annealed at 200 °C. Thus, the higher post-annealing temperature will cause more inter-diffusion between HfO2 and SnO.  Increasing the annealing temperature from 100 to 400 • C led to significant Sn diffusion from SnO into HfO 2 . This is attributed to the weak Sn-O band enthalpy [38], even though it also leads to high hole mobility [15,16]: The diffused Sn 2+ can behave as trap states in HfO2 gate dielectric, provide extra transport paths for the carriers, and lead to higher gate leakage current (Figure 4b). To understand the conduction mechanism of gate leakage current, the measured data were fitted with various mechanisms. As shown in Figure 7a, the measured |IGS|-VGS fits well with the hopping conduction [44][45][46][47], under an electric field (E) of <0.25 MV/cm, for 100 and 200 °C annealed top-gate SnO p-TFTs, where the slope of ln(|JGS|)-E is 5.72 and 4.91, respectively. The hopping conduction mechanism is expressed as [45]: The charged Sn 2+ can diffuse into HfO 2 , create vacancies at elevated temperatures, and, together with charged O 2− ions, allow HfO x diffusion into the SnO layer at 200 • C annealing temperature. The inter-diffusion of Sn and Hf atoms and the formed vacancies and charged ions further degrade the HfO 2 gate-dielectric and HfO 2 /SnO interface that cause poor |I GS |, µ FE , I ON , and I OFF . The amount of Hf diffusion into the SnO layer at 400 • C annealing temperature can be calculated by the area within SnO layer in Figure 6c, which is 1.15 times higher than the HfO 2 /SnO annealed at 200 • C. The Sn atoms diffused into HfO 2 layer at 400 • C were 1.14 times more than the HfO 2 /SnO annealed at 200 • C. Thus, the higher post-annealing temperature will cause more inter-diffusion between HfO 2 and SnO.
The diffused Sn 2+ can behave as trap states in HfO 2 gate dielectric, provide extra transport paths for the carriers, and lead to higher gate leakage current (Figure 4b). To understand the conduction mechanism of gate leakage current, the measured data were fitted with various mechanisms. As shown in Figure 7a, the measured |I GS |-V GS fits well with the hopping conduction [44][45][46][47], under an electric field (E) of <0.25 MV/cm, for 100 and 200 • C annealed top-gate SnO p-TFTs, where the slope of ln(|J GS |)-E is 5.72 and 4.91, respectively. The hopping conduction mechanism is expressed as [45]: where J, q, a, n, ν, and E a are the current density, electron charge, mean hopping distance, carrier concentration, thermal vibration frequency of carriers at trap states, and activation energy, respectively. The hopping distances of 100 and 200 • C annealed devices calculated from Equation (3) are 1.48 and 1.27 nm, respectively. The smaller hopping distance is ascribed to the Sn diffusion in HfO 2 , which increases the gate leakage J GS . The mechanism of poor gate leakage current and interface at high annealing temperature is depicted schematically in Figure 7b. The trap-induced hopping conduction causes high |I GS |. The degraded interface by Sn and Hf inter-diffusion and created vacancies increase the hole scattering from the source to drain, thus lowering the important I ON and µ FE . The created vacancies also increase the I OFF through defect conduction. The device performance can be further evaluated by the |I DS |-V GS hysteresis curves. The defect density formed by hysteresis curves, under forward and reverse sweep between 0 to −3 V, are 1.5 × 10 12 and 5.4 × 10 12 cm −2 for device annealed at 100 and 200 • C, respectively. This result is consistent to our conclusion: the higher post-annealing temperature creates more defects in the HfO 2 /SnO gate capacitor, which leads to higher gate leakage current, lower hole mobility, and poorer hysteresis than the one annealed at lower 100 • C temperature. The sub-threshold slope is related to interface trap, which can be calculated [48]: where the Cdep, Cit and Cox are the depletion capacitance, interface trap capacitance and gate dielectric capacitance, respectively. The interface trap density (Dit) is 2.5 × 10 13 eV −1 cm −2 that is higher than the metal-gate/high-κ/Si CMOS. Therefore, the hump of sub-threshold |IDS|-VGS curve in Figure 2 is due to the charge modulation from the interface traps [49].
In comparison with SnO atomic density of 2.9 × 10 22 atoms/cm 3 or sheet atomic density of 9.4 × 10 14 atoms/cm 2 , the Dit is only 2.7% of the sheet atoms of SnO. Thus, the electronic The sub-threshold slope is related to interface trap, which can be calculated [48]: where the C dep , C it and C ox are the depletion capacitance, interface trap capacitance and gate dielectric capacitance, respectively. The interface trap density (D it ) is 2.5 × 10 13 eV −1 cm −2 that is higher than the metal-gate/high-κ/Si CMOS. Therefore, the hump of sub-threshold |I DS |-V GS curve in Figure 2 is due to the charge modulation from the interface traps [49].
In comparison with SnO atomic density of 2.9 × 10 22 atoms/cm 3 or sheet atomic density of 9.4 × 10 14 atoms/cm 2 , the D it is only 2.7% of the sheet atoms of SnO. Thus, the electronic measurement is highly sensitive to defects compared with other measurements. The µ FE data increase to a peak value and decrease with increasing gate field. The detailed physical analysis in oxide semiconductor transistor is not reported yet. However, such hole mobility dependence is generally observed in SiO 2 /Si [50], high-κ/Si [51][52][53], SiO 2 /SiGe [54], high-κ/SiGe [55] and high-κ/Ge [56] p-MOSFETs. Because the Si, SiGe, Ge and SnO are all semiconductors and have the similar valance band structure, the decreased mobility at high electric field may be due to the similar mechanisms of phonon and interface roughness scatterings [57].
The La 2 O 3 can achieve the excellent performance of low leakage current and highκ value [55,58,59], but the moisture degradation is stronger than the HfO 2 and ZrO 2 . The ZrO 2 [60] has a higher κ value than HfO 2 once crystallized, which is widely used for dynamic random-access memory (DRAM) capacitor. For gate dielectric application, orientation-independent amorphous material like conventional SiO 2 is needed [61]. The TiO 2 has the highest κ value but suffers from the small energy bandgap and high leakage current [62]. Thus, the TiO 2 is generally added to other high-κ dielectric to increase the overall κ value [63]. The Al 2 O 3 has been used for gate dielectric due to its excellent stability [40], but suffers from relatively lower κ value than HfO 2 . Therefore, the HfO 2 is used for CMOS application and also for this work.
To inspect the stability of the top-gate SnO TFT devices, the devices were measured at as-fabricated and after retention in air ambient for two months, as depicted in Figure 8. In comparison with the conventional bottom-gate structure, such top-gate device shows huge stability improvement after retention in air [32], which is due to fully covered channel layer by metal-gate and gate-dielectric. Therefore, both the 100 and 200 • C annealed top-gate transistors show only slight degradation after exposure in air for two months. The top-gate HfO 2 /SnO p-TFT has slightly lower hole µ FE of 4.4 cm 2/ Vs than our previously reported 7.6 cm 2 /Vs of bottom-gate HfO 2 /SnO device, which is attributed to the HfO 2 /SnO interdiffusion. Because of the larger SS of top-gate device than the bottom-gate one with the same HfO 2 and SnO, the HfO 2 /SnO interface degradation is confirmed from Equation (4). Table 1 presents a comparison of the essential device characteristics of top-gate SnO p-TFTs [11,[33][34][35] The merits of this work are the highest µ FE of 4.4 cm 2 /Vs, largest I ON /I OFF of 1.2 × 10 5 , and sharpest SS of 526 mV/decade reported to date at fabrication temperatures of only 100-200 • C. This device thus has high potential to be integrated into the IMD layer of Si chips for monolithic 3D and brain-mimicking IC applications.   Table 1 presents a comparison of the essential device characteristics of top-gate SnO p-TFTs [11,[33][34][35] The merits of this work are the highest μFE of 4.4 cm 2 /Vs, largest ION/IOFF of 1.2 × 10 5 , and sharpest SS of 526 mV/decade reported to date at fabrication temperatures of only 100-200 °C. This device thus has high potential to be integrated into the IMD layer of Si chips for monolithic 3D and brain-mimicking IC applications.

Conclusions
While SnO has the advantage of high hole mobility, it also has low bond enthalpy. The key factor for good device integrity of top-gate HfO 2 /SnO p-TFT is to maintain the low process temperature, which can preserve good HfO 2 /SnO interface. Such a lowtemperature fabrication (100-200 • C) and excellent device performance are crucial for monolithic 3D and brain-mimicking ICs made on the backend IMD layers of Si chips.

Data Availability Statement:
The data presented in this study are available on request from the corresponding author. The data are not publicly available due to privacy.