Area-Scalable 109-Cycle-High-Endurance FeFET of Strontium Bismuth Tantalate Using a Dummy-Gate Process

Strontium bismuth tantalate (SBT) ferroelectric-gate field-effect transistors (FeFETs) with channel lengths of 85 nm were fabricated by a replacement-gate process. They had metal/ferroelectric/insulator/semiconductor stacked-gate structures of Ir/SBT/HfO2/Si. In the fabrication process, we prepared dummy-gate transistor patterns and then replaced the dummy substances with an SBT precursor. After forming Ir gate electrodes on the SBT, the whole gate stacks were annealed for SBT crystallization. Nonvolatility was confirmed by long stable data retention measured for 105 s. High erase-and-program endurance of the FeFETs was demonstrated for up to 109 cycles. By the new process proposed in this work, SBT-FeFETs acquire good channel-area scalability in geometry along with lithography ability.

The conventional (C)SBT-FeFETs were formed by etching the gate stacks. By decreasing the FeFET gate length, SBT etching-damage problems [29][30][31][32] on the gate-stack sidewalls became significant. Since we recognized that L m = 100 nm was approaching the shortest limit by the conventional method based on etching, we changed the fabrication strategy to shape the gate stacks from etching-down to filling-up. The new (C)SBT-FeFET process is outlined as follows: Dummy-gate transistor patterns with self-aligned sourceand drain regions are prepared in advance. The dummy substance is selectively removed to leave grooves which are later filled up with SBT precursor. Gate electrodes are formed. Finally, whole gate stacks of Ir/SBT/HfO 2 /Si are annealed for SBT crystallization. In the new FeFET process, the (C)SBT sidewall of the gate stack is not exposed to etching plasma. The sidewall is thus free from etching damage problem [6]. Consequently, the ferroelectric becomes more controllable in terms of quality and more scalable in terms of geometry than by the etching. The new FeFET dimensions follow good lithography progress with an adequate height of (C)SBT to show large memory windows increasing with the ferroelectric thickness [3,43]. In this work, SBT-FeFETs with gate channel lengths L ch = 85 nm were first reported by adopting the proposed process. Excellent characteristics were demonstrated such as 10 9 cycle erase-program endurance and long stable retention for 10 5 s. The endurance and retention were as good as those of the conventional (C)SBT-FeFETs formed by the gate-stack etching [1][2][3][4][5][6][7][8][9][10][11][12].

Device Fabrication Process
The fabrication process (schematic drawings shown in Figure 1) in this work is as follows:

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Step 1: Si substrate preparation. A p-type Si substrate patterned with FET active areas was prepared. Local-oxidation-of-silicon (LOCOS) process was used in the patterning for device isolation. The LOCOS patterns with various channel widths (W) were designed in a sample chip. Areas for source-, drain-and substrate-contact holes on the Si were heavily ion-doped. Sacrificial SiO 2 on Si was removed with buffered hydrogen fluoride.

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Step 2: Insulator deposition. A 5 nm thick HfO 2 was deposited on the Si substrate by a large-area pulsed-laser deposition system (Vacuum Products Corporation, Kodaira, Tokyo, Japan) [53]. A KrF laser was irradiated on a ceramic HfO 2 target in 15.3 Pa N 2 ambient [54]. The substrate temperature was 220 • C.

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Step 3: Lithography. Electron-beam (EB) lithography was performed by spin-coating an organic resist, exposing 130 kV EB, and developing. Resist patterns 550 nm tall were left on the HfO 2 /Si. They were later used as ion-implantation mask in Step 4 and as dummy gates in Step 7.

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Step 4: Ion implantation. HfO 2 uncovered with resist was etched out by inductivelycoupled-plasma reactive-ion etching (ICP-RIE). On the exposed Si, As + ions were implanted for source and drain. The energy and dose conditions were 4 keV and 5.0 × 10 12 /cm 2 .

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Step 5: SiO 2 deposition. An 830 nm thick SiO 2 was deposited to cover the resist patterns on the substrate by 300 W rf sputtering in 0.1 Pa Ar.

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Step 6: Flattening SiO 2 . The SiO 2 was etched back and flattened by ICP-RIE with 1.0 Pa Ar-CF 4 mixed gas until tops of the resists or dummy gates were exposed.

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Step 7: Leaving grooves on gates. The dummy-gate substances were selectively removed by O 2 plasma ashing. There remained grooves in a 410 nm tall SiO 2 isolation. The grooves were located on the HfO 2 with self-aligned source and drain regions prepared in Step 4. The whole chip was rapidly annealed at 800 • C in ambient N 2 .

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Step 8: Ferroelectric deposition. SBT precursor film was deposited to fill up the grooves by a metal-organic-chemical-vapor deposition (MOCVD) system (WACOM R&D, Nihonbashi, Tokyo, Japan  2 and Ta(OCH 2 CH 3 ) 5 (Tri Chemical Laboratories Inc., Uenohara, Yamanashi, Japan) were used [6]. As-deposited precursor-film thickness was estimated as 80 nm on a flat place of the substrate.

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Step 9: Metal deposition. Ir was deposited by rf sputtering on the SBT precursor layer. Resist mask was patterned for gate electrodes by EB lithography.

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Step 10: Forming gate electrodes. Ir uncovered with resist was etched out by Ar + ion milling. Then, the resist mask was removed by O 2 plasma ashing.

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Step 11: FeFET completed. SBT precursor was deposited again by MOCVD to cover the substrate [6]. The whole substrate was annealed for crystallization of the SBT to show ferroelectricity. The annealing condition was at 780 • C in an O 2 -N 2 mixed gas we investigated before [8]. Finally, contact holes for gate, source, drain and substrate were formed by ultraviolet g-line lithography and Ar + ion milling.

Reason for Using SBT in FeFET
The gate stack of MFIS should be regarded as MFI(IL)S, as shown in in Figure 2a, where F, I, IL, S are connected in series. The IL is an interfacial layer between I and S which is formed during the ferroelectric crystallization annealing process of FeFETs [8,39,[55][56][57]. The main component of IL is silicon dioxide with an electric permittivity (ε IL ) of ε IL = 3.9. In the MFI(IL)S, |P F | ≈ ε 0 ·ε I ·|E I | = ε 0 ·ε IL ·|E IL | = |Q S | is satisfied in any time. The P F is ferroelectric polarization. E I and E IL are electric fields in the I and the IL. The Q S is charge area density in the semiconductor surface. The ε I is a relative permittivity of the I. The ε 0 is the vacuum dielectric constant of ε 0 = 8.85 × 10 −12 F/m. For a simplified explanation, we assumed a virtual equivalent circuit of series capacitance as drawn in Figure 2a which is expressed by |P F | ≈ |Q I | = |Q IL | = |Q S | with virtual charges Q I and Q IL on I and IL, respectively. In MFI(IL)S, the IL suffers from a stress of field |E IL | ≈ |P F |/(ε 0 ·ε IL ) = 8.7 MV/cm even at a small |P F | = 3 µC/cm 2 . For example, real IL thickness is 2.6 nm [8] or about 1 nm [55][56][57]. Electric-field-assisted tunnel current through such a thin SiO 2 [58,59] brings charge injection into the gate stack from S across IL. In erase-and-program operations, a large E IL derived from a large P F swing induces significant trapped-charge accumulation which accelerates endurance degradations [2,52]. According to our experience [43,52,60], |P F | should normally be less than 2.5 µC/cm 2 all the time and should not exceed 2.0 µC/cm 2 for further high-endurance requirements of the FeFET. For convenience of explanation, the circuit is represented using virtual capacitances instead of a strict physical explanation by the electric flux density continuity, D. (b) Schematic drawings of P F versus E F . All P F -E F loops are drawn in counter-clockwise directions. The inner loop (red solid) is a minor loop corresponding to unsaturated P F discussed in Section 2.2. Outer loop (blue broken) is a major loop for saturated P F added as a reference. Every loop has its P max at E max and P min at E min .
Ferroelectric materials show P F versus E F hysteresis loops as illustrated in Figure 2b. The E F is the electric field across the F. We defined E max as the positive maximum E F and P max as the P F at E F = E max . Similarly, E min and P min are the negative minimum E F and the P F at E F = E min . The loop is called "major" loop when the E max and |E min | are strong enough to force P F saturated, whereas it is called "minor" loop when P F is unsaturated by moderate E F swing. In SBT-FeFETs, restrictions of P max ≤ 2.5 µC/cm 2 corresponding to the minor loops are used during all operations as we emphasized in early works [39,43,52,60].
Regarding a ferroelectric hidden in MFI(IL)S, an exact symmetric swing maximum, i.e., P max = |P min | or E max = |E min |, is difficult because |Q S | versus Φ S is very asymmetric [61,62]. The Q S is the charge area density of the semiconductor surface and Φ S is the surface potential. Presence of the flat-band voltage V fb makes the symmetric swing further difficult. However, to simplify the physical explanation, P max = |P min | and E max = |E min | are assumed as shown in Figure 2b with V fb = 0V. In every P F -E F loop, the E F width at P F = 0 is defined as E w being related with a voltage memory window (V w ) by an approximate expression E w = 2E c = V w /d F , where the E c is a coercive field and d F is ferroelectric thickness. According to a method we proposed before [43], an important characteristic E max of the ferroelectric can be evaluated which has not been measurable by direct probing on a FeFET. If P max is provided, a gate voltage V g to achieve a target memory window V w = E w ·d F can be estimated as a sum of E max ·d F , E I ·d I , E IL ·d IL and Φ S at Q S = P max . An exact discussion can be found in the paper [43].
For instance, Pt/SBT/HAO/Si FeFETs showed E w = 18 kV/cm at P max = 2.0 µC/cm 2 and E max = 25 kV/cm [43]. By adopting an advanced process [8], Ir/CSBT/HfO 2 /Si FeFETs had the best improved values of E w = 65 kV/cm at P max = 2.0 µC/cm 2 and E max = 140 kV/cm [3,43]. A good reason for using (C)SBT in Si-based FeFETs is the (C)SBT ferroelectric nature of a convenient minor P F -E F loop [14,17,20] which has E w available and is controllable in a restricted P F range of P max ≤ 2 µC/cm 2 with E max ≤ 140 kV/cm.
There are some other ferroelectric materials also intensively studied for applications in Si-based MFIS FeFETs. Regarding Pb 5 Ge 3 O 11 (PGO), attempts to develop replacementgate-type Pt/PGO/ZrO 2 /Si FeFETs were reported [63] but the erase-program-test results of the FeFETs were not found although the ferroelectric itself showed a good potential P max -E max and E w − E max judging from hysteresis loops of the PGO metal/ferroelectric/metal capacitors [64]. Regarding another candidate, the ferroelectric HfO 2 family [55][56][57][65][66][67][68][69][70], the intrinsic material nature may not be suitable for applying to Si-based FeFETs. Informative minor hysteresis loops were reported on Y-doped HfO 2 in which E w seemed nearly equal to 0 V/cm at P max = 2.0 µC/cm 2 , although it was as large as about 1 MV/cm at P max = 10 µC/cm 2 [66]. Operation of the FeFETs under the restriction of P max ≤ 2 µC/cm 2 may be difficult. Some reports suggested that HfO 2 -FeFETs cannot help using a large P max (>>2 µC/cm 2 ) [52,55]. The large P max may induce significant charge injection into the gate stack. As far as we know, fair works on HfO 2 -FeFETs have not cleared 10 8 cycles endurance in spite of using sophisticated production facilities [56,[67][68][69][70].

Device Dimensions
A cross-sectional scanning-electron-microscope photograph of an Ir/SBT/HfO 2 /Si FeFET fabricated by the new proposed process is shown in Figure 3a. Figure 3b shows the same picture added with support lines to clarify the material boundaries. The schematic drawing of the FeFET was assigned with four terminals of gate, drain, source and substrate (Figure 3c). The gate-channel length (L ch ) was L ch = 85 nm. The gate-channel width was W = 100 µm depending on the initial LOCOS pattern designed in Step 1 in Section 2.1. The metal-gate length L m was 150 nm which could be shorter but was not the focus in this work. The SBT precursor film thickness was about 80 nm measured on a flat place. By filling gate grooves with SBT precursor (Step 8 in Section 2.1.), the effective SBT height (H) was finally about 450 nm which was a distance between Ir and HfO 2 . Area scalability of the new FeFET was equivalent to that of the dummy gates which are organic resist patterns made by lithography. From the viewpoint of Si transistor technology, L ch = 10 nm is expected to be the critical limit [71]. A significant Curie-temperature decrease in SBT started when particle were sizes of around 20 nm [25]. Thus, the prospective shortest limit of L ch by our proposed FeFET process may be around 20 nm.

Electrical Characterizations
In this study, memory windows, endurance and retention of FeFETs were investigated at room temperature. A semiconductor parameter analyzer (4156C, Keysight Technologies, Santa Rosa, CA, USA) was used for measuring static drain current versus gate voltage (I d -V g ) curves of the FeFETs. A pulse generator (81110A, Keysight Technologies, Santa Rosa, CA, USA) was used to apply V g pulses. The instruments were computer-controlled using programs written by the language of LabVIEW (ver. 10, National Instruments, Austin, TX, USA).

Memory Windows
As an elementary test of the FeFETs, I d -V g hysteresis loops were investigated (Figure 4). The I d was measured by V g increments and decrements with 0.1 V steps. The V g sweeping ranges were V g = 1 ± 4 V, 1 ± 5 V and 1 ± 6 V. Drain voltage (V d ), source voltage (V s ) and substrate voltage (V sub ) were fixed to V d = 0.1 V and V s = V sub = 0 V during the measurements. The I d -V g showed hysteresis loops drawn in counter-clockwise directions because the FeFET was an n-channel-type one. In an I d -V g curve, threshold voltage (V th ) was defined as a V g value at I d /W = 1 × 10 −7 A/cm. Two V th values were extracted from the left-and right-side curves in an I d -V g hysteresis loop. A memory window was defined as the V th difference. In this work, we call this a static memory window (V w ) because V g sweep by 4156C is slow. The static V w was, for instance, 1.0 V by sweeping V g from −5 to 7 V then back to −5 V, or at V g = 1 ± 6 V as expressed in Figure 4. During the measurement of a wide-range I d from 10 −12 to 10 −4 A as indicated in Figure 4, V g sweep speed depends on the current range. Therefore, an I d -V g hysteresis curve only gives reference information that is not suitable for accurate discussion. The channel width was W = 150 µm. V g ranges were V g = 1 ± 4 V, 1 ± 5 V and 1 ± 6 V.
For an accurate understanding, the FeFET performance, a pulsed V g with a controlled time width, was applied to the FeFETs for the erase (Ers) or program (Prg) operation. The V g pulse heights with the time widths were (V E , t E ) for Ers, and (V P , t P ) for Prg, respectively. For the n-channel-type FeFET, the V E was negative (V E < 0 V) and V P was positive (V P > 0 V) [9]. The pulse time widths t E and t P were the same with each other in this work (t E = t P = t EP ). After, Ers and Prg, I d -V g curves were individually measured with a small common V g range for Read. Two V th values were defined in the I d -V g curves as the V g at I d /W = 1 × 10 −7 A/cm. They were expressed as V thE after Ers and V thP after Prg. The V thE was larger than the V thP [9]. The V th difference of ∆V th = V thE − V thP was defined as a memory window obtained by read operation after erase-and-program pulse applications. The memory window ∆V th is normally smaller than the above-mentioned static V w , because slow switching components in a ferroelectric do not respond to short pulses [27,72,73]. The V thE and V thP were investigated by repeating a series of operations: Ers, Read, Prg, Read, in this order (Figure 5a). In Ers, a pulsed V g of (V E , t EP ) was applied with keeping V d = V s = V sub = 0 V. In Read after Ers, a V thE was extracted from an I d -V g curve drawn by narrow-range varying V g from 0 to 1.1 V at V d = 0.1 V and V s = V sub = 0 V. In Prg, a pulsed V g of (V P , t EP ) was applied, keeping V d = V s = V sub = 0 V. In Read after Prg, a V thP was extracted from an I d -V g curve drawn under exactly the same conditions as those in Read after Ers. Figure 5b shows V thE and V thP by Read after Ers and Prg for three sets of (V E , t EP ) and (V P , t EP ) of |V E | = V P = 6, 7 and 8 V. Every marker corresponds to the measured V thE and V thP . Memory windows, ∆V th = V thE -V thP , as a function of pulse height |V E | = |V P | ( Figure 5c) and width t EP (Figure 5d) can be seen in Figure 5b, where the V thE and V thP results (not shown in Figure 5b) of other V P (=|V E |) conditions were also used. Short V g pulses of t EP = 50 ns were available for Ers and Prg of the FeFET. Memory windows of ∆V th > 0.7 V were obtained using 8 and 8.5 V pulses. Figure 5c,d show a clear monotonic ∆V th increases when raising either the pulse height or width. Good analog V thE and V thP controllability was suggested by smooth and linear ∆V th growths with raising log(t EP ) as shown in Figure 5d. The similar tendencies of ∆V th and t EP have already been reported in our previous works [3,5,7,9,52]. In the prior FeFETs, poly-crystalized ferroelectrics were visualized by electron backscatter diffraction (EBSD) [44]. The EBSD indicated that the (C)SBT consisted of multi-grains with various crystal orientations in the FeFETs. The poly-crystalized ferroelectrics may bring the analog V thE and V thP controllability to the FeFETs. In the present FeFET, there must be numerous grains in channel-width direction with W = 100 µm whereas a single grain or a few were expected in channel-length with L ch = 85 nm which was smaller than average diameters of SBT grains freely grown in-plane [44].
In a preferable geometry of the replacement-gate FeFET in the future, only the channel area L ch × W will be intensively scaled down with remaining the height H. The H is decided by the gate-groove depth in Step 7 in Section 2.1 and Figure 1. The ∆V th in this report was not yet at its best ability considering the ferroelectric height H = 450 nm. In the vertical direction of FeFET, a gate stack by filling SBT should be essentially the same as a large L ch conventional one by etching SBT. Therefore, potential ∆V th will become the same as that of conventional FeFETs by improving the details in the fabrication process in Section 2.1. An immediate target for the present FeFET will be realizing ∆V th = 0.7 V by Ers of (−6V, 10 µs) and Prg of (6V, 10 µs) for H = 190 nm as demonstrated before using Pt/CSBT/HfO 2 /Si FeFETs [7].

Retention
Retention of a FeFET was measured by the procedures as shown in Figure 6a,b. After program (Prg), Retain and Read were repeated during the scheduled time. In Prg, a V g pulse of (V P , t EP ) was applied with V d = V s = V sub = 0 V. In Retain, all the terminals were kept at zero as V g = V d = V s = V sub = 0 V. In Read at a certain time t, an I d -V g curve was drawn by varying V g in a narrow range from 0 to 1.0 V at V d = 0.1 V and V s = V sub = 0 V. A V thP was extracted from the I d -V g and plotted with a marker at t as shown in Figure 6c. After completing the V thP -t, V thE -t started to be measured. In erase (Ers), a V g pulse of (V E , t EP ) was applied with V d = V s = V sub = 0 V. After Ers, Retain and Read were repeated during the scheduled time. The Retain and Read conditions for V thE -t were the same as those for V thP -t. In the Read at a certain time t, an extracted V thE was plotted with a marker at t as shown in Figure 6c. In this work, V P = 8 V, V E = −8 V and t EP = 10 µs. The retention was measured for 10 5 s in each of V thP -t and V thE -t. At t = 10 5 s, they were still distinguishable with a difference ∆V th = 0.26 V. When t > 10 3 s, as shown in Figure 6c, the gradient of the V thP -log(t) and V thE -log(t) curves appeared to be nearly zero. A possible ten-year retention was suggested by extrapolation lines drawn on the last three markers in each branch. The present L ch = 85 nm FeFET showed a good retention to the same extent as those of the conventional (C)SBT FeFETs [1][2][3][4][5][6][7][8][9]11,12,[37][38][39][40]42,45,46,52]. Figure 6. Retention investigation after applying V g pulses to a FeFET with L ch = 85 nm. The channel width was W = 100 µm. The measurement procedures for the retentions of (a) V thP after Prg of (V P , t EP ) and (b) V thE after Ers of (V E , t EP ). (c) The measured retentions for 10 5 s each. Dashed lines are extrapolations of V thP -log(t) and V thE -log(t) for estimating V thP and V thE after ten years.

Endurance
Endurance of a FeFET was measured by the procedure shown in Figure 7a. After imposing endurance cycles on FeFETs, pairs of V thE and V thP were obtained. The endurance cycles consisted of periodic bipolar V g pulses for an alternate Ers of (V E , t EP ) and Prg of (V P , t EP ) with V d = V s = V sub = 0 V. The endurance-cycle application was interrupted at certain scheduled cycle numbers (N). After the N cycle application, V thE and V thP were read as follows: a series operation of Ers, Read, Prg, and Read, in this order was performed. In Ers, a single V g pulse of (V E , t EP ) was applied with V d = V s = V sub = 0 V. In Read after Ers, an I d -V g was measured by varying V g in a narrow range from 0 to 1.5 V at V d = 0.1 V and V s = V sub = 0 V. A V thE was extracted from the I d -V g and plotted with a marker at N as shown in Figure 7b. In Prg, a single V g pulse of (V P , t EP ) was applied with V d = V s = V sub = 0 V. In Read after Prg, an I d -V g was measured under the same conditions with Read after Ers. The obtained V thP was plotted with a marker at N as shown in Figure 7b. As shown in Figure 7b, the Ers of (−7.5 V, 10 µs) and Prg of (7.5 V, 10 µs) were first applied for an endurance up to N = 10 8 cycles. Next, a stronger input of (−8 V, 10 µs) and (8 V, 10 µs) was applied to the same FeFET up to N = 10 9 cycles. No significant sifts of V thE and V thP were observed throughout the measurements. By taking the minimum of the V thE and the maximum of the V thP in the endurance test, ∆V th = 0.40 V for |V E | = V P = 7.5 V and ∆V th = 0.57 V for |V E | = V P = 8 V were obtained. These were margins for distinguishing V thE from V thP as indicated in Figure 7b. In spite of using the rather complicated dummygate process, the L ch = 85 nm FeFET fabricated showed high endurance up to 10 8~1 0 9 cycles. This is the same as the endurance level that (C)SBT-FeFETs inherently have [1][2][3][4][5][6][7][8][9][10][11][12].

Summary
A new fabrication process of a FeFET was proposed and demonstrated. Dummy-gate patterns with self-aligned sources and drains were prepared on a Si substrate. HfO 2 with a thickness of 5 nm was inserted in advance between the dummy-gate substance and the Si substrate. The dummy substance was selectively removed to form a self-aligned groove on the gate. A thin SBT precursor film was deposited to fill up the groove. After forming the Ir gate electrode on the SBT, the whole gate stack was annealed for the SBT crystallization. The finished FeFET of Ir/SBT/HfO 2 /Si had a channel length L ch = 85 nm. The FeFET exhibited a 10 9 cycle-high endurance and long stable retentions measured for 10 5 s. By adopting the replacement-gate process, area-scalable SBT-FeFETs with the high endurance and long retention were successfully produced.