Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications

In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.


Introduction
In recent years, the application of semiconductor field-effect transistors (FET) sensors have attracted a lot of attention because of their ability to translate the interaction with target molecules on the FET surface to an electrical signal directly [1][2][3][4]. Silicon nanowires (Si NW) sensors have been considered as one of the most promising candidates for biochemical sensors [5][6][7][8][9], due to their large surface to volume (S/V) ratio, high sensitivity, and good biocompatibility [10,11]. In recent years, NW field-effect-transistor (FET) sensors have been used for the very high sensitivity detection of pH [12][13][14], gases [15][16][17] and DNA [18][19][20]. However, the conventional fabrication process with siliconon-insulator (SOI) materials is complex and high-cost, and the nanometer patterns are usually formed by traditional low-efficiency electron beam lithography (EBL) process, which does not meet the demands of future mass production with a low cost and low efficiency. The spacer image transfer (SIT) process (also named self-aligned double or quadruple patterning) could achieve nanometer array with high efficiency and low cost, which are widely used in foundries [21][22][23]. In addition, there are no reports on the design or fabrication of Si NW sensors for monolithic three-dimensional integrated circuits (3D-ICs) application, which is one of the most convincing candidates for future application (see Figure 1). In order to achieve better performance of the system, the fabrication of top devices (Si NW sensor) usually need low-temperature processes to avoid a degradation on characteristics of bottom circuits (logic circuits and memory in Figure 1) [24]. However, there are no reports on the design or fabrication of Si NW sensor for monolithic 3D-ICs application. In this paper, poly-silicon NW sensors with low cost and high efficiency are designed and fabricated using advanced spacer image transfer (SIT) [22][23][24] and low-temperature silicide techniques for monolithic 3D-IC application. The highest annealing temperature is not over 600 °C, which overcomes the problems of overheating the bottom transistor and the wires. The achieved poly-silicon NW sensors have good electrical properties, such as over six orders of magnitude in onoff ratio and 932 mV/dec of subthreshold swing (SS) by bias back-gate voltages.

Materials and Methods
Two types of Si NW sensors (poly-silicon and silicon-on-insulator (SOI)) were designed and fabricated, and the detailed fabrication flow is illustrated in Figure 2. The poly-silicon NW sensors were manufactured on p-type 200 mm Si (100) silicon wafers (see Figure 2a): Firstly, 145 nm SiO2 and 40 nm poly-silicon were deposited, respectively (see Figure 2b). The SOI Si NW sensors were manufactured on 200 mm SOI wafers featured with a 145-nm-thick buried oxide layer (BOX) and a 40-nm-thick top silicon layer. The fabrication process of the two types of devices was all the same in the flowing steps. During the fabrication of the Si NWs, a spacer image transfer (SIT) technology was chosen to form NW arrays patterns with high efficiency [25][26][27] , and the detailed fabrication process flow is described as follows: sequential multi-layer SiO2/amorphous Si (α-Si)/Si3N4 films were deposited (see Figure 2c). Next, the conventional photolithography process (i-line) and dry etching processes were used to form rectangular arrays of Si3N4 and α-Si films (see Figure 2d). The top Si3N4 hard masks (HMs) were removed by a hot H3PO4 solution at 140 °C (see Figure 2e). A 30 nm Si3N4 film was deposited by plasma-enhanced chemical vapor deposition (PECVD) approach and then the corresponding Si3N4 reactive ion etching (RIE) was performed to form two SiNx spacers on both sides In this paper, poly-silicon NW sensors with low cost and high efficiency are designed and fabricated using advanced spacer image transfer (SIT) [22][23][24] and low-temperature silicide techniques for monolithic 3D-IC application. The highest annealing temperature is not over 600 • C, which overcomes the problems of overheating the bottom transistor and the wires. The achieved poly-silicon NW sensors have good electrical properties, such as over six orders of magnitude in on-off ratio and 932 mV/dec of subthreshold swing (SS) by bias back-gate voltages.

Materials and Methods
Two types of Si NW sensors (poly-silicon and silicon-on-insulator (SOI)) were designed and fabricated, and the detailed fabrication flow is illustrated in Figure 2. The poly-silicon NW sensors were manufactured on p-type 200 mm Si (100) silicon wafers (see Figure 2a): Firstly, 145 nm SiO 2 and 40 nm poly-silicon were deposited, respectively (see Figure 2b). The SOI Si NW sensors were manufactured on 200 mm SOI wafers featured with a 145-nm-thick buried oxide layer (BOX) and a 40-nm-thick top silicon layer. The fabrication process of the two types of devices was all the same in the flowing steps. During the fabrication of the Si NWs, a spacer image transfer (SIT) technology was chosen to form NW arrays patterns with high efficiency [25][26][27], and the detailed fabrication process flow is described as follows: sequential multi-layer SiO 2 /amorphous Si (α-Si)/Si 3 N 4 films were deposited (see Figure 2c). Next, the conventional photolithography process (i-line) and dry etching processes were used to form rectangular arrays of Si 3 N 4 and α-Si films (see Figure 2d). The top Si 3 N 4 hard masks (HMs) were removed by a hot H 3 PO 4 solution at 140 • C (see Figure 2e). A 30 nm Si 3 N 4 film was deposited by plasma-enhanced chemical vapor deposition (PECVD) approach and then the corresponding Si 3 N 4 reactive ion etching (RIE) was performed to form two SiN x spacers on both sides of α-Si (see Figure 2f,g). The α-Si material between two Si 3 N 4 spacers was removed by tetramenthylammonium hydroxide (TMAH) (see Figure 2h). In order to obtain Si NW arrays, dry etching processes of SiO 2 and Si were carried out, respectively (see Figure 2h). Afterward, the top HMs were removed using hot phosphoric acid and diluted hydrofluoroacid (DHF) solution, respectively (see Figure 2i). After the Si NW formation, a 5-nm-thick SiO 2 was deposited on the Si NW followed by the deposition of a thick layer of Si 3 N 4 (see Figure 2j,k). The Si 3 N 4 film was etched by dry etching processes. A nickel platinum alloy (Ni 0.95 Pt 0.05 ) was used to form metal silicide in the source and drain regions to reduce the parasitic of Si nanowires (see Figure 2l,m). Afterward, BF 2+ ions with a heavy dose and low energy were implanted into the top silicided Si NWs and activated by low temperature rapid thermal annealing (RTA) to form Schottky barrier source and drain (SBSD) (about 600 • C/30 s annealing). For a better combination, the aluminum electrode was prepared by a sputtering process and the RIE process was performed (see Figure 2n,o). Subsequently, a layer of thick SiO 2 was deposited, and the source drain contact holes were opened by photolithography and etching processes (see Figure 2p,q). Finally, the gate with different channel lengths (5, 10 and 15 µm) was defined by photolithography and the open gate trench of the sensor to expose the sensitive area was achieved by RIE processes. The bounding of SD contact was carried out and a layer of 20-nm-thick HfO 2 was deposited on the surface of the device (see Figure 2r). Figure 2s is a schematic top view of the device. Except for the source drain and gate trench of the devices, other areas were covered by a thick SiO 2 , which helps to improve the stability and reliability of the solution.
Nanomaterials 2020, 10, x FOR PEER REVIEW 3 of 11 tetramenthylammonium hydroxide (TMAH) (see Figure 2h). In order to obtain Si NW arrays, dry etching processes of SiO2 and Si were carried out, respectively (see Figure 2h). Afterward, the top HMs were removed using hot phosphoric acid and diluted hydrofluoroacid (DHF) solution, respectively (see Figure 2i). After the Si NW formation, a 5-nm-thick SiO2 was deposited on the Si NW followed by the deposition of a thick layer of Si3N4 (see Figure 2j,k). The Si3N4 film was etched by dry etching processes. A nickel platinum alloy (Ni0.95Pt0.05) was used to form metal silicide in the source and drain regions to reduce the parasitic of Si nanowires (see Figure 2l,m). Afterward, BF 2+ ions with a heavy dose and low energy were implanted into the top silicided Si NWs and activated by low temperature rapid thermal annealing (RTA) to form Schottky barrier source and drain (SBSD) (about 600 °C/30 s annealing). For a better combination, the aluminum electrode was prepared by a sputtering process and the RIE process was performed (see Figure 2n,o). Subsequently, a layer of thick SiO2 was deposited, and the source drain contact holes were opened by photolithography and etching processes (see Figure 2p,q). Finally, the gate with different channel lengths (5, 10 and 15 μm) was defined by photolithography and the open gate trench of the sensor to expose the sensitive area was achieved by RIE processes. The bounding of SD contact was carried out and a layer of 20-nmthick HfO2 was deposited on the surface of the device (see Figure 2r). Figure 2s is a schematic top view of the device. Except for the source drain and gate trench of the devices, other areas were covered by a thick SiO2, which helps to improve the stability and reliability of the solution. The cross-sectional views and top views of the device's structures were observed using S-5500 and S-4800 scanning electron microscopes (SEM, Hitachi, Tokyo, Japan), respectively. The crosssectional profiles of the final device were performed using transmission electron microscopy (TEM, FEI Talos, Brno, Czech) and energy-dispersive X-ray spectroscopy (EDX, FEI Talos, Brno, Czech). The electrical characterization was performed using a B1500A (Keysight, Santa Rosa, CA, USA) semiconductor parameter analyzer. The cross-sectional views and top views of the device's structures were observed using S-5500 and S-4800 scanning electron microscopes (SEM, Hitachi, Tokyo, Japan), respectively. The cross-sectional profiles of the final device were performed using transmission electron microscopy (TEM, FEI Talos, Brno, Czech) and energy-dispersive X-ray spectroscopy (EDX, FEI Talos, Brno, Czech). The electrical Nanomaterials 2020, 10, 2488 4 of 11 characterization was performed using a B1500A (Keysight, Santa Rosa, CA, USA) semiconductor parameter analyzer.

Results and Discussion
The images of the fabricated poly-Si NWs sensors by the SIT process are shown in Figure 3. Figure 3a,b shows top views of poly-Si NW arrays by SEM measurement. As can been seen from the images, highly uniform poly-Si NW arrays without any landing pads are achieved. The achieved poly-Si NW arrays using the SIT approach have high efficiency, low cost and smaller sizes compared with that of fabricated using the EBL process. Figure 3c shows a cross-sectional view of poly-Si NWs. Contrasted with previous work [28,29], the dimensions and the morphology of the fabricated Si NW arrays are well controlled and extraordinarily small, theoretically providing higher sensitivity for the fabricated poly-Si NW sensor. Figure 3d,e shows top views of poly-Si NW sensors arrays. The length of the electrode is 2 mm; the gate lengths (L Gs ) of poly-Si NW FETs are 5 µm, 10 µm, and 15 µm, respectively. The sensor current is increased and the device's variations are reduced for the multi-channel poly-Si NW sensors.

Results and Discussion
The images of the fabricated poly-Si NWs sensors by the SIT process are shown in Figure 3. Figure 3a,b shows top views of poly-Si NW arrays by SEM measurement. As can been seen from the images, highly uniform poly-Si NW arrays without any landing pads are achieved. The achieved poly-Si NW arrays using the SIT approach have high efficiency, low cost and smaller sizes compared with that of fabricated using the EBL process. Figure 3c shows a cross-sectional view of poly-Si NWs. Contrasted with previous work [28,29], the dimensions and the morphology of the fabricated Si NW arrays are well controlled and extraordinarily small, theoretically providing higher sensitivity for the fabricated poly-Si NW sensor. Figure 3d,e shows top views of poly-Si NW sensors arrays. The length of the electrode is 2 mm; the gate lengths (LGs) of poly-Si NW FETs are 5 μm, 10 μm, and 15 μm, respectively. The sensor current is increased and the device's variations are reduced for the multichannel poly-Si NW sensors.  Initial measurements of transfer and output curves (ID-VG and ID-VD) were performed by applying a bias gate voltage. In the measurement of the ID-VG curve, ID was measured at constant drain voltages (VD = −0.2 V, −1.2 V, −2.2 V), and the gate voltage was swept from 0 to −30 V. In the measurement of the ID-VD curves, the drain current was measured at constant gate voltages (VG from 0 to −20 V with a −2 V step), and the VD was swept from 0 to −5V with a −0.2 V step.
The ID-VG and ID-VD curves by bias gate voltages of the p-type poly-Si NW sensors are shown in Figure 5. Figure 5a-c shows typical ID-VG curves of 5-μm-LG, 10-μm-LG and 15-μm-LG poly-Si NW devices, respectively. As can be seen from the images, smooth and uniform p-type MOSFET curves were achieved for the sensors fabricated at low temperature. The Ion/Ioff ratios of poly-Si NW devices with the 5-μm-LG, 10-μm-LG and 15-μm-LG are 5.68 × 10 6 , 2.84 × 10 6 and 2.31 × 10 6 , respectively. The corresponding extracted values of subthreshold swing (SS) are estimated to be 1070 mV/dec, 965  mV/dec and 956 mV/dec, respectively. Figure 5d depicts the ID-VD curves of poly-Si NW device 10μm-LG. The drain current increases with increasing VG bias, implying that the carrier's concentration inside Si NWs can be linearly adjusted, and devices prepared at low temperatures exhibit good FET electrical performance.  The ID-VG and ID-VD curves of the SOI Si NW for 5-μm-LG, 10-μm-LG and 15-μm-LG are shown in Figure 6, respectively. As can be seen from the images, smooth p-type MOSFET curves are achieved for the sensors fabricate at low temperature. The Ion/Ioff ratios of 5-μm-LG, 10-μm-LG and 15-μm-LG SOI Si NW devices are 1.47 × 10 8 , 1.29 × 10 7 and 6.34 × 10 4 , respectively, and extracted values of SSs The I D -V G and I D -V D curves by bias gate voltages of the p-type poly-Si NW sensors are shown in Figure 5. Figure 5a-c shows typical I D -V G curves of 5-µm-L G , 10-µm-L G and 15-µm-L G poly-Si NW devices, respectively. As can be seen from the images, smooth and uniform p-type MOSFET curves were achieved for the sensors fabricated at low temperature. The I on /I off ratios of poly-Si NW devices with the 5-µm-L G , 10-µm-L G and 15-µm-L G are 5.68 × 10 6 , 2.84 × 10 6 and 2.31 × 10 6 , respectively. The corresponding extracted values of subthreshold swing (SS) are estimated to be 1070 mV/dec, 965 mV/dec and 956 mV/dec, respectively. Figure 5d depicts the I D -V D curves of poly-Si NW device 10-µm-L G. The drain current increases with increasing V G bias, implying that the carrier's concentration inside Si NWs can be linearly adjusted, and devices prepared at low temperatures exhibit good FET electrical performance. Nanomaterials 2020, 10, x FOR PEER REVIEW 5 of 11 mV/dec and 956 mV/dec, respectively. Figure 5d depicts the ID-VD curves of poly-Si NW device 10μm-LG. The drain current increases with increasing VG bias, implying that the carrier's concentration inside Si NWs can be linearly adjusted, and devices prepared at low temperatures exhibit good FET electrical performance.  The ID-VG and ID-VD curves of the SOI Si NW for 5-μm-LG, 10-μm-LG and 15-μm-LG are shown in Figure 6, respectively. As can be seen from the images, smooth p-type MOSFET curves are achieved for the sensors fabricate at low temperature. The Ion/Ioff ratios of 5-μm-LG, 10-μm-LG and 15-μm-LG SOI Si NW devices are 1.47 × 10 8 , 1.29 × 10 7 and 6.34 × 10 4 , respectively, and extracted values of SSs The I D -V G and I D -V D curves of the SOI Si NW for 5-µm-L G , 10-µm-L G and 15-µm-L G are shown in Figure 6, respectively. As can be seen from the images, smooth p-type MOSFET curves are achieved for the sensors fabricate at low temperature. The I on /I off ratios of 5-µm-L G , 10-µm-L G and 15-µm-L G SOI Si NW devices are 1.47 × 10 8 , 1.29 × 10 7 and 6.34 × 10 4 , respectively, and extracted values of SSs are estimated to be 686 mV/dec, 767 mV/dec and 1120 mV/dec, respectively. Figure 6d depicts the I D -V D curves of the 10-µm-L G poly-Si NW device. Nanomaterials 2020, 10, x FOR PEER REVIEW 6 of 11 are estimated to be 686 mV/dec, 767 mV/dec and 1120 mV/dec, respectively. Figure 6d depicts the ID-VD curves of the 10-μm-LG poly-Si NW device.  LGs are similar to those of the SOI devices. The values of SSs of SOI devices are smaller than those of poly-Si devices and the Ion/Ioff is also larger. The performance of SOI devices is slightly better than that of low-temperature poly-silicon devices, which is caused by the monocrystalline silicon channel with a low channel resistance. The achieved results imply that the poly-Si NW sensors could be applied for future monolithic 3D-IC application.  Figure 7 shows the extracted typical parameter comparison between the poly-Si NW and SOI Si NW sensors, e.g., the threshold voltage (V th ), SS, on-stage current (I on ) and I on / off ratio, respectively. The V th s of 5-µm-L G , 10-µm-L G and 15-µm-L G poly-Si NW devices are −8.06 V, −8.125 V and −7.87 V, respectively. The V th of 5-µm-L G , 10-µm-L G and 15-µm-L G SOI Si NW devices are −7.67 V, −7.95 V and −7.8 V, respectively. The values of V th s of poly-silicon devices with different L G s are similar to those of the SOI devices. The values of SSs of SOI devices are smaller than those of poly-Si devices and the I on /I off is also larger. The performance of SOI devices is slightly better than that of low-temperature poly-silicon devices, which is caused by the monocrystalline silicon channel with a low channel resistance. The achieved results imply that the poly-Si NW sensors could be applied for future monolithic 3D-IC application. Figure 8 shows the typical sensing characteristics of the poly-silicon nanowire sensors by analyzing different stranded pH solutions. In the measurement of the I D -V G curve and the gate voltage was swept from 0 to −10 V by top solution (see Figure 8a inserted image). The detection principle is to convert the sensor surface potential change introduced by a different pH solution into the current change in the semiconductor Si NW channel. The actual amount of charges depends on the concentration of specific ions in the solution (the concentration of H + ion in the manuscripts). Therefore, the pH of the solutions could modulate the surface charge of the insulator/semiconducting interface consequently, resulting in a shift of the threshold voltage. The scheme of the test using the top liquid gate is shown in the inserted figure of Figure 8a. Due to the change of film surface potential of the channel, the poly-silicon nanowire sensors exhibit V th shifts (see Figure 8a). If the added solution is acidic (alkaline), the I D -V G curve will shift to the right (left). After adding different pH buffers, the real-time response of I D is shown in Figure 8b. Taking the buffer solution with pH = 7 as a reference, when the pH buffer is acidic, a positive charge is introduced and the current of the p-type poly-silicon nanowire sensor increases. When the pH buffer is alkaline, a negative charge is introduced and the current decreases. The results are consistent with the transfer curve of the p-type poly-silicon nanowire sensor increases. The extracted change values of V th and I D as a function of pH values are shown in Figure 8c,d, respectively. The changes of V th and I D have approximate linearity with the pH values, and the sensitivity as high as about 178 ± 1 mV/pH, which is caused by the small size in Si NW and large surface to volume ratio.  Figure 8 shows the typical sensing characteristics of the poly-silicon nanowire sensors by analyzing different stranded pH solutions. In the measurement of the ID-VG curve and the gate voltage was swept from 0 to −10 V by top solution (see Figure 8a inserted image). The detection principle is to convert the sensor surface potential change introduced by a different pH solution into the current change in the semiconductor Si NW channel. The actual amount of charges depends on the concentration of specific ions in the solution (the concentration of H + ion in the manuscripts). Therefore, the pH of the solutions could modulate the surface charge of the insulator/semiconducting interface consequently, resulting in a shift of the threshold voltage. The scheme of the test using the top liquid gate is shown in the inserted figure of Figure 8a. Due to the change of film surface potential of the channel, the poly-silicon nanowire sensors exhibit Vth shifts (see Figure 8a). If the added solution is acidic (alkaline), the ID-VG curve will shift to the right (left). After adding different pH buffers, the real-time response of ID is shown in Figure 8b. Taking the buffer solution with pH = 7 as a reference, when the pH buffer is acidic, a positive charge is introduced and the current of the ptype poly-silicon nanowire sensor increases. When the pH buffer is alkaline, a negative charge is introduced and the current decreases. The results are consistent with the transfer curve of the p-type poly-silicon nanowire sensor increases. The extracted change values of Vth and ID as a function of pH values are shown in Figure 8c,d, respectively. The changes of Vth and ID have approximate linearity with the pH values, and the sensitivity as high as about 178 ± 1 mV/pH, which is caused by the small size in Si NW and large surface to volume ratio.  Figure 9 shows the typical sensing characteristics of the SOI nanowire sensors by analyzing different stranded pH solutions. In the measurement of the ID-VG curve, the gate voltage was swept from 0 to −4 V by the top solution. Figure 9a shows that the threshold voltage shifts with the pH of the solution. The extracted threshold change is linear with the pH of the solution (see Figure 9b). A similar trend of Vth shift is obtained, but the values of changes are only about a fifth of the poly-silicon nanowire.  Figure 9 shows the typical sensing characteristics of the SOI nanowire sensors by analyzing different stranded pH solutions. In the measurement of the I D -V G curve, the gate voltage was swept from 0 to −4 V by the top solution. Figure 9a shows that the threshold voltage shifts with the pH of the solution. The extracted threshold change is linear with the pH of the solution (see Figure 9b). A similar trend of V th shift is obtained, but the values of changes are only about a fifth of the poly-silicon nanowire.  Figure 9 shows the typical sensing characteristics of the SOI nanowire sensors by analyzing different stranded pH solutions. In the measurement of the ID-VG curve, the gate voltage was swept from 0 to −4 V by the top solution. Figure 9a shows that the threshold voltage shifts with the pH of the solution. The extracted threshold change is linear with the pH of the solution (see Figure 9b). A similar trend of Vth shift is obtained, but the values of changes are only about a fifth of the poly-silicon nanowire.  Table 1 shows system parameters comparison of the relevant reported results in recent years and our fabricated poly-silicon nanowire sensors. The SIT technique is used to form poly-silicon NW sensor arrays with 25 nm in width and 35 nm in length, which exhibits high efficiency and low cost than that of formed by EBL. Furthermore, the resistance and the device performance-the poly-silicon  Table 1 shows system parameters comparison of the relevant reported results in recent years and our fabricated poly-silicon nanowire sensors. The SIT technique is used to form poly-silicon NW sensor arrays with 25 nm in width and 35 nm in length, which exhibits high efficiency and low cost than that of formed by EBL. Furthermore, the resistance and the device performance-the poly-silicon NW sensor is greatly improved by introducing SBSD techniques, which is attributed to achieve a larger I on /I off ratio and smaller values of SSs. The results indicate that the poly-silicon NWs sensor fabricated by low-temperature annealing has much better characteristics than those of the sensors prepared by other methods, which attributed to its application for future monolithic 3D-IC applications.

Conclusions
In summary, low cost poly-Si NW sensors arrays are fabricated through an advanced SIT process with high efficiency than that formed by electron beam lithography, and the morphology of Si NW is well controlled with small sizes. Furthermore, a low-temperature flow (600 • C) with silicide and implantation is designed and carried out. Benefiting from the silicide and isolation processes, the poly-Si NW FET sensors show six orders of magnitude in switching ratio and a SS of 965 mV/dec, which is similar to the counterpart of the SOI Si NW sensor. In addition, the poly-Si NW FET sensors show the V th shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. Therefore, the design and fabricated poly-Si NW sensor arrays approach provides a good option for its potential application of the monolithic 3D-ICs in the future.