High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (μFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, μFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2. The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2/SnO2 interfaces to increase the mobility. Such high μFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.


Introduction
The development of high-performance transistors has been continuously pursued for more than seven decades, since the transistor was invented in 1947. The metal-oxide thin-film transistor (TFT) was invented in 1964 [1], and had the important merits of low-temperature fabrication, a simple process for mass production, and visible light transparency . Moreover, metal-oxide TFTs have widely diverse applications, such as in active matrix organic light emitting diodes [2,3], flexible electronics [4][5][6][7], and gas sensors [8][9][10]. By applying a high-mobility channel material and high-dielectric-constant (high-κ) gate dielectric, metal-oxide TFT can also be used in high-speed low-power monolithic three-dimensional (3D) integrated circuits (ICs) [11][12][13][14][15][16]. Furthermore, the wide energy bandgap, excellent field-effect mobility (µ FE ) at high temperatures, and low leakage current of metal-oxide TFTs are especially important for high-temperature electronics [17] and dynamic random-access memory (DRAM) access transistors. In this paper, we report a top-gate SnO 2 TFT that uses a combined HfO 2 and SiO 2 stack as a gate dielectric layer and an SnO 2 channel layer. The top-gate TFT structure is more favorable than the bottom-gate device, owing to its high performance and easy integration in forming an IC. This top-gate device, with an SiO 2 interfacial layer between HfO 2 and SnO 2 , exhibited an excellent device performance, with a remarkably high µ FE of 136 cm 2 /Vs, a large on-/off-current (I ON /I OFF ) of 1.5 × 10 8 , a sharp subthreshold slope (SS) of 108 mV/dec, and a much better resistance to moisture than the bottom-gate SnO 2 TFT. Here, the SiO 2 interfacial layer with a thickness of 3 nm is the key factor in decreasing the charged defect scattering inside HfO 2 and increasing the µ FE . Such high-performance TFTs are crucial for future-generation high-resolution displays, DRAM access transistors, high interconnect-density monolithic 3D ICs, and 3D brain-mimicking ICs [11][12][13], where the down-scaling of silicon ICs is expected to be ended at an equivalent node around 1 nm within ten years.

Materials and Methods
P-type silicon wafers with~10 ohmic-cm resistivity were used as substrates. A standard IC cleaning process was applied to remove the particles and native oxide from the silicon substrate. Then, an SiO 2 layer with a thickness of 300 nm was formed on the substrate, and was used as an inter-metal-dielectric layer of the IC. Thereafter, a 4.5 nm SnO 2 layer was deposited through reactive sputtering with a Sn target under a pressure of 7.6 × 10 −3 torr, a mixture of O 2 /Ar gas flow at 20/24 sccm, and a DC power of 50 W. The deposited SnO 2 layer was subjected to post-annealing at 350 • C in ambient air for 30 min. Next, 30 nm low work function aluminum Schottky source and drain electrodes [27,28] were deposited and patterned. Subsequently, a 3 nm SiO 2 layer and a 50 nm high-κ HfO 2 gate dielectric were deposited on the SnO 2 layer through physical vapor deposition. Finally, a 30 nm Ni top-gate electrode was created using electron-beam evaporation and patterning. The gate length and width are 50 and 400 µm, respectively. Material analyses through X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), and high-resolution transmission electron microscopy (TEM) were performed using Thermo Nexsa (Thermo Fisher Scientific Inc., Waltham, MA, USA), CAMECA IMS-6fE7 (CAMECA, Gennevilliers, France), and FEI Talos F200X (FEI company, Hillsboro, OR, USA), respectively. The electrical characterization of the device was measured using the HP4155B semiconductor parameter analyzer (HP, Englewood, CO, USA) and a probe station. Figure 1a presents the drain-source current versus gate-source voltage (I DS -V GS ) characteristics of the top-gate TFTs with and without the SiO 2 interfacial layer between the SnO 2 channel and the HfO 2 gate dielectric. The devices, with and without the ultra-thin SiO 2 , exhibit good I ON /I OFF s of 1.5 × 10 8 and 1 × 10 8 , respectively, and sharp turn-on SS values of 108 and 117 mV/dec, respectively. The interface trap density (D it ) can be calculated from SS [29,30]:

Results and Discussion
where C dep is the depletion capacitance. A D it of 5.5 × 10 12 eV −1 cm −2 is obtained, which is higher than the high-κ/silicon transistor. Further interface improvement can increase the SS and µ FE . To understand the significantly better the IDS and μFE data for TFTs with an ultra-thin SiO2 layer, we further measured the gate-source current versus gate-source voltage (IGS-VGS) characteristics. As shown in Figure 2a, the gate leakage current does not demonstrate a significant difference between these two devices because the interfacial SiO2 layer was only 3 nm thick, and much thinner than the high-κ HfO2, which had a thickness of 50 nm. The IDS versus the drain-source voltage (IDS-VDS)  1b depicts the µ FE -V GS characteristics of these devices. The µ FE was obtained by a standard method used in silicon IC from the trans-conductance (g m ) at a small V DS of 0.1 V: where W G , L G , and C ox are the gate width, gate length, and oxide capacitance, respectively. The C ox was obtained from the measured C-V characteristics divided by the area of the Ni/HfO 2 /SiO 2 /Al MIM device on the same chip. The SnO 2 TFT with an SiO 2 interfacial layer has a µ FE as high as 136 cm 2 /Vs, which is significantly higher than the 49.3 cm 2 /Vs for the device without the SiO 2 layer. This is the highest µ FE value for top-gate TFTs made on an amorphous SiO 2 substrate and processed at a temperature of ≤400 • C [21][22][23][24][25].
To understand the significantly better the I DS and µ FE data for TFTs with an ultra-thin SiO 2 layer, we further measured the gate-source current versus gate-source voltage (I GS -V GS ) characteristics. As shown in Figure 2a, the gate leakage current does not demonstrate a significant difference between these two devices because the interfacial SiO 2 layer was only 3 nm thick, and much thinner than the high-κ HfO 2 , which had a thickness of 50 nm. The I DS versus the drain-source voltage (I DS -V DS ) characteristics are presented in Figure 2b. The TFT device with the ultra-thin SiO 2 layer exhibits a higher I DS than the TFT without it, which is consistent with the I DS -V GS and µ FE -V GS data presented in Figure 1a,b, because the higher I DS leads to a higher µ FE value. To understand the significantly better the IDS and μFE data for TFTs with an ultra-thin SiO2 layer, we further measured the gate-source current versus gate-source voltage (IGS-VGS) characteristics. As shown in Figure 2a, the gate leakage current does not demonstrate a significant difference between these two devices because the interfacial SiO2 layer was only 3 nm thick, and much thinner than the high-κ HfO2, which had a thickness of 50 nm. The IDS versus the drain-source voltage (IDS-VDS) characteristics are presented in Figure 2b. The TFT device with the ultra-thin SiO2 layer exhibits a higher IDS than the TFT without it, which is consistent with the IDS-VGS and μFE-VGS data presented in Figure 1a,b, because the higher IDS leads to a higher μFE value. An XPS analysis was performed on both the HfO2/SiO2/SnO2 and the HfO2/SnO2 stacks. Before the analysis, both samples were sputter-etched from HfO2 to SnO2 at a slow rate of 0.1 nm/s. As shown in Figure 3, the Sn 3d5/2 spectrum of the SnOx layer is split into three peaks: Sn 4+ , Sn 2+ , and Sn 0 . The binding energies of the Sn 4+ , Sn 2+ , and Sn 0 peaks were 487, 486.5, and 485.2 eV, respectively. The intensity of Sn 2+ is related to the p-type SnO TFT [18]. By contrast, Sn 4+ conducts electrons for n-type TFTs [11][12][13][14][15][16]. As the results obtained using XPS analysis do not indicate obvious differences between these two samples, the inserted SiO2 interfacial layer has little effect on the chemical composition of the SnOx channel layer. An XPS analysis was performed on both the HfO 2 /SiO 2 /SnO 2 and the HfO 2 /SnO 2 stacks. Before the analysis, both samples were sputter-etched from HfO 2 to SnO 2 at a slow rate of 0.1 nm/s. As shown in Figure 3, the Sn 3d 5/2 spectrum of the SnO x layer is split into three peaks: Sn 4+ , Sn 2+ , and Sn 0 . The binding energies of the Sn 4+ , Sn 2+ , and Sn 0 peaks were 487, 486.5, and 485.2 eV, respectively. The intensity of Sn 2+ is related to the p-type SnO TFT [18]. By contrast, Sn 4+ conducts electrons for n-type TFTs [11][12][13][14][15][16]. As the results obtained using XPS analysis do not indicate obvious differences between these two samples, the inserted SiO 2 interfacial layer has little effect on the chemical composition of the SnO x channel layer. We further investigated the HfO2/SiO2/SnO2 stack through TEM and SIMS measurements. Figure  4a displays the cross-sectional TEM image of the SnO2 TFT with an SiO2 interfacial layer, where the thicknesses of HfO2, SiO2, and SnO2 were 50, 3, and 4.5 nm, respectively. The distributions of the Sn, Si, Hf, and O atoms in the gate stack and channel layer are depicted from the SIMS depth profiles in Figure 4b. An SiO2 interfacial layer was clearly observed in both the TEM and SIMS analyses.  It is important to note that the extra SiO2 interfacial layer will increase the thickness of the gate dielectric slightly and theoretically lead to a slightly higher transistor threshold voltage (VTH) than the device without the SiO2 layer. However, the IDS-VGS characteristics of the SnO2 devices in Figure  1a display a contrary result. Thus, the increased VTH for the device without the interfacial SiO2 layer is due to the extra negative charges formed in HfO2. These negative charges may also exist in the HfO2/SnO2 interface because the interface charges are strongly related to SS [22], which improves with the extra SiO2 interfacial layer, as shown in Figure 1a. Further, such negative charges in the HfO2 and HfO2/SnO2 interfaces can cause electron scattering and degrade the mobility [31,32], as shown in Figure 1b. It is known that the high-κ gate dielectric has defects, especially when formed at low  We further investigated the HfO 2 /SiO 2 /SnO 2 stack through TEM and SIMS measurements.   We further investigated the HfO2/SiO2/SnO2 stack through TEM and SIMS measurements. Figure  4a displays the cross-sectional TEM image of the SnO2 TFT with an SiO2 interfacial layer, where the thicknesses of HfO2, SiO2, and SnO2 were 50, 3, and 4.5 nm, respectively. The distributions of the Sn, Si, Hf, and O atoms in the gate stack and channel layer are depicted from the SIMS depth profiles in Figure 4b. An SiO2 interfacial layer was clearly observed in both the TEM and SIMS analyses.  It is important to note that the extra SiO2 interfacial layer will increase the thickness of the gate dielectric slightly and theoretically lead to a slightly higher transistor threshold voltage (VTH) than the device without the SiO2 layer. However, the IDS-VGS characteristics of the SnO2 devices in Figure  1a display a contrary result. Thus, the increased VTH for the device without the interfacial SiO2 layer is due to the extra negative charges formed in HfO2. These negative charges may also exist in the HfO2/SnO2 interface because the interface charges are strongly related to SS [22], which improves with the extra SiO2 interfacial layer, as shown in Figure 1a. Further, such negative charges in the HfO2 and HfO2/SnO2 interfaces can cause electron scattering and degrade the mobility [31,32], as shown in Figure 1b. It is known that the high-κ gate dielectric has defects, especially when formed at low  It is important to note that the extra SiO 2 interfacial layer will increase the thickness of the gate dielectric slightly and theoretically lead to a slightly higher transistor threshold voltage (V TH ) than the device without the SiO 2 layer. However, the I DS -V GS characteristics of the SnO 2 devices in Figure 1a display a contrary result. Thus, the increased V TH for the device without the interfacial SiO 2 layer is due to the extra negative charges formed in HfO 2. These negative charges may also exist in the HfO 2 /SnO 2 interface because the interface charges are strongly related to SS [22], which improves with the extra SiO 2 interfacial layer, as shown in Figure 1a. Further, such negative charges in the HfO 2 and HfO 2 /SnO 2 interfaces can cause electron scattering and degrade the mobility [31,32], as shown in Figure 1b. It is known that the high-κ gate dielectric has defects, especially when formed at low temperatures. The negative charges formed in the HfO 2 and HfO 2 /SnO 2 interfaces cause channel electron scattering and mobility degradation, which can be observed in the schematic diagrams illustrated in Figure 5a,b. The device with the SiO 2 interfacial layer has less negative charge scattering in HfO 2 and the interface because of the separation of the SiO 2 layer, which results in a higher mobility and I DS .
temperatures. The negative charges formed in the HfO2 and HfO2/SnO2 interfaces cause channel electron scattering and mobility degradation, which can be observed in the schematic diagrams illustrated in Figure 5a,b. The device with the SiO2 interfacial layer has less negative charge scattering in HfO2 and the interface because of the separation of the SiO2 layer, which results in a higher mobility and IDS. Figure 5. The schematic diagrams for electron transport in (a) with (b) without an SiO2 interfacial layer. Negative charges formed in HfO2 for a device without an SiO2 layer will increase the electron scattering and lower the mobility.
The moisture degradation of TFT devices is a significant issue for an IC. Figure 6 illustrates the IDS-VGS characteristics for the as-fabricated top-gate coplanar and bottom-gate staggered SnO2 TFTs in ambient air after 7 days and 30 days of exposure to air. The IDS-VGS characteristics of the bottomgate SnO2 TFT are shifted as high as 1.5 V after 7 days of exposure, and the IOFF, SS, and ION further degrade significantly after 30 days of exposure to air. This is because the top SnO2 layer can react with H2O molecules in the air and form Sn-OH bonds [14,19,20], resulting in charged defects that lower the IDS and μFE. The penetration of OHinto the SnO2 could also form defects and lead to a higher IOFF by defect conduction [26]. In sharp contrast, only a slight VTH shift of −0.09 V was observed in the top-gate device because the gate dielectric HfO2 layer can behave as a passivation layer on the SnO2 channel layer. The slight VTH shift might be attributed to the intrinsic defects of the HfO2 layer and the charge trapping and de-trapping phenomena of those defects [33,34].   The moisture degradation of TFT devices is a significant issue for an IC. Figure 6 illustrates the I DS -V GS characteristics for the as-fabricated top-gate coplanar and bottom-gate staggered SnO 2 TFTs in ambient air after 7 days and 30 days of exposure to air. The I DS -V GS characteristics of the bottom-gate SnO 2 TFT are shifted as high as 1.5 V after 7 days of exposure, and the I OFF , SS, and I ON further degrade significantly after 30 days of exposure to air. This is because the top SnO 2 layer can react with H 2 O molecules in the air and form Sn-OH bonds [14,19,20], resulting in charged defects that lower the I DS and µ FE . The penetration of OHinto the SnO 2 could also form defects and lead to a higher I OFF by defect conduction [26]. In sharp contrast, only a slight V TH shift of −0.09 V was observed in the top-gate device because the gate dielectric HfO 2 layer can behave as a passivation layer on the SnO 2 channel layer. The slight V TH shift might be attributed to the intrinsic defects of the HfO 2 layer and the charge trapping and de-trapping phenomena of those defects [33,34]. Nanomaterials 2020, 10, x FOR PEER REVIEW 5 of 8 temperatures. The negative charges formed in the HfO2 and HfO2/SnO2 interfaces cause channel electron scattering and mobility degradation, which can be observed in the schematic diagrams illustrated in Figure 5a,b. The device with the SiO2 interfacial layer has less negative charge scattering in HfO2 and the interface because of the separation of the SiO2 layer, which results in a higher mobility and IDS. Figure 5. The schematic diagrams for electron transport in (a) with (b) without an SiO2 interfacial layer. Negative charges formed in HfO2 for a device without an SiO2 layer will increase the electron scattering and lower the mobility.
The moisture degradation of TFT devices is a significant issue for an IC. Figure 6 illustrates the IDS-VGS characteristics for the as-fabricated top-gate coplanar and bottom-gate staggered SnO2 TFTs in ambient air after 7 days and 30 days of exposure to air. The IDS-VGS characteristics of the bottomgate SnO2 TFT are shifted as high as 1.5 V after 7 days of exposure, and the IOFF, SS, and ION further degrade significantly after 30 days of exposure to air. This is because the top SnO2 layer can react with H2O molecules in the air and form Sn-OH bonds [14,19,20], resulting in charged defects that lower the IDS and μFE. The penetration of OHinto the SnO2 could also form defects and lead to a higher IOFF by defect conduction [26]. In sharp contrast, only a slight VTH shift of −0.09 V was observed in the top-gate device because the gate dielectric HfO2 layer can behave as a passivation layer on the SnO2 channel layer. The slight VTH shift might be attributed to the intrinsic defects of the HfO2 layer and the charge trapping and de-trapping phenomena of those defects [33,34].  In Table 1, we summarize the important device characteristics and compare them with the published data on top-gate TFTs made on amorphous SiO 2 substrates [21][22][23][24][25]. Our device with an ultra-thin channel thickness of 4.5 nm exhibits the highest µ FE , a sharp SS for low-voltage operation, and a sufficiently large I ON /I OFF , which are crucial for display, low-leakage DRAM access transistors, and monolithic 3D IC applications. Further improvement of µ FE and SS may be reachable by using a thicker SnO 2 layer than the 4.5 nm thickness and a Fin Field-Effect Transistor (FinFET) or gate-all-around structure, respectively.

Conclusions
An excellent device integrity was achieved for a top-gate TFT made on an amorphous SiO 2 substrate using a low process temperature of 350 • C with a high µ FE of 136 cm 2 /Vs, a sharp SS of 108 mV/dec for low-voltage operations, and a sufficiently large I ON /I OFF of 1.5 × 10 8 . Such a top-gate structure is preferred for monolithic IC as compared to bottom-gate devices. In addition, a much better resistance to moisture can be achieved than in the bottom-gate device without passivation. Such a superb device performance is strongly related to the inserted ultra-thin SiO 2 layer between the HfO 2 and SnO 2 . The outstanding device performance with top-gate structure is a crucial technology for future-generation high-resolution displays, low-leakage DRAM access transistors, and monolithic 3D brain-mimicking ICs.