Understanding the Origin of the Hysteresis of High-Performance Solution Processed Polycrystalline SnO2 Thin-Film Transistors and Applications to Circuits

Crystalline tin oxide has been investigated for industrial applications since the 1970s. Recently, the amorphous phase of tin oxide has been used in thin film transistors (TFTs) and has demonstrated high performance. For large area electronics, TFTs are well suited, but they are subject to various instabilities due to operating conditions, such as positive or negative bias stress PBS (NBS). Another instability is hysteresis, which can be detrimental in operating circuits. Understanding its origin can help fabricating more reliable TFTs. Here, we report an investigation on the origin of the hysteresis of solution-processed polycrystalline SnO2 TFTs. We examined the effect of the carrier concentration in the SnO2 channel region on the hysteresis by varying the curing temperature of the thin film from 200 to 350 °C. Stressing the TFTs characterized further the origin of the hysteresis, and holes trapped in the dielectric are understood to be the main source of the hysteresis. With TFTs showing the smallest hysteresis, we could fabricate inverters and ring oscillators.

Single cation-based oxides demonstrate a polycrystalline phase with higher mobilities. Zinc oxide (ZnO) [6], indium oxide (In 2 O 3 ) [3], and tin oxide (SnO 2 ) [7] are among the most investigated materials. One of the most valuable metrics in TFTs is the mobility, and ZnO TFTs have demonstrated 40-70 cm 2 /Vs [6,8] while In 2 O 3 TFTs [4] have demonstrated mobilities~50 cm 2 /Vs. Even the crystalline form of IGZO (c-axis crystalline IGZO, the so called CAAC-IGZO) has attracted attention due to the TFTs reaching mobilities 90 cm 2 /Vs [9,10]. For a few years now, tin oxide has regained attention. Devices comprising SnO 2 have demonstrated high mobility. Perovskite solar cells [11,12] and TFTs have been the main focus of research. TFTs have shown mobilities ranging from 40 to 147 cm 2 /Vs [13,14]. Even more recently, the amorphous phase of tin oxide [15,16] has demonstrated possible use in TFTs, reaching similar performances as the polycrystalline counterpart. Interestingly, in all these studies authors used a high-k dielectric as the gate insulator (ZrO 2 , HfO 2 , Al 2 O 3 ) , and a very thin channel layer (less than 10 nm).
With the use of high-k dielectrics [17], it is possible to obtain clockwise or anticlockwise hysteresis in the TFTs. The reasons are multiple, but shortly, in n-type based TFTs, the clockwise hysteresis can be resulting from the semiconductor (trapping of the electrons), while the anticlockwise from the gate dielectric (due to the movement of mobile ions for example) [18]. The anticlockwise behavior can be used in memory devices, while it can be detrimental for circuits. To fully understand the origin of the hysteresis (i.e., trapping of charge carriers, movement of mobile ions in the semiconductor or in the dielectric), measuring the hysteresis at slow and fast rates can help discriminate the origin.
We previously demonstrated that solution processed SnO 2 using SnCl 2 precursors could have various phases, and that the curing and annealing temperatures could impact significantly the various optical, electrical, and physical properties [19]. Here, we implemented the polycrystalline SnO 2 thin films fabricated at various T curing temperatures (200, 280, and 350 • C) and a fixed annealing temperature (T anneal = 350 • C). High mobility TFTs (over 100 cm 2 /Vs) are obtained and we studied the hysteresis behaviors of the polycrystalline SnO 2 TFTs (poly-SnO 2 TFTs). By varying the sweep rate and applying negative and positive bias stresses to the TFTs, we can clearly identify the origin of the hysteresis.

Fabrication of the Precursor Solutions
Solutions of HfO 2 (SnO 2 ) were made by mixing HfCl 4 (SnCl 2 ) into a mixture of acetonitrile (Ac) and ethyleneglycol (Etg). We used 35% of Ac and 65% of Etg in volume%. The HfO 2 (SnO 2 ) precursor solutions were stirred in a N 2 environment for 2 h (24 h) before use. The HfO 2 precursor solutions had a concentration of 0.2 M and the SnO 2 ones had a concentration of 0.2 M for the thin films, and 0.167 M for the TFTs.

Thin Film Fabrication and Analysis
The SnO 2 thin films were fabricated by spin-coating at 2000 rpm during 25 s. After spin-coating, the layer was subject to a curing at 100 • C for 5 min, and a second curing step at 200, 280, or 350 • C for 5 min. The coating was repeated once. We measured the Hall effect on a Ecopia HMS-3000. The samples had a van der Pauw configuration. The data was collected from 15 points. We used the Kα line (1.54 Å) for X-ray diffraction measurement to evaluate the crystallinity of the thin films. The surface roughness was evaluated by atomic force microscopy (AFM) by using a XE-7 from Park systems. The optical properties were evaluated by using an Scinco S4100. We measured X-ray photospectroscopy (XPS) with a Nexsa from ThermoFisher Scientific, by using the Al-Ka at 1486.6 eV as the X-ray source. Calibration was made with the carbon peak at 284.8 eV.

Thin Film Transistor Fabrication and Analysis
We fabricated poly-SnO 2 TFTs by first sputtering 40 nm Mo as the gate on glass. After patterning, we spin-coated the HfO 2 film. The coating was made at 2000 rpm for 25 s. The layer was then subject to a curing at 250 • C for 5 min, and UV treatment during 90 s. The deposition, curing, and treatment were repeated to obtain a 95 nm thick HfO 2 layer. The samples were then subject to annealing at 350 • C for 2 h in air. The precursor solution of SnO 2 was spin-coated at 4000 rpm during 25 s, and followed a curing step explained in the previous paragraph. After patterning, the TFTs were annealed at 350 • C for 2 h in air. We created via holes, sputtered and patterned IZO as the source/drain electrodes. Finally, a hot-plate annealing at 300 • C for 2 h and another hot-plate annealing step at 350 • C for 1 h were performed.
We measured the TFTs IV curves with a 4156 C semiconductor parameter analyzer. The TFTs had a width W and a length L of 50 and 10 µm, respectively. We evaluated the field-effect mobility in the linear region where Cox is the HfO 2 capacitance. The threshold voltage was evaluated at W/L × 10 −10 A. The slope was evaluated as The various parameters were averaged over 25 TFTs. The various parameters are extracted from the transfer curve measured at fast measurement rate, from negative to positive voltage. The hysteresis was measured at V DS = 0.1 V, with a fast and a slow measurement rate related to an integration time of 6.04, and 20 ms, respectively. The positive (negative) bias stress PBS (NBS) were measured by applying V GS = 3 V (−3 V) during 1 h. We note that the capacitance of the hafnium oxide dielectric was 219 nF/cm 2 [15].

Circuit Fabrication
The inverter and ring oscillator followed the same process steps as the TFTs. The inverter had a load TFT with width and length of 50 and 6µm, respectively. The driving TFT had a width and length of 400 µm and 6 µm. The inverter had a depletion mode structure with the gate of the load TFT connected to the output.
The ring oscillator consisted of 11 of these inverters. The output of one is connected as the input of the following one. The last inverter being connected to the first inverter. A buffer inverter is put at the end of the ring oscillator to stabilize the measured output. Figure 1 shows the optical and crystalline properties of SnO 2 . Figure 1a shows the extraction of the band gap from the Tauc plot [20]. The films with a T curing of 200, 280, and 350 • C had a respective bandgap of 3.89, 3.94, and 3.94 eV. The films are adequate for application in invisible electronics [1]. Figure 1b Figure 2b) leads to the smoothest surface. We note that we observe the crystallite sizes were in the 10-25 nm range, with the biggest crystallites for the 350 °C cured film. We note that the roughnesses decrease then increase at 280 °C. This was previously reported to be due to the melting of SnCl2 at 250 We extracted the carrier concentration N and the Hall mobility µ H according to their definition:

Thin Film Analysis
Membranes 2022, 12, 7 4 of 12 where R H is the Hall coefficient, and ρ the electrical resistivity. For the SnO 2 film cured at 200, 280, and 350 • C, we observe an increase in the carrier concentration from 1.37 ± 0.19 to 4.28 ± 0.54 to 4.47 ± 1.20 × 10 18 cm −3 . The Hall mobility also increases from 1.56 ± 0.32 to 1.79 ± 0.67 and to 2.28 ± 0.92 cm 2 /Vs. The mobility increases with the carrier concentration as for oxide semiconductors which has been explained by the percolation conduction of the charge carriers [21]. Also, we note that the values match the trend previously reported for SnO 2 [19]. Figure 2 shows the surface morphologies of SnO 2 made at the different curing temperatures measured by AFM. The quality of the surface can be assessed by two metrics: the root mean square roughness (R rms ) and also the peak-to-valley roughness (R pv ). We note that we observe the crystallite sizes were in the 10-25 nm range, with the biggest crystallites for the 350 • C cured film. We note that the roughnesses decrease then increase at 280 • C. This was previously reported to be due to the melting of SnCl 2 at 250 • C [19], which would alter the crystallization of the 280 • C-cured thin films leading to a smoother surface.   Figure 2b) leads to the smoothest surface. We note that we observe the crystallite sizes were in the 10-25 nm range, with the biggest crystallites for the 350 °C cured film. We note that the roughnesses decrease then increase at 280 °C. This was previously reported to be due to the melting of SnCl2 at 250 °C [19], which would alter the crystallization of the 280 °C-cured thin films leading to a smoother surface.

Thin Film Transistor and the Origin of Their Hysteresis
The typical poly-SnO 2 TFT structure used in this work is shown at the bottom of Figure 3a. The micrograph of the TFT shown on top of Figure 3a reveals the various elements constituting the TFT. The hysteresis of the TFT transfer curves measured at fast and low rates, when SnO 2 was cured at 200, 280, and 350 • C are shown in Figure 3b-d, respectively. On average the TFTs made with a SnO 2 thin film cured at 200, 280, and 350 • C show a linear mobility of 86 ± 12, 90 ± 12, 110 ± 35 cm 2 /Vs; a V th of −0.04 ± 0.05, 0.02 ± 0.12, −0.19 ± 0.14 V; and a subthreshold swing of 103.7 ± 9.9, 112.9 ± 9.4, and 102.7 ± 8.4 mV/dec. We note that the reliability of the extraction of the mobility in particular is highly depending on the size of the TFT [22]. The size chosen in the study should not have a significant impact on the mobility value [15,22]. We gather in Table 1 our present results and various other TFT performances using polycrystalline oxide semiconductors. linear mobility of 86 ± 12, 90 ± 12, 110 ± 35 cm /Vs; a Vth of −0.04 ± 0.05, 0.02 ± 0.12, −0.19 ± 0.14 V; and a subthreshold swing of 103.7 ± 9.9, 112.9 ± 9.4, and 102.7 ± 8.4 mV/dec. We note that the reliability of the extraction of the mobility in particular is highly depending on the size of the TFT [22]. The size chosen in the study should not have a significant impact on the mobility value [15,22]. We gather in Table 1 our present results and various other TFT performances using polycrystalline oxide semiconductors.
We note that even though the hysteresis is an important parameter, the characterization is only seldom reported.   We note that even though the hysteresis is an important parameter, the characterization is only seldom reported.
At the T curing of 200 and 280 • C, the hysteresis is clockwise, and the slow sweep rate measurements lead to higher hysteresis than the fast sweep rate measurements. We note that the slow sweep rate hysteresis for the 280 • C-cured-SnO 2 is smaller than the TFTs with the 200 • C-cured-SnO 2 layer. Also, the fast sweep measurement rate leads to a~0.15 V hysteresis. At T curing of 350 • C, an anticlockwise hysteresis is observed, and the fast sweep rate leads to higher hysteresis than the slow sweep rate. The reason why the TFT only shows the anticlockwise hysteresis will be discussed later.
A slow mobility species or a slow phenomenon responsible for the hysteresis for the 200-and 280 • C cured SnO 2 based TFT could be the reason for the slow sweep measurement rate leading to higher hysteresis than the fast measurement rate [18]. Also, the amount of the species would be smaller in the former than the later. The anticlockwise hysteresis is usually resulting from moving ions in the dielectric, from charge carriers entering the dielectric, or from the polarization of the dielectric. An anticlockwise hysteresis resulting from the polarization of the dielectric would have appeared in all conditions, and cannot therefore explain the behavior of our TFTs. Also, a clockwise hysteresis usually results from charge carriers near/at the channel/dielectric interface. To clarify the underlying phenomenon, we performed PBS and NBS on the TFTs, and measured the hysteresis. resis appearing under NBS suggests that holes could enter the dielectric during the stress. Figure 4d,e show that the 200-and 280°C-cured SnO2 TFT have a positive shift and a decrease in the current under PBS. Also, we observe the decrease of IGS in Figure 4d,e. The decrease in the IGS is almost one order of magnitude for the 200 °C-cured TFT. For the 350 °C-cured TFT, we observe that the TFT current decreases without a significant change in the Vth. Therefore, considering the various stresses and the various change in Vth and the change in IGS, we understand that charge carriers are injected from and to the dielectric. We therefore evaluated the band offsets between SnO2 and HfO2 for all three different curing temperatures of SnO2 [26]. The valence band offset ΔEv is defined as

Bias Stress Effect on Poly-SnO 2 Thin-Film Transistors
where HfO2surface, SnO2surface and SnO2/HfO2 denote, respectively, the top of the HfO2 layer without SnO2 on top of it, the top of the SnO2 layer, and the HfO2/SnO2 interface. Therefore, for each curing temperature we extracted the following peak values: the Hf 4f peak at the SnO2/HfO2 interface (as shown in Figure 5a,e,i), the Sn 3d5/2 peak at the   Figure 4d,e. The decrease in the I GS is almost one order of magnitude for the 200 • C-cured TFT. For the 350 • C-cured TFT, we observe that the TFT current decreases without a significant change in the V th . Therefore, considering the various stresses and the various change in V th and the change in I GS , we understand that charge carriers are injected from and to the dielectric.
We therefore evaluated the band offsets between SnO 2 and HfO 2 for all three different curing temperatures of SnO 2 [26]. The valence band offset ∆E v is defined as where HfO 2surface , SnO 2surface and SnO 2 /HfO 2 denote, respectively, the top of the HfO 2 layer without SnO 2 on top of it, the top of the SnO 2 layer, and the HfO 2 /SnO 2 interface. Therefore, for each curing temperature we extracted the following peak values: the Hf 4f peak at the SnO 2 /HfO 2 interface (as shown in Figure 5a,e,i), the Sn 3d 5/2 peak at the SnO 2 /HfO 2 interface (as shown in Figure 5b,f,j), the Sn 3d 5/2 peak on the top of the SnO 2 layer (Figure 5c,g,k), and the valence band at the top of the SnO 2 layer (as shown in Figure 5d,h,l). The various extracted values are gathered in Table 2. We note that the values for the position peaks taken for HfO 2 without SnO 2 on top are taken from a previous report [16] and we consider the Hf 4f peak position E Hf4f = 18.15 eV, the bandgap of HfO 2 Eg HfO2 = 5.34 eV, and the position of the valence band E VBM = 2.4 eV.
Membranes 2022, 11, x FOR PEER REVIEW 9 of 12 gathered in Table 2. Figure 6b,c summarize the proposed mechanism of the hole extraction (injection) during PBS (NBS).  The letters in the cells correspond to the peak and peak position shown in the letter-designated-subfigure of Figure 5. We could evaluate that the valence band offset was 0.17, 0.19 and 0.09 eV for the 200-280-and 350 • C-cured SnO 2 layer, respectively. To avoid charge carrier injection, the offset value should be bigger than 1 eV [27]. So, our TFTs having a smaller band offset could have holes injected into the dielectric.
The small offset can therefore explain the possibility of holes to be trapped into (detrapped from) the dielectric under NBS (PBS). The presence of trapped holes in the dielectric would add up to the electric field attracting more electrons in the channel resulting in an anticlockwise hysteresis. Under PBS, holes can exit the dielectric leading to a decrease in the gate leakage, but also a decrease in the electron current. Thus, trapping of electrons would lead to the observed clockwise hysteresis.
The fact that only the 350 • C-cured SnO 2 TFT demonstrate the anticlockwise hysteresis could result from the higher density of holes in the SnO 2 layer compared to the other temperature cured SnO 2 layer based TFTs. Also, the TFT cured at 350 • C showed an apparent higher mobility. But this value is certainly due to the presence of injected holes in the gate insulator increasing the electron density in the channel during operation and therefore leading to an increased value of the mobility. We note that the 280 • C-cured-SnO 2 layer showing the smallest R RMS and R pp value leads to the TFT with the smallest clockwise hysteresis. As mentioned before, we previously studied the fabrication of SnO 2 thin films at various curing and annealing temperatures [19]. We demonstrated that the melting of the precursors at 250 • C had an impact on the various properties of the thin films. The various films had an increase of the R rms roughness and R PV for temperatures higher than the melting temperature. The TFT properties are consistent with the thin film fabrication process and their properties.
Also, we note that holes should be moving slowly in SnO 2 , as they would in IGZO with a mobility of~0.01 cm 2 /Vs [28]. Under NBS, holes may be injected from the SnO 2 layer to the dielectric and be trapped, resulting in a negative shift and the anticlockwise hysteresis. This also explains the change of the hysteresis direction for the 280 • C-cured SnO 2 based TFT shown in Figure 4b. Therefore, we propose that the main phenomenon responsible for the hysteresis in our solution-processed SnO 2 TFT is the trapping of holes in the dielectric. Detrapping or trapping of holes would therefore monitor the hysteresis. Figure 6 shows the band offsets between HfO 2 and polycrystalline SnO 2 Figure 6a summarizes the bandgaps (3.89-3.94 eV for SnO 2 , 5.34 eV for HfO 2 ), ∆E v (0.09-0.19 eV), and ∆Ec (deduced from the previous values). To find ∆E v, we used the values taken from Figure 5, and gathered in Table 2. Figure 6b,c summarize the proposed mechanism of the hole extraction (injection) during PBS (NBS). ranes 2022, 11, x FOR PEER REVIEW 9 of 12 gathered in Table 2. Figure 6b,c summarize the proposed mechanism of the hole extraction (injection) during PBS (NBS).

Application to Circuits: Inverters and Ring Oscillators
We fabricated both inverters and ring oscillators as circuits to demonstrate the possibility to incorporate SnO2 TFT in more advanced circuitry. We chose the devices with a curing step at 280 °C. Indeed, the TFTs showed the clockwise hysteresis. Compared to the 200 °C cured TFTs, the 280 °C-cured TFTs demonstrated smaller hysteresis and higher mobility. We note that the ring oscillators using the TFTs with the anticlockwise hysteresis could not show any oscillation. Figure 7a,b show the respective schematics of an inverter and a ring oscillator (R.O.). The inverter output is shown in Figure 7c. At 5 V the gain is ~30 V/V. The top of Figure 7d shows the optical image of a fabricated ring oscillator, and its various components. In the figure, we indicated the basic inverter structure, but also the buffer. The bottom of Figure 7d shows the output of the R.O. at a Vdd of 3 V. The peakto-peak voltage (Vpp) is 1.862 V, the frequency is 2.12 kHz. Even though the operating frequency is rather low, which could be due to the low sheet resistance of IZO (~20 ohm/□), and the non-optimized ratio of the TFTs, the present results demonstrate the possibility to further include poly-SnO2 TFTs in other more advanced circuitry.

Application to Circuits: Inverters and Ring Oscillators
We fabricated both inverters and ring oscillators as circuits to demonstrate the possibility to incorporate SnO 2 TFT in more advanced circuitry. We chose the devices with a curing step at 280 • C. Indeed, the TFTs showed the clockwise hysteresis. Compared to the 200 • C cured TFTs, the 280 • C-cured TFTs demonstrated smaller hysteresis and higher mobility. We note that the ring oscillators using the TFTs with the anticlockwise hysteresis could not show any oscillation. Figure 7a,b show the respective schematics of an inverter and a ring oscillator (R.O.). The inverter output is shown in Figure 7c. At 5 V the gain is~30 V/V. The top of Figure 7d shows the optical image of a fabricated ring oscillator, and its various components. In the figure, we indicated the basic inverter structure, but also the buffer.
The bottom of Figure 7d shows the output of the R.O. at a V dd of 3 V. The peak-to-peak voltage (V pp ) is 1.862 V, the frequency is 2.12 kHz. Even though the operating frequency is rather low, which could be due to the low sheet resistance of IZO (~20 ohm/ ), and the non-optimized ratio of the TFTs, the present results demonstrate the possibility to further include poly-SnO 2 TFTs in other more advanced circuitry.

Application to Circuits: Inverters and Ring Oscillators
We fabricated both inverters and ring oscillators as circuits to demonstrate the possibility to incorporate SnO2 TFT in more advanced circuitry. We chose the devices with a curing step at 280 °C. Indeed, the TFTs showed the clockwise hysteresis. Compared to the 200 °C cured TFTs, the 280 °C-cured TFTs demonstrated smaller hysteresis and higher mobility. We note that the ring oscillators using the TFTs with the anticlockwise hysteresis could not show any oscillation. Figure 7a,b show the respective schematics of an inverter and a ring oscillator (R.O.). The inverter output is shown in Figure 7c. At 5 V the gain is ~30 V/V. The top of Figure 7d shows the optical image of a fabricated ring oscillator, and its various components. In the figure, we indicated the basic inverter structure, but also the buffer. The bottom of Figure 7d shows the output of the R.O. at a Vdd of 3 V. The peakto-peak voltage (Vpp) is 1.862 V, the frequency is 2.12 kHz. Even though the operating frequency is rather low, which could be due to the low sheet resistance of IZO (~20 ohm/□), and the non-optimized ratio of the TFTs, the present results demonstrate the possibility to further include poly-SnO2 TFTs in other more advanced circuitry.

Conclusions
We successfully fabricated solution processed polycrystalline SnO2 TFTs. The SnO2 thin films were fabricated at various curing temperature to obtain various carrier concentrations, ranging from ~10 18 to ~4 × 10 18 cm −3 . The TFTs demonstrated a field effect mobility of ~100 cm 2 /Vs. We demonstrated that under stress the hysteresis present in the TFTs was due to the presence of trapped holes in the gate dielectric. We suggest that the trapping occurs due to the small valence band offset between SnO2 and HfO2. Nonetheless, we demonstrated the possibility of fabricating circuits with SnO2 TFTs. The inverters demonstrated a gain of ~30 V/V and the ring oscillators operated at a frequency of 2.12 kHz at a VDD of 3 V. Further optimization of the TFTs by increasing the valence band offset could lead to higher reliability and circuits with higher performances.

Conclusions
We successfully fabricated solution processed polycrystalline SnO 2 TFTs. The SnO 2 thin films were fabricated at various curing temperature to obtain various carrier concentrations, ranging from~10 18 to~4 × 10 18 cm −3 . The TFTs demonstrated a field effect mobility of~100 cm 2 /Vs. We demonstrated that under stress the hysteresis present in the TFTs was due to the presence of trapped holes in the gate dielectric. We suggest that the trapping occurs due to the small valence band offset between SnO 2 and HfO 2 . Nonetheless, we demonstrated the possibility of fabricating circuits with SnO 2 TFTs. The inverters demonstrated a gain of~30 V/V and the ring oscillators operated at a frequency of 2.12 kHz at a V DD of 3 V. Further optimization of the TFTs by increasing the valence band offset could lead to higher reliability and circuits with higher performances.

Conflicts of Interest:
The authors declare no conflict of interest.