Compact Model for L-Shaped Tunnel Field-E ﬀ ect Transistor Including the 2D Region

: The L-shaped tunneling ﬁeld-e ﬀ ect transistor (LTFET) is the only line-tunneling type of TFET to be experimentally demonstrated. To date, there is no literature available on the compact model of LTFET. In this paper, a compact model of LTFET is presented. LTFET has both one-dimensional (1D) and 2D band-to-band tunneling (BTBT) components. The 2D BTBT part dominates in the subthreshold region, whereas the 1D BTBT dominates at higher gate-source biases. The model consists of 1D and 2D BTBT models. The 2D BTBT model is based on the assumption that the electric ﬁeld originating from the gate and terminating at the source edge is perfectly circular. Tunneling path length is obtained by calculating the distance along an electric ﬁeld arc that runs from gate to source. The 1D BTBT model is based on a simultaneous solution of the 1D Poisson equation in source and channel regions. Expressions for electric ﬁeld and potential obtained from integrating the Poisson equation in source and channel regions are solved simultaneously to ﬁnd the surface potential. Once the surface potential is known, all the other unknown variables, including junction potential and source depletion length, can be calculated. Using the potential proﬁle, tunneling lengths were found for both the source-to-channel BTBT regime, and channel-to-channel BTBT regime. The tunneling lengths were used to calculate the BTBT tunneling rate, and ﬁnally, the drain-source current as a function of gate-source, and drain-source bias was calculated. The model results were compared against technology computer-aided design (TCAD) simulation results and were found to be in reasonable agreement for a compact model.


Introduction
With the power requirements of complementary metal-oxide-semiconductor (CMOS) technology surging beyond unreasonable levels to meet the high computing demands of today's world, there has been a desperate push for devices that can perform better for less power [1]. The tunnel field-effect transistor (TFET) is one such device among the potential candidate devices [2]. TFET works on the principle of band-to-band-tunneling (BTBT) and achieves a steeper subthreshold slope (SS) than a metal-oxide-semiconductor field-effect transistor (MOSFET) of equivalent dimensions and electrical parameters.
However, the on-current (I ON ) of TFET is lower than that of MOSFET of equivalent dimensions/electrical parameters. To overcome this problem, different types of TFET architectures have been suggested, including the line-tunneling type [3] TFETs. The structure of line tunneling type TFETs has a gate-source overlap. This overlap increases the BTBT area and consequently increases the I ON . The L-shaped TFET (LTFET) [4] is an example of a line-tunneling TFET that features the channel region grown vertically in the form of an L-shape. The LTFET offers the same benefits as a conventional line-tunneling type TFET, but with a much lower device footprint. More significantly, LTFET is the only example of a line-tunneling TFET that has been experimentally realized.
Compact modeling is an important part of the circuit design process. While there are compact models available for the conventional TFET [5][6][7], the literature is almost completely lacking in compact models for the line-tunneling type TFETs. Vandenberghe et al. [3] developed a compact model for conventional line-tunneling TFET. Najam et al. [8] developed a compact model for LTFET. However, the line-tunneling TFET considered in [3] features a significant difference from the LTFET: The gate directly overlaps with the source region, as shown in Figure 1 in [3], whereas in the LTFET, there is a channel region present between the source and the gate. Direct overlapping of gate/source without any channel layer present in between completely changes the electrostatics of the device and makes the model presented in [3] inapplicable to LTFET. In [8], only the one-dimensional (1D) model is presented. In LTFET, both 1D and 2D BTBT components are present.
This paper presents a complete model of the LTFET, including both the 2D and 1D BTBT, which is presented in Section 2. The model presented is continuous from the subthreshold region to strong inversion. The model is tested for LTFETs with varying geometries, and the results are presented in Section 3. A conclusion is presented in Section 4. Figure 1 shows the schematic of the LTFET. The channel region shown in blue color is found in an L-shape and is sandwiched between the gate and the source. The part of the channel region found in between the source and gate regions is termed as C overlap with height (H overlap ) = 40 nm and length (T j ) = 4 nm. The source and drain are p + (N a = 10 20 cm −3 ) and n + (N drain = 10 20 cm −3 ) doped, respectively, while the channel is lightly n − doped (N d = 10 15 cm −3 ). The source region height (H s ) and length (L s ) are 40 and 50 nm, respectively. The bottom part of the channel, which is not in between the source and gate regions, is termed as C nonoverlap and has a height (H nonoverlap ) = 20 nm, and length (L nonoverlap ) = 50 nm. An HfO 2 dielectric of thickness (t ox ) = 2 nm for gate oxide was considered.

Model Development
Appl. Sci. 2019, 9, x FOR PEER REVIEW 2 of 11 significantly, LTFET is the only example of a line-tunneling TFET that has been experimentally realized. Compact modeling is an important part of the circuit design process. While there are compact models available for the conventional TFET [5][6][7], the literature is almost completely lacking in compact models for the line-tunneling type TFETs. Vandenberghe et al. [3] developed a compact model for conventional line-tunneling TFET. Najam et al. [8] developed a compact model for LTFET. However, the line-tunneling TFET considered in [3] features a significant difference from the LTFET: The gate directly overlaps with the source region, as shown in Figure 1 in [3], whereas in the LTFET, there is a channel region present between the source and the gate. Direct overlapping of gate/source without any channel layer present in between completely changes the electrostatics of the device and makes the model presented in [3] inapplicable to LTFET. In [8], only the one-dimensional (1D) model is presented. In LTFET, both 1D and 2D BTBT components are present.
This paper presents a complete model of the LTFET, including both the 2D and 1D BTBT, which is presented in Section 2. The model presented is continuous from the subthreshold region to strong inversion. The model is tested for LTFETs with varying geometries, and the results are presented in Section 3. A conclusion is presented in Section 4. Figure 1 shows the schematic of the LTFET. The channel region shown in blue color is found in an L-shape and is sandwiched between the gate and the source. The part of the channel region found in between the source and gate regions is termed as Coverlap with height (Hoverlap) = 40 nm and length (Tj) = 4 nm. The source and drain are p + (Na = 10 20 cm −3 ) and n + (Ndrain = 10 20 cm −3 ) doped, respectively, while the channel is lightly n − doped (Nd = 10 15 cm −3 ). The source region height (Hs) and length (Ls) are 40 and 50 nm, respectively. The bottom part of the channel, which is not in between the source and gate regions, is termed as Cnonoverlap and has a height (Hnonoverlap) = 20 nm, and length (Lnonoverlap) = 50 nm. An HfO2 dielectric of thickness (tox) = 2 nm for gate oxide was considered. Dynamic nonlocal BTBT model [9], fermi statistics, and constant mobility models were considered in the technology computer-aided design (TCAD) simulation.

Model Development
As shown in Figure 1, the source has a sharp corner marked by an X in Figure 1. The electric field from the gate converges at and around this sharp source corner, increasing the potential around this point. The right axis in Figure 2a shows surface potential (φs) at Vgs = 0.15 V and Vds = 0.5 V. As shown in Figure 2a, φs sharply rises in Cnonoverlap because of convergence of the electric field, whereas φs is less in Coverlap where this convergence does not take place. This convergence affects the BTBT threshold voltage of Coverlap and Cnonoverlap. Cnonoverlap is found to have a lower BTBT threshold voltage because of this increased φs. Meanwhile, Coverlap has a significantly higher BTBT threshold voltage because of the lower potential [10]. This can be seen in Figure 2b, which shows integrated BTBT tunneling rates [10] (Gtuns) in x and y directions in Coverlap and Cnonoverlap, respectively; that is, Dynamic nonlocal BTBT model [9], fermi statistics, and constant mobility models were considered in the technology computer-aided design (TCAD) simulation.
As shown in Figure 1, the source has a sharp corner marked by an X in Figure 1. The electric field from the gate converges at and around this sharp source corner, increasing the potential around this point. The right axis in Figure 2a shows surface potential (ϕ s ) at V gs = 0.15 V and V ds = 0.5 V. As shown in Figure 2a, ϕ s sharply rises in C nonoverlap because of convergence of the electric field, whereas ϕ s is less in C overlap where this convergence does not take place. This convergence affects the BTBT threshold voltage of C overlap and C nonoverlap . C nonoverlap is found to have a lower BTBT threshold voltage because of this increased ϕ s . Meanwhile, C overlap has a significantly higher BTBT threshold voltage because of the lower potential [10]. This can be seen in Figure 2b, which shows integrated BTBT tunneling rates [10] (G tun s) in x and y directions in C overlap and C nonoverlap , respectively; that is, 0 L s +T j H overlap 0 G tun dxdy in C overlap (black triangles) and 0 L nonoverlap H nonoverlap H overlap G tun dxdy in C nonoverlap (red circles) in the left axis. Figure 2b clearly shows that C nonoverlap turns on earlier than C overlap . The right axis in Figure 2b shows the drain-source current (I ds ) as a function of gate-source bias (V gs ) of LTFET. It is shown that in the subthreshold part of the I ds -V gs characteristics, only the C nonoverlap is active. C overlap turns on at V gs = 0.15 V. When C overlap turns on, its G tun is significantly higher because of 1D BTBT paths. As a result, it dominates the 2D G tun in C nonoverlap , as can be seen in Figure 2b. Based on this analysis, I ds -V gs characteristics of LTFET were modeled in two parts, first the 2D model in C nonoverlap for the subthreshold region and then the 1D model in C overlap .
Appl. Sci. 2019, 9, x FOR PEER REVIEW 3 of 11 in Coverlap (black triangles) and in Cnonoverlap (red circles) in the left axis. Figure 2b clearly shows that Cnonoverlap turns on earlier than Coverlap. The right axis in Figure 2b shows the drain-source current (Ids) as a function of gate-source bias (Vgs) of LTFET. It is shown that in the subthreshold part of the Ids-Vgs characteristics, only the Cnonoverlap is active. Coverlap turns on at Vgs = 0.15 V. When Coverlap turns on, its Gtun is significantly higher because of 1D BTBT paths. As a result, it dominates the 2D Gtun in Cnonoverlap, as can be seen in Figure 2b. Based on this analysis, Ids-Vgs characteristics of LTFET were modeled in two parts, first the 2D model in Cnonoverlap for the subthreshold region and then the 1D model in Coverlap.

2D Model: Cnonoverlap Model
The 2D model is based on the work in [3]. The following assumptions are used in this model: (1) Electric fields are assumed to be completely circular and terminate from gate to source. This helps in obtaining a convenient expression for the tunneling length (Wt); (2) Gate dielectric is treated as the same material as the channel with an equivalent dielectric thickness t'ox given by t'ox = toxεsi/εox, where tox, εsi, and εox are the physical dielectric thickness, silicon dielectric permittivity, and oxide dielectric permittivity, respectively. This is necessary to ensure a continuous and perfectly circular electric field from the gate-to-channel/gate dielectric interface, and finally terminate at the source. Without this assumption, the electric field will be discontinuous, that is, not perfectly circular in its path from gate to source. In this work, Wt is conveniently calculated as the length along the perfectly circular electric field arc, from gate to source, as will be shown below. If a discontinuity arises in the circularity of the electric field arc, such convenient calculation of Wt will not be possible; (3) The source is assumed to be completely depleted, and depletion length is ignored. The source is heavily doped. Depletion length is inversely proportional to doping concentration [3]. This makes the source depletion length negligible. Including the source depletion length would add complexity to the model without significantly increasing the accuracy of the model; (4) The source is assumed to be touching the gate. Table 1 mentions most of the symbols used in the equations below.
With these assumptions, the boundary conditions at source and gate can be given by , 0 = and 0, = .
where φsource is assumed to be 0 V and φg is the gate-source bias minus the flat band voltage (Vfb), that is, φg = Vgs − Vfb. The solution of potential in polar co-ordinates is given by (2) Figure 2. (a) G tun along the surface of C overlap and C nonoverlap (left axis), and ϕ s along the channel (right axis) at V gs = 0.15 V and V ds = 0.5 V. (b) Integrated band-to-band tunneling (BTBT) tunneling rates in C overlap (black triangles) and C nonoverlap (red circles) as a function of V gs (left axis), and I ds -V gs characteristics of LTFET (right-axis). BTBT threshold voltages for C overlap and C nonoverlap are indicated by arrows.

2D Model: C nonoverlap Model
The 2D model is based on the work in [3]. The following assumptions are used in this model: (1) Electric fields are assumed to be completely circular and terminate from gate to source. This helps in obtaining a convenient expression for the tunneling length (W t ); (2) Gate dielectric is treated as the same material as the channel with an equivalent dielectric thickness t' ox given by t' ox = t ox ε si /ε ox , where t ox , ε si , and ε ox are the physical dielectric thickness, silicon dielectric permittivity, and oxide dielectric permittivity, respectively. This is necessary to ensure a continuous and perfectly circular electric field from the gate-to-channel/gate dielectric interface, and finally terminate at the source. Without this assumption, the electric field will be discontinuous, that is, not perfectly circular in its path from gate to source. In this work, W t is conveniently calculated as the length along the perfectly circular electric field arc, from gate to source, as will be shown below. If a discontinuity arises in the circularity of the electric field arc, such convenient calculation of W t will not be possible; (3) The source is assumed to be completely depleted, and depletion length is ignored. The source is heavily doped. Depletion length is inversely proportional to doping concentration [3]. This makes the source depletion length negligible. Including the source depletion length would add complexity to the model without significantly increasing the accuracy of the model; (4) The source is assumed to be touching the gate. Table 1 mentions most of the symbols used in the equations below.
With these assumptions, the boundary conditions at source and gate can be given by ϕ(x, 0) = ϕ source and ϕ(0, y) = ϕ g .
(1) where ϕ source is assumed to be 0 V and ϕ g is the gate-source bias minus the flat band voltage (V fb ), that is, ϕ g = V gs − V fb . The solution of potential in polar co-ordinates is given by (2) The above boundary condition along with θ 0 is shown in Figure 3a. Thanks to assumptions 1 and 2, W t is calculated as the length along a perfectly circular electric field line as follows: where θ 0 is given by θ 0 = πE g /(2qϕ g ), (where E g is the bandgap, and q is the charge on an electron) and is the angle when the potential difference between the source edge and some point along the electric field line becomes equal to E g /q. θ 0 is obtained by substituting the BTBT condition, that is, (2), and inverting it. Since θ 0 is bias-dependent, θ 0 decreases, and W t decreases as V gs bias increases. This is illustrated in Figure 3b. r 0 is the radius of the electric field arc and is given by r 0 = t' ox /cos (θ 0 ). Drain current expression in C nonoverlap (I ds_Cnonoverlap ) is given by the following equation for D = 2.5 [3]: where W (=10 −4 cm) is the device width, and A k = 1 × 10 15 eV 0.5 ·cm −1/2 ·s −1 ·V −2.5 and B k = 1.5 × 10 7 V·cm −1 ·eV −1.5 are the parameters used in the dynamic nonlocal BTBT model. There is one notable difference between this work and [3] which is that, as C overlap turns on, I ds_Cnonoverlap is assumed to saturate. This is in line with the results presented in Figure 2b. Once C overlap turns on, it dominates, and C nonoverlap does not have any significant contribution beyond that point. Without this assumption, the model overestimates I ds_Cnonoverlap in the high V gs region.
Appl. Sci. 2019, 9, x FOR PEER REVIEW 4 of 11 The above boundary condition along with θ0 is shown in Figure 3a. Thanks to assumptions 1 and 2, Wt is calculated as the length along a perfectly circular electric field line as follows: where θ0 is given by θ0 = πEg/(2qφg), (where Eg is the bandgap, and q is the charge on an electron) and is the angle when the potential difference between the source edge and some point along the electric field line becomes equal to Eg/q. θ0 is obtained by substituting the BTBT condition, that is, φ = Eg/q in (2), and inverting it. Since θ0 is bias-dependent, θ0 decreases, and Wt decreases as Vgs bias increases. This is illustrated in Figure 3b. r0 is the radius of the electric field arc and is given by r0 = t ' ox/cos (θ0). Drain current expression in Cnonoverlap (Ids_Cnonoverlap) is given by the following equation for D = 2.5 [3]: where W (=10 −4 cm) is the device width, and Ak = 1 × 10 15 eV 0.5 ·cm −1/2 ·s −1 ·V −2.5 and Bk = 1.5 × 10 7 V·cm −1 ·eV −1.5 are the parameters used in the dynamic nonlocal BTBT model. There is one notable difference between this work and [3] which is that, as Coverlap turns on, Ids_Cnonoverlap is assumed to saturate. This is in line with the results presented in Figure 2b. Once Coverlap turns on, it dominates, and Cnonoverlap does not have any significant contribution beyond that point. Without this assumption, the model overestimates Ids_Cnonoverlap in the high Vgs region.
(a) (b)      Figure 4a shows a magnified C overlap and source regions. The channel region considered in the 1D model comprises the C overlap region. Figure 4a mentions the important parameters used in the 1D model, including the location of ϕ s and junction potential (ϕ j ). ϕ j is the potential at the junction of the source and channel region in Figure 4a. The device origin is at the top of the channel/gate dielectric interface, and x channel and x source correspond to the x-coordinate in channel and source regions, respectively. The dimension for the 1D model is along the x-direction, as shown by the cutline shown in Figure 4b. The cutline begins at the channel/gate dielectric interface and ends in the source region. Figures 5d-f and 6a,b are along the black cutline shown in Figure 4b. shown in Figure 4b. The cutline begins at the channel/gate dielectric interface and ends in the source region. Figures 5d-f and 6a,b are along the black cutline shown in Figure 4b.
where Ldep is the depletion length of the source region. Integrating (5) and (6)  With the potential profile known, Wt can be calculated. Because (9) is derived from the depletion approximation, the smoothing function from [11][12][13] was used to model strong inversion of the electron. There are two different 1D BTBT mechanisms present in LTFET [8]. One is the source-to-channel BTBT, which starts at low bias, and the other is the channel-to-channel BTBT, which takes place at high Vgs bias. The first source to channel the 1D BTBT model is discussed.  The potential profile within the channel is assumed to be linear, as seen in Figure 5d-f, which is given by where m is the slope of the linear potential profile in the channel, m = (φs − φj)/Tj. φj can be found from (8) by using xchannel = Tj. Figure 5a-c shows φs as a function of Vgs of LTFET with Tj = 4, 5, and 6 nm at different Vds biases, respectively. Figure 5d-f shows the potential profile along the cutline shown in Figure 4b for LTFET with Tj = 4, 5, and 6 nm at different Vgs and Vds = 0.25 V, respectively. Symbols and lines denote the simulation results of TCAD and the proposed potential model, respectively. Reasonable agreement is observed within a maximum error of 10% between the model and TCAD simulations. Figure 6a shows a band diagram at Vgs = 0.3 V and Vds = 0.5 V, along the cutline of Figure 4b. Black and green symbols represent conduction band minimum energy (Ec) and valence band x s_longest x e_shortest

Results
Figure 7a-c shows Ids-Vgs characteristics of LTFET with Tj = 4, 5, and 6 nm, respectively. Symbols and lines denote the simulation results of TCAD and the proposed model, respectively. Blue, red, and black colors denote Vds = 0.25, 0.5, and 0.7 V, respectively. A kink is observed in Figure 7a-c, at the transition point where the 1D model takes over the 2D model. This is observed because the 1D and 2D models are independent of each other and don't produce the same and continuous Gtun at the transition point.
There is no noticeable change observed in the subthreshold behavior as Tj is changed from 4 nm to 6 nm. However, the on-current (ION) is observed to decrease as Tj is increased. ION at Vgs = 0.8 V and Vds = 0.7 V is 0.48, 0.22, and 0.09 µA for Tj = 4, 5, and 6 nm, respectively. This is because Wt and Gtun are inversely proportional, as can be observed from (13); the longer Wt in Tj = 5 and 6 nm results in lower Gtun, and consequently, lower Ids. This effect is captured by the model reasonably well. This suggests that shorter Tj is more desirable for getting higher ION. Figure 7d-f shows Ids-Vds characteristics of the LTFET for Tj = 4, 5, and 6 nm, respectively. Symbols denote TCAD simulation results, and lines denote model results. Black, red, blue, and Appl. Sci. 2019, 9, 3716 7 of 12 where L dep is the depletion length of the source region. Integrating (5) and (6) again yields potential in source and channel regions, which is given by where C ox is the gate oxide capacitance, ϕ dep is the source depletion potential, and γ = (2ε si qN a ) 1/2 /C ox . With the potential profile known, W t can be calculated. Because (9) is derived from the depletion approximation, the smoothing function from [11][12][13] was used to model strong inversion of the electron. There are two different 1D BTBT mechanisms present in LTFET [8]. One is the source-to-channel BTBT, which starts at low bias, and the other is the channel-to-channel BTBT, which takes place at high V gs bias. The first source to channel the 1D BTBT model is discussed.
The potential profile within the channel is assumed to be linear, as seen in Figure 5d-f, which is given by ϕ channel (x channel ) = mx channel + ϕ s (10) where m is the slope of the linear potential profile in the channel, m = (ϕ s − ϕ j )/T j . ϕ j can be found from (8) by using x channel = T j . Figure 5a-c shows ϕ s as a function of V gs of LTFET with T j = 4, 5, and 6 nm at different V ds biases, respectively. Figure 5d-f shows the potential profile along the cutline shown in Figure 4b for LTFET with T j = 4, 5, and 6 nm at different V gs and V ds = 0.25 V, respectively. Symbols and lines denote the simulation results of TCAD and the proposed potential model, respectively. Reasonable agreement is observed within a maximum error of 10% between the model and TCAD simulations. Figure 6a shows a band diagram at V gs = 0.3 V and V ds = 0.5 V, along the cutline of Figure 4b. Black and green symbols represent conduction band minimum energy (E c ) and valence band maximum energy (E v ), respectively. Red circles represent potential. Arrows denote W t s. The longest W t (W t_longest ) originates where ϕ source = ϕ dep , and the shortest W t (W t_shortest ) originates from where the potential is the highest, that is, ϕ s . The starting and ending points for W t_shortest are x s_shortest and x e_shortest , respectively, and the starting and ending points for W t_longest are x s_longest and x e_longest , respectively, which are all indicated by arrows in Figure 6a. x s_longest naturally starts from L dep , that is, x s_longest = −abs(L dep + T j ), and the ending point for the W t_shortest is the surface, that is, x e_shortest = 0. x e_longest is the point where the BTBT condition for W t_longest , that is, ϕ(x e_longest ) = ϕ dep + E g /q, is satisfied. By substituting this BTBT condition in (10) and inverting it, x e_longest is given by x e_longest = (ϕ dep + E g /q − ϕ s )T j /(ϕ s − ϕ j ). x s_shortest is the point where the BTBT condition for W t_shortest , that is, ϕ(x s_shortest ) = ϕ s − E g /q, is satisfied. By substituting this BTBT condition in (7) and inverting it, x s_shortest is given by Finally, W t_shortest and W t_longest are given by G tun is given by Kane's model [14] I ds for source-to-channel BTBT (I ds_s_c ) is given by where x j is the integration limit indicated in Figure 6a, and is equal to x j = x e_shortest − x e_longest . In (14), a constant average G tun , that is, , is used. Here, G tun_shortest and G tun_longest are found by using W t = W t_shortest and W t_longest in (13), respectively. G tun is a function of W t , as can be inferred from (13). The integral in (14), however, is with respect to x. Finding a closed-form expression for I ds_s_c then necessitates expressing W t as a function of x. However, because W t cannot be expressed as a function of x, W t can only be found for fixed BTBT boundary conditions, as done in (12a, b). In this scenario, dW t /dx cannot be evaluated. As a result, there is no closed-form expression available for G tun integrated as a function of x. Therefore, the simplification of using average G tun was necessary and, as it will be shown in Section 3, the average G tun approximates the integral of G tun with respect to x reasonably well. When the bias is high enough, the potential increases so much that BTBT becomes possible from even inside the channel. This is illustrated by the band diagram shown in Figure 6b along the cutline of Figure 4b. Here, E v /E c becomes aligned within the channel, as illustrated by the arrows, in addition to the source/channel E v /E c alignment. Here, W t_longest starts from x s_longest = T j and ends at x e_longest , where the BTBT condition, ϕ(x e_longest ) = ϕ j + E g /q, is satisfied. Similarly, W t_shortest starts at x s_shortest , where the BTBT condition, ϕ(x s_shortest ) = ϕ s − E g /q, is satisfied and ends at x e_shortest = 0. By substituting these boundary conditions in (10) and inverting it, x e_longest and x s_shortest can be calculated as x e_longest = (ϕ j + E g /q − ϕ s )T j /(ϕ s − ϕ j ) and x s_shortest = −E g T j /(q(ϕ s − ϕ j )). As can be seen in Figure 6b, W t is almost constant within the channel. Therefore, in the channel-to-channel regime, G tun_shortest ≈ G tun (W t_longest ) ≈ G tun (W t_shortest ). This means that G tun (x) can be taken out of the integral in the channel-to-channel drain current (I ds_c_c ) expression, which is given by The total I ds is given by

Results
Figure 7a-c shows I ds -V gs characteristics of LTFET with T j = 4, 5, and 6 nm, respectively. Symbols and lines denote the simulation results of TCAD and the proposed model, respectively. Blue, red, and black colors denote V ds = 0.25, 0.5, and 0.7 V, respectively. A kink is observed in Figure 7a-c, at the transition point where the 1D model takes over the 2D model. This is observed because the 1D and 2D models are independent of each other and don't produce the same and continuous G tun at the transition point.
that shorter Tj is more desirable for getting higher ION.
Figure 7d-f shows Ids-Vds characteristics of the LTFET for Tj = 4, 5, and 6 nm, respectively. Symbols denote TCAD simulation results, and lines denote model results. Black, red, blue, and magenta denote Vgs = 0.2, 0.4, 0.6, and 0.8 V, respectively. As shown in Figure 7d-f, the saturation characteristics of the LTFET are predicted reasonably well by the model.    Figure 8 shows Ids-Vgs characteristics of LTFET with Tj = 4 nm and Hoverlap = Hs varied at Vds = 0.5 V. Symbols denote TCAD simulation results and lines denote model results. Blue, red, and black represent Hoverlap = 40, 50, and 60 nm, respectively. It is shown in Figure 8 that, as Hoverlap = Hs is increased, the Ids increases. This is because, with an increase in Hoverlap, the BTBT area increases. This results in an increase in Ids. Once again, the model captures this effect reasonably well.   There is no noticeable change observed in the subthreshold behavior as T j is changed from 4 nm to 6 nm. However, the on-current (I ON ) is observed to decrease as T j is increased. I ON at V gs = 0.8 V and V ds = 0.7 V is 0.48, 0.22, and 0.09 µA for T j = 4, 5, and 6 nm, respectively. This is because W t and G tun are inversely proportional, as can be observed from (13); the longer W t in T j = 5 and 6 nm results in lower G tun , and consequently, lower I ds . This effect is captured by the model reasonably well. This suggests that shorter T j is more desirable for getting higher I ON .
Figure 7d-f shows I ds -V ds characteristics of the LTFET for T j = 4, 5, and 6 nm, respectively. Symbols denote TCAD simulation results, and lines denote model results. Black, red, blue, and magenta denote V gs = 0.2, 0.4, 0.6, and 0.8 V, respectively. As shown in Figure 7d-f, the saturation characteristics of the LTFET are predicted reasonably well by the model. Figure 8 shows I ds -V gs characteristics of LTFET with T j = 4 nm and H overlap = H s varied at V ds = 0.5 V. Symbols denote TCAD simulation results and lines denote model results. Blue, red, and black represent H overlap = 40, 50, and 60 nm, respectively. It is shown in Figure 8 that, as H overlap = H s is increased, the I ds increases. This is because, with an increase in H overlap , the BTBT area increases. This results in an increase in I ds . Once again, the model captures this effect reasonably well. Figure 7. (a-c) Ids-Vgs characteristics of LTFET with Tj = 4, 5, and 6 nm, respectively, at Vds = 0.25 (blue), 0.5 (red), and 0.7 V (black). (d-f) Ids-Vds characteristics of LTFET with Tj = 4, 5, and 6 nm, respectively, at Vgs = 0.2 (black), 0.4 (red), 0.6 (blue), and 0.8 V (magenta). Error bar: 10%. Lines: Model. Symbols: TCAD. Figure 8 shows Ids-Vgs characteristics of LTFET with Tj = 4 nm and Hoverlap = Hs varied at Vds = 0.5 V. Symbols denote TCAD simulation results and lines denote model results. Blue, red, and black represent Hoverlap = 40, 50, and 60 nm, respectively. It is shown in Figure 8 that, as Hoverlap = Hs is increased, the Ids increases. This is because, with an increase in Hoverlap, the BTBT area increases. This results in an increase in Ids. Once again, the model captures this effect reasonably well.  Compared to the planar TFET, the LTFET offers better SS and I ON performance. This can be gauged from the fact that while in planar TFET, the dominant BTBT generation area comprises the surface source/channel depletion regions. In the LTFET, however, because of the gate-source overlap, this area is significantly amplified by the height of the source and C overlap regions. Furthermore, because of this overlap, the electrostatic coupling between gate and source is stronger in LTFET. In other words, the electric field is stronger in the LTFET as compared to the planar TFET, which also results in higher I ON and lower inverse subthreshold slope in LTFET, as was demonstrated even in the case of the experimental LTFET and planar TFET in [4]. For a compact model, the simulation results of the model agree reasonably well with those of TCAD within a maximum error of 10%. However, it is not entirely accurate. The inaccuracy results from the simplified integral expression in (14). Numerical integration of G tun with respect to x will significantly improve the result. Another source of error is the use of the smoothing function to model electron inversion. The smoothing function only approximates surface potential saturation due to electron inversion, and is thus not very accurate at high bias. Considering the electron concentration term in the Poisson equation and doing a self-consistent solution for potential and electron concentration will also improve the model accuracy significantly. However, both numerical integration and self-consistent potential electron concentration solution will significantly add to the computational complexity of the model. This will make the model unsuitable for SPICE applications.
It should also be mentioned that the model was bench-marked only against TCAD data and not experimental data. This is because the experimental LTFET demonstrated significant trap-assisted tunneling (TAT), and Shockley-Read-Hall (SRH) generation-recombination current-and ambipolar current-induced degradation of the I ds -V gs characteristics [4]. In particular, TAT in line TFETs is a significant topic and requires its own modeling framework [9]. This work with the equations for surface and junction potentials lays the foundation for the TAT model. However, due to space constraints, TAT, SRH, ambipolar, quantum confinement [15], and breakdown models [16] could not be included in this manuscript.

Conclusions
A compact model for LTFET was presented. The model calculates both the 1D BTBT and 2D BTBT present in LTFET. The 1D model is based on the simultaneous solution of 1D Poisson equations in the channel and source region. The Poisson equation is integrated twice in both regions, and the expression for electric field and potential are equated at the source-channel junction point to yield expression for surface potential. To model electron inversion, a simple smoothing function was used. After obtaining the potential profile, starting and ending points of tunneling paths were determined using BTBT boundary conditions. The shortest tunneling path was considered in the drain current expression for source-to-channel BTBT. This was done to obtain a simplified expression for the source-to-channel drain current. Tunneling path lengths were similarly determined for the channel-to-channel BTBT regime. The model was compared against I ds -V gs /V ds results obtained from the simulator for different V ds /V gs biases, and for different channel region thicknesses, and heights. The results of the compact model are in reasonable agreement with the simulator results.