Mini-Review: Modeling and Performance Analysis of Nanocarbon Interconnects

Wen-Sheng Zhao 1 , Kai Fu 1, Da-Wei Wang 2, Meng Li 3, Gaofeng Wang 1,* and Wen-Yan Yin 2,* 1 Key Lab of RF Circuits and Systems of Ministry of Education, School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China; wsh.zhao@gmail.com (W.-S.Z.); kain.foh@gmail.com (K.F.) 2 Key Lab of Advanced Micro-Nano Electronic Devices and Smart Systems of Zhejiang Province, College of Information Science and Electronic Engineering, Innovative Institute of Electromagnetic Information and Electronic Integration, Zhejiang University, Hangzhou 310058, China; davidwangwf@zju.edu.cn 3 Beijing Aerospace Technology Institute, Beijing 100074, China; limeng_smile@163.com * Correspondence: gaofeng@hdu.edu.cn (G.W.); wyyin@zju.edu.cn (W.-Y.Y.)


Introduction
The breakthrough development of the semiconductor industry has revolutionized human society, from personal electronic gadgets, commercial and industrial equipment to military and aeronautical facilities. As predicted by Moore's law, the number of transistors within a chip doubles about every two years, while the cost comes down [1]. According to the International Technology Roadmap for Semiconductors (ITRS) projection, a 10 nm minimum feature size could support a tera-scale chip with a trillion transistors by 2020 [2]. Such phenomenal progress has been achieved through scaling of digital integrated circuit (IC) feature size to smaller physical dimensions.
The ongoing miniaturization of the IC feature size has had a significant benefit in increasing the transistor speed. However, different from the transistor, the interconnect performance would be degraded due to the reduced conduction area and increased scattering probability for electrons [3,4]. Under such circumstances, the chip performance is restricted by the shrinking interconnect dimensions on account of both the interconnect delay and the power dissipation. Moreover, the interconnect reliability has been becoming a more and more important problem, as the ampacity of conventional Cu wire cannot satisfy the increasingly stringent requirements [2, 5,6]. Therefore, interconnects have become the major challenge in the design of modern ICs, thereby leading to the transition of IC technology from transistor-centric to interconnect-centric [7]. To address the interconnect challenges for next-generation ICs, diverse improvements of interconnect optimization and design methods have been reported, such as a low-k dielectric structure, three-dimensional integration, and inter-chip optical interconnects [8][9][10].

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Nanocarbon materials have attracted much attention since the carbon nanotube (CNT) was discovered by an arc-discharge evaporation method in 1991 [11]. Graphene, a Nobel Prize honored discovery, has further promoted the research in this field [12]. It was found that nanocarbon materials have many extraordinary physical properties. For example, the ultrahigh thermal conductivity of nanocarbon materials can help heat dissipation in high-density integrated systems [13][14][15]. The maximum current-carrying density of a CNT is more than two orders higher than that of Cu wires, thereby mitigating the electromigration-induced reliability problems [16]. It is natural to apply nanocarbon materials as an alternative option to potentially replace Cu for interconnects and passive devices in ICs [17][18][19][20][21][22]. In recent years, there have been many publications in the literature devoted to the design, modeling/analysis, and fabrication/integration of nanocarbon interconnects. This paper seeks to review recent research efforts and progress in the nanocarbon interconnects. In particular, this paper focuses on the modeling and direct current (DC) performance analysis of nanocarbon interconnects for next-generation digital ICs.

Graphene Nanoribbon (GNR) Interconnects
Physically, graphene is a 2D monolayer of carbon atoms packed into a honeycomb lattice, and the quasi-1D graphene nanoribbon (GNR), as shown in Figure 1a, can be utilized as on-chip interconnects [23]. Depending on the edge shape, a GNR can be zigzag, armchair, or chiral (other shapes). The zigzag GNR is always metallic, whereas the armchair GNR is metallic or semiconducting, depending on the number of carbon atoms across its width. Different from the GNR, a CNT's chirality is defined by its circumferential edge shape. A single-walled carbon nanotube (SWCNT) can be visualized as a seamlessly rolled-up GNR, on the basis of which a novel fabrication method has been developed to unzip the CNT to form a GNR [24]. A multi-walled carbon nanotube (MWCNT) is a parallel assembly of coaxial SWCNTs, and the neighboring shells in an MWCNT are separated by the van der Waals gap.
Appl. Sci. 2019, 9,2174 2 of 20 and design methods have been reported, such as a low-k dielectric structure, three-dimensional integration, and inter-chip optical interconnects [8][9][10]. Nanocarbon materials have attracted much attention since the carbon nanotube (CNT) was discovered by an arc-discharge evaporation method in 1991 [11]. Graphene, a Nobel Prize honored discovery, has further promoted the research in this field [12]. It was found that nanocarbon materials have many extraordinary physical properties. For example, the ultrahigh thermal conductivity of nanocarbon materials can help heat dissipation in high-density integrated systems [13][14][15]. The maximum current-carrying density of a CNT is more than two orders higher than that of Cu wires, thereby mitigating the electromigration-induced reliability problems [16]. It is natural to apply nanocarbon materials as an alternative option to potentially replace Cu for interconnects and passive devices in ICs [17][18][19][20][21][22]. In recent years, there have been many publications in the literature devoted to the design, modeling/analysis, and fabrication/integration of nanocarbon interconnects. This paper seeks to review recent research efforts and progress in the nanocarbon interconnects. In particular, this paper focuses on the modeling and direct current (DC) performance analysis of nanocarbon interconnects for next-generation digital ICs.

Graphene Nanoribbon (GNR) Interconnects
Physically, graphene is a 2D monolayer of carbon atoms packed into a honeycomb lattice, and the quasi-1D graphene nanoribbon (GNR), as shown in Figure 1a, can be utilized as on-chip interconnects [23]. Depending on the edge shape, a GNR can be zigzag, armchair, or chiral (other shapes). The zigzag GNR is always metallic, whereas the armchair GNR is metallic or semiconducting, depending on the number of carbon atoms across its width. Different from the GNR, a CNT's chirality is defined by its circumferential edge shape. A single-walled carbon nanotube (SWCNT) can be visualized as a seamlessly rolled-up GNR, on the basis of which a novel fabrication method has been developed to unzip the CNT to form a GNR [24]. A multi-walled carbon nanotube (MWCNT) is a parallel assembly of coaxial SWCNTs, and the neighboring shells in an MWCNT are separated by the van der Waals gap.

Multilayer Graphene Nanoribbon (MLGNR) Interconnects
In comparison to the CNT, the GNR can be easily controlled horizontally and is more compatible with conventional lithography [24]. By using the tight-binding approximation, the conductance of a monolayer GNR has been calculated as a function of width , Fermi level , and specularity parameter for edge diffuse scattering in Reference [25]. It was demonstrated that the atomically thick monolayer GNR could outperform Cu wire for widths below 8 nm. Figure 2a shows the

Multilayer Graphene Nanoribbon (MLGNR) Interconnects
In comparison to the CNT, the GNR can be easily controlled horizontally and is more compatible with conventional lithography [24]. By using the tight-binding approximation, the conductance of a monolayer GNR has been calculated as a function of width W, Fermi level E F , and specularity parameter p for edge diffuse scattering in Reference [25]. It was demonstrated that the atomically thick monolayer GNR could outperform Cu wire for widths below 8 nm. Figure 2a shows the schematic Appl. Sci. 2019, 9, 2174 3 of 21 diagram of a monolayer GNR interconnect with its equivalent circuit model. In the model, R c is the contact resistance, and it can be calculated by: where R mc is the imperfect contact resistance, and it highly depends on the fabrication technology. R Q is the quantum contact resistance, and it is calculated as R Q = h/ 2e 2 N ch , where h is the Planck's constant and e is the electron charge. The number of conducting channels in a monolayer GNR can be calculated by [26,27]: where k B is the Boltzmann's constant and T is the temperature. For a given width of the metallic armchair GNR with W > 10 nm and E F > 0.1 eV, N ch can be approximated as 1.2WE F , where W and E F are in units of nanometers and electron volts, respectively [28]. The total resistance of a monolayer GNR is given by: where L is the interconnect length, and λ eff,i is the effective MFP (mean free path) for the ith subband. The MFP is determined by various scattering mechanisms, and it is a function of the specularity parameter p [29]. Herein, the fully diffusive GNR can be represented by p = 0, meanwhile, p = 1 represents that the GNR is fully specular.
Appl. Sci. 2019, 9, 2174 3 of 20 schematic diagram of a monolayer GNR interconnect with its equivalent circuit model. In the model, is the contact resistance, and it can be calculated by: where is the imperfect contact resistance, and it highly depends on the fabrication technology. is the quantum contact resistance, and it is calculated as = ℎ 2 ⁄ , where ℎ is the Planck's constant and is the electron charge. The number of conducting channels in a monolayer GNR can be calculated by [26,27]: where is the Boltzmann's constant and is the temperature. For a given width of the metallic armchair GNR with > 10 nm and > 0.1 eV, can be approximated as 1.2 , where and are in units of nanometers and electron volts, respectively [28]. The total resistance of a monolayer GNR is given by: where is the interconnect length, and , is the effective MFP (mean free path) for the th subband. The MFP is determined by various scattering mechanisms, and it is a function of the specularity parameter [29]. Herein, the fully diffusive GNR can be represented by = 0 , meanwhile, = 1 represents that the GNR is fully specular. However, it is worth noting that the physical properties of monolayer GNR is susceptible to the substrate influence, which can be avoided for the case of multilayer GNR (MLGNR). Moreover, MLGNR has superior characteristics for signal propagation as the multilayer structure can effectively reduce the interconnect resistance [29][30][31][32]. Figures 2b,c show the schematic diagrams of MLGNR interconnects with top contacts and side contacts, respectively. In the figure, denotes the van der Waal's gap between the adjacent graphene layers, is the thickness of the MLGNR interconnect, and the number of graphene layers = 1 + Inter ⁄ , where "Inter ⋅ " represents that only the integer part is considered.
To date, most of the experiments on multilayer graphene have employed top contacts, as shown in Figure 2b [33][34][35]. For the top-contacted MLGNR interconnect, Kumar, et al. [36] developed a resistor circuit model with the consideration of in-plane resistance and perpendicular resistance between adjacent layers . It was found that the perpendicular resistance makes the conductance a nonlinear function of the number of graphene layers. Further, Pan, et al. [37] conducted a benchmark study, which indicated such top-contacted MLGNR can exhibit advantages under certain circumstances. With the increasing interconnect length, however, the in-plane resistance increases, while the perpendicular resistance decreases continually. It can be seen in Figure 3, that as However, it is worth noting that the physical properties of monolayer GNR is susceptible to the substrate influence, which can be avoided for the case of multilayer GNR (MLGNR). Moreover, MLGNR has superior characteristics for signal propagation as the multilayer structure can effectively reduce the interconnect resistance [29][30][31][32]. Figure 2b,c show the schematic diagrams of MLGNR interconnects with top contacts and side contacts, respectively. In the figure, δ denotes the van der Waal's gap between the adjacent graphene layers, H is the thickness of the MLGNR interconnect, and the number of graphene layers N = 1 + Inter(H/δ), where "Inter(·)" represents that only the integer part is considered.
To date, most of the experiments on multilayer graphene have employed top contacts, as shown in Figure 2b [33][34][35]. For the top-contacted MLGNR interconnect, Kumar, et al. [36] developed a resistor circuit model with the consideration of in-plane resistance R layer and perpendicular resistance between adjacent layers R perp . It was found that the perpendicular resistance makes the conductance a nonlinear function of the number of graphene layers. Further, Pan, et al. [37] conducted a benchmark study, which indicated such top-contacted MLGNR can exhibit advantages under certain circumstances. With the increasing interconnect length, however, the in-plane resistance increases, while the perpendicular resistance decreases continually. It can be seen in Figure 3, that as the length exceeds a certain value, the influences of the contact type and interlayer coupling can be ignored, and the top-contacted MLGNR can be treated as a side-contacted one [28].
Appl. Sci. 2019, 9,2174 4 of 20 the length exceeds a certain value, the influences of the contact type and interlayer coupling can be ignored, and the top-contacted MLGNR can be treated as a side-contacted one [28].  Figure 4 shows the multi-conductor transmission line model and the simplified equivalent single-conductor (ESC) transmission line model of a side-contacted MLGNR interconnect. In the multi-conductor model, the mutual capacitance and inductance between the adjacent graphene layers have been considered. The MLGNR interconnects are assumed to be decoupled, because several decoupled graphene layers have been grown experimentally in References [33,34], and demonstrated theoretically in Reference [39]. In this case, the resistance of the MLGNR interconnect is a parallel connection of the resistance of each layer, i.e., = ∑ , . The per-unit-length (p.u.l.) magnetic inductance and electrostatic capacitance are determined by the MLGNR geometry and its surrounding dielectrics. By applying the boundary conditions, the equivalent kinetic inductance and quantum capacitance in the ESC model can be obtained by recursive schemes [40,41]. As the kinetic inductance is much larger than the magnetic inductance, the equivalent kinetic inductance in the ESC model can be expressed as [28]: The equivalent quantum capacitance is mainly determined by the mutual coupling one between the adjacent layers. As the number of layers is larger than eight, the equivalent quantum capacitance can be given by: Based on the extracted parameters, the 50% propagation delay can be calculated by [42]: where is the driver resistance, is the load capacitance, = + , = 1 ⁄ + 1 ⁄ , and Due to large driver resistance, nanocarbon interconnects will not exhibit superior performance compared to conventional Cu wires at the local level. So our attention is focused on the intermediate level and global level MLGNR interconnects. Figure 5 shows the time delay ratios of MLGNR and Cu wires at the intermediate level and global level, respectively. The inverter size is assumed as 50  3 Ω · cm [28]. Figure 4 shows the multi-conductor transmission line model and the simplified equivalent single-conductor (ESC) transmission line model of a side-contacted MLGNR interconnect. In the multi-conductor model, the mutual capacitance and inductance between the adjacent graphene layers have been considered. The MLGNR interconnects are assumed to be decoupled, because several decoupled graphene layers have been grown experimentally in References [33,34], and demonstrated theoretically in Reference [39]. In this case, the resistance of the MLGNR interconnect is a parallel connection of the resistance of each layer, i.e., S . The per-unit-length (p.u.l.) magnetic inductance L M and electrostatic capacitance C E are determined by the MLGNR geometry and its surrounding dielectrics. By applying the boundary conditions, the equivalent kinetic inductance L K and quantum capacitance C Q in the ESC model can be obtained by recursive schemes [40,41]. As the kinetic inductance is much larger than the magnetic inductance, the equivalent kinetic inductance in the ESC model can be expressed as [28]: Appl. Sci. 2019, 9, 2174 5 of 20 and 100 times larger than the minimum-sized gate, respectively, at these levels. The imperfect contact resistance is neglected, and the Fermi level is set as 0.6 eV. As shown in Figure 5, the MLGNR interconnects with fully specular edges show superior performance over Cu wires at both the intermediate and global levels. Such an advantage can be enhanced with the feature size scaling down. However, when the specularity parameter decreases to 0.8, the electrical performance of the MLGNR interconnects will degrade to the comparable level of Cu wires. Therefore, it can be concluded that the MLGNR interconnects have the potential to outperform conventional Cu wires at an advanced technology node, and more attention should be paid to the edge quality.   The equivalent quantum capacitance is mainly determined by the mutual coupling one between the adjacent layers. As the number of layers is larger than eight, the equivalent quantum capacitance can be given by: Based on the extracted parameters, the 50% propagation delay can be calculated by [42]: where R d is the driver resistance, C L is the load capacitance, , and Due to large driver resistance, nanocarbon interconnects will not exhibit superior performance compared to conventional Cu wires at the local level. So our attention is focused on the intermediate level and global level MLGNR interconnects. Figure 5 shows the time delay ratios of MLGNR and Cu wires at the intermediate level and global level, respectively. The inverter size is assumed as 50 and 100 times larger than the minimum-sized gate, respectively, at these levels. The imperfect contact resistance is neglected, and the Fermi level is set as 0.6 eV. As shown in Figure 5, the MLGNR interconnects with fully specular edges show superior performance over Cu wires at both the intermediate and global levels. Such an advantage can be enhanced with the feature size scaling down. However, when the specularity parameter decreases to 0.8, the electrical performance of the MLGNR interconnects will degrade to the comparable level of Cu wires. Therefore, it can be concluded that the MLGNR interconnects have the potential to outperform conventional Cu wires at an advanced technology node, and more attention should be paid to the edge quality.
Appl. Sci. 2019, 9,2174 5 of 20 and 100 times larger than the minimum-sized gate, respectively, at these levels. The imperfect contact resistance is neglected, and the Fermi level is set as 0.6 eV. As shown in Figure 5, the MLGNR interconnects with fully specular edges show superior performance over Cu wires at both the intermediate and global levels. Such an advantage can be enhanced with the feature size scaling down. However, when the specularity parameter decreases to 0.8, the electrical performance of the MLGNR interconnects will degrade to the comparable level of Cu wires. Therefore, it can be concluded that the MLGNR interconnects have the potential to outperform conventional Cu wires at an advanced technology node, and more attention should be paid to the edge quality.

Vertical Graphene Nanoribbon (VGNR) Interconnects
Although the MLGNR interconnects show excellent electrical properties in terms of low resistance and high reliability, they may hinder the heat dissipation in vertical direction due to the anisotropic property [43]. To resolve this issue, the scheme of vertical graphene nanoribbon (VGNR) interconnect, as shown in Figure 6, was proposed and studied in [44]. Unlike the top-contacted MLGNR interconnect shown in Figure 2b, each layer in VGNR interconnect can participate in the electron transport, thereby reducing the contact resistance.

Vertical Graphene Nanoribbon (VGNR) Interconnects
Although the MLGNR interconnects show excellent electrical properties in terms of low resistance and high reliability, they may hinder the heat dissipation in vertical direction due to the anisotropic property [43]. To resolve this issue, the scheme of vertical graphene nanoribbon (VGNR) interconnect, as shown in Figure 6, was proposed and studied in [44]. Unlike the top-contacted MLGNR interconnect shown in Figure 2b, each layer in VGNR interconnect can participate in the electron transport, thereby reducing the contact resistance. As described in [45], the vertical graphene layers have been realized experimentally. Definitely, further improvement in the fabrication of long and highly aligned VGNRs is still required for their practical usage as on-chip interconnects [46]. A possible fabrication process is outlined briefly in the following. First, a catalyst layer is sputtered to grow graphene layers. Then, the vertical graphene layers grow below these layers, which are removed subsequently. VGNR interconnects are obtained finally by patterning the vertical graphene layers. As aforementioned, VGNRs can also be assumed to be decoupled [33,34,39], and the resistance is a parallel connection of the resistance of each layer. Figure 7a shows the p.u.l. resistance of a monolayer GNR interconnect with a 400 µm length and the 0.2 eV Fermi level. It is shown that the resistance of a monolayer GNR increases with the decreasing width. For GNRs with < 1, the resistance increases superlinearly with the decreasing width when the width becomes smaller than 10 nm. This superlinear relationship between GNR resistance and width becomes more significant as decreases. Note that for on-chip interconnect applications, the aspect ratio is always larger than 1 [2]. Therefore, it can be concluded that VGNR, which has a larger GNR width, possesses smaller resistivity than horizontal MLGNR. Figure 7b shows the time delay of Cu, horizontal MLGNR, and VGNR interconnects at the intermediate level.
It can be found that the decrease in specularity parameter can effectively improve the electrical performances of GNR interconnects. When = 1, the horizontal MLGNR and VGNR show similar performances. As is well known, however, the perfectly specular edges are difficult to fabricate [47]. Therefore, in practical applications, for < 1, the VGNR interconnect can provide smaller time delay than horizontal MLGNR interconnect. In other words, VGNR interconnect requires smaller specularity parameter than the horizontal MLGNR one, thereby reducing the process difficulty. As described earlier, the graphene is an anisotropic material, and its out-plane thermal conductivity is much lower than the in-plane one. Here, the in-plane and out-plane thermal conductivities of graphene are assumed as 1750 W/m·K and 10 W/m·K, respectively [48]. Under such circumstance, the horizontal MLGNR would hinder heat dissipation in vertical direction, thereby As described in [45], the vertical graphene layers have been realized experimentally. Definitely, further improvement in the fabrication of long and highly aligned VGNRs is still required for their practical usage as on-chip interconnects [46]. A possible fabrication process is outlined briefly in the following. First, a catalyst layer is sputtered to grow graphene layers. Then, the vertical graphene layers grow below these layers, which are removed subsequently. VGNR interconnects are obtained finally by patterning the vertical graphene layers. As aforementioned, VGNRs can also be assumed to be decoupled [33,34,39], and the resistance is a parallel connection of the resistance of each layer. Figure 7a shows the p.u.l. resistance of a monolayer GNR interconnect with a 400 µm length and the 0.2 eV Fermi level. It is shown that the resistance of a monolayer GNR increases with the decreasing width. For GNRs with p < 1, the resistance increases superlinearly with the decreasing width when the width becomes smaller than 10 nm. This superlinear relationship between GNR resistance and width becomes more significant as p decreases. Note that for on-chip interconnect applications, the aspect ratio is always larger than 1 [2]. Therefore, it can be concluded that VGNR, which has a larger GNR width, possesses smaller resistivity than horizontal MLGNR. Figure 7b shows the time delay of Cu, horizontal MLGNR, and VGNR interconnects at the intermediate level. It can be found that the decrease in specularity parameter can effectively improve the electrical performances of GNR interconnects. When p = 1, the horizontal MLGNR and VGNR show similar performances. As is well known, however, the perfectly specular edges are difficult to fabricate [47]. Therefore, in practical applications, for p < 1, the VGNR interconnect can provide smaller time delay than horizontal MLGNR interconnect. In other words, VGNR interconnect requires smaller specularity parameter than the horizontal MLGNR one, thereby reducing the process difficulty.
As described in [45], the vertical graphene layers have been realized experimentally. Definitely, further improvement in the fabrication of long and highly aligned VGNRs is still required for their practical usage as on-chip interconnects [46]. A possible fabrication process is outlined briefly in the following. First, a catalyst layer is sputtered to grow graphene layers. Then, the vertical graphene layers grow below these layers, which are removed subsequently. VGNR interconnects are obtained finally by patterning the vertical graphene layers. As aforementioned, VGNRs can also be assumed to be decoupled [33,34,39], and the resistance is a parallel connection of the resistance of each layer. Figure 7a shows the p.u.l. resistance of a monolayer GNR interconnect with a 400 µm length and the 0.2 eV Fermi level. It is shown that the resistance of a monolayer GNR increases with the decreasing width. For GNRs with < 1, the resistance increases superlinearly with the decreasing width when the width becomes smaller than 10 nm. This superlinear relationship between GNR resistance and width becomes more significant as decreases. Note that for on-chip interconnect applications, the aspect ratio is always larger than 1 [2]. Therefore, it can be concluded that VGNR, which has a larger GNR width, possesses smaller resistivity than horizontal MLGNR. Figure 7b shows the time delay of Cu, horizontal MLGNR, and VGNR interconnects at the intermediate level.
It can be found that the decrease in specularity parameter can effectively improve the electrical performances of GNR interconnects. When = 1, the horizontal MLGNR and VGNR show similar performances. As is well known, however, the perfectly specular edges are difficult to fabricate [47]. Therefore, in practical applications, for < 1, the VGNR interconnect can provide smaller time delay than horizontal MLGNR interconnect. In other words, VGNR interconnect requires smaller specularity parameter than the horizontal MLGNR one, thereby reducing the process difficulty. 21   As described earlier, the graphene is an anisotropic material, and its out-plane thermal conductivity is much lower than the in-plane one. Here, the in-plane and out-plane thermal conductivities of graphene are assumed as 1750 W/m·K and 10 W/m·K, respectively [48]. Under such circumstance, the horizontal MLGNR would hinder heat dissipation in vertical direction, thereby As described earlier, the graphene is an anisotropic material, and its out-plane thermal conductivity is much lower than the in-plane one. Here, the in-plane and out-plane thermal conductivities of graphene are assumed as 1750 W/m·K and 10 W/m·K, respectively [48]. Under such circumstance, the horizontal MLGNR would hinder heat dissipation in vertical direction, thereby threatening the IC performance and reliability. It has been found that VGNR interconnects are likely to solve this problem. Figure 8a depicts the unit cell for simulation performed in commercial software COMSOL Multiphysics, with the geometrical parameters adopted at the 7.5 nm technology node from ITRS projection [2]. In the simulation, an equivalent packaging layer is considered, and the bottom junction temperature and the top ambient temperature are assumed as 378 K and 318 K, respectively. By injecting power into the topmost global interconnect, the temperature rise as a function of input power can be depicted as shown in Figure 8b and the plots the temperature profiles could be obtained as shown in Figure 8c. It is evident that the heat dissipation problems, which is crucial for future nanoscale ICs development, can be effectively avoided by VGNR interconnects [49].
Appl. Sci. 2019, 9,2174 7 of 20 threatening the IC performance and reliability. It has been found that VGNR interconnects are likely to solve this problem. Figure 8a depicts the unit cell for simulation performed in commercial software COMSOL Multiphysics, with the geometrical parameters adopted at the 7.5 nm technology node from ITRS projection [2]. In the simulation, an equivalent packaging layer is considered, and the bottom junction temperature and the top ambient temperature are assumed as 378 K and 318 K, respectively. By injecting power into the topmost global interconnect, the temperature rise as a function of input power can be depicted as shown in Figure 8b and the plots the temperature profiles could be obtained as shown in Figure 8c. It is evident that the heat dissipation problems, which is crucial for future nanoscale ICs development, can be effectively avoided by VGNR interconnects [49].

CNT Interconnects
Similar with GNR, CNT possesses long MFP, high ampacity, and large thermal conductivity [14,16,[50][51][52]. Based on the Luttinger liquid theory, Burke firstly developed the transmission line model of a metallic SWCNT interconnect [53]. The equivalent circuit model of an isolated SWCNT interconnect is the same as the circuit model shown in Figure 2a, with the CNT diameter denoted as . The number of conducting channels of a metallic SWCNT is 2, and the MFP is usually 1000 . Although an SWCNT possesses many unit properties and some efforts have been devoted to reducing the SWCNT resistance by doping, an isolated SWCNT is still too resistive for interconnect applications in high-performance ICs [54,55]. It can only be used in some specific applications such as subthreshold circuits and sub-10 nm circuits [56][57][58]. To reduce the CNT resistance, three kinds of CNT interconnects, i.e., monolayer SWCNT, bundled SWCNT, and MWCNT interconnects, have been widely studied, as shown in Figure 9.

CNT Interconnects
Similar with GNR, CNT possesses long MFP, high ampacity, and large thermal conductivity [14,16,[50][51][52]. Based on the Luttinger liquid theory, Burke firstly developed the transmission line model of a metallic SWCNT interconnect [53]. The equivalent circuit model of an isolated SWCNT interconnect is the same as the circuit model shown in Figure 2a, with the CNT diameter denoted as D cnt . The number of conducting channels of a metallic SWCNT is 2, and the MFP is usually 1000D cnt . Although an SWCNT possesses many unit properties and some efforts have been devoted to reducing the SWCNT resistance by doping, an isolated SWCNT is still too resistive for interconnect applications in high-performance ICs [54,55]. It can only be used in some specific applications such as subthreshold circuits and sub-10 nm circuits [56][57][58]. To reduce the CNT resistance, three kinds of CNT interconnects, i.e., monolayer SWCNT, bundled SWCNT, and MWCNT interconnects, have been widely studied, as shown in Figure 9.
As discussed in [59], for short local interconnects, the interconnect resistances are not important, while their capacitances play a key role. So the electrical performance can be improved by using low aspect ratio interconnects such as monolayer metallic SWCNT. It can be seen in Figure 10a that monolayer SWCNT interconnect possesses smaller parasitic capacitance than Cu wire. Therefore, it can be expected that monolayer SWCNT interconnects can reduce power dissipation and crosstalk noise [60]. Figure 10b depicts the energy-delay product (EDP) ratio between Cu wire and monolayer SWCNT interconnect. Here, the imperfect contact resistance is neglected as it is highly dependent on the process. As the length exceeds 20 µm, the EDP ratio becomes larger than 1, indicating that the monolayer SWCNT interconnect can provide better performance than the Cu counterpart. Moreover, the advantage of monolayer SWCNT interconnect becomes more evident for smaller inverter size. cnt 1000 cnt . Although an SWCNT possesses many unit properties and some efforts have been devoted to reducing the SWCNT resistance by doping, an isolated SWCNT is still too resistive for interconnect applications in high-performance ICs [54,55]. It can only be used in some specific applications such as subthreshold circuits and sub-10 nm circuits [56][57][58]. To reduce the CNT resistance, three kinds of CNT interconnects, i.e., monolayer SWCNT, bundled SWCNT, and MWCNT interconnects, have been widely studied, as shown in Figure 9. As discussed in [59], for short local interconnects, the interconnect resistances are not important, while their capacitances play a key role. So the electrical performance can be improved by using low aspect ratio interconnects such as monolayer metallic SWCNT. It can be seen in Figure 10(a) that monolayer SWCNT interconnect possesses smaller parasitic capacitance than Cu wire. Therefore, it can be expected that monolayer SWCNT interconnects can reduce power dissipation and crosstalk noise [60]. Figure 10(b) depicts the energy-delay product (EDP) ratio between Cu wire and monolayer SWCNT interconnect. Here, the imperfect contact resistance is neglected as it is highly dependent on the process. As the length exceeds 20 µ m, the EDP ratio becomes larger than 1, indicating that the monolayer SWCNT interconnect can provide better performance than the Cu counterpart. Moreover, the advantage of monolayer SWCNT interconnect becomes more evident for smaller inverter size. As discussed in [59], for short local interconnects, the interconnect resistances are not important, while their capacitances play a key role. So the electrical performance can be improved by using low aspect ratio interconnects such as monolayer metallic SWCNT. It can be seen in Figure 10a that monolayer SWCNT interconnect possesses smaller parasitic capacitance than Cu wire. Therefore, it can be expected that monolayer SWCNT interconnects can reduce power dissipation and crosstalk noise [60]. Figure 10b depicts the energy-delay product (EDP) ratio between Cu wire and monolayer SWCNT interconnect. Here, the imperfect contact resistance is neglected as it is highly dependent on the process. As the length exceeds 20 µm, the EDP ratio becomes larger than 1, indicating that the monolayer SWCNT interconnect can provide better performance than the Cu counterpart. Moreover, the advantage of monolayer SWCNT interconnect becomes more evident for smaller inverter size. To further reduce the interconnect resistance, as shown in Figure 9b, the bundled SWCNTs have been proposed and manufactured [61][62][63]. It is worth noting that for the pristine SWCNTs with random distribution of chirality, one-third are metallic and two-thirds are semiconducting. Researchers have been continually tasked to improve the metallic fraction. For instance, Harutyunyan, et al. [64] successfully fabricated a bundled SWCNTs with very high metallic fraction of 0.91. Based on physical models, Naeemi, et al. [65] developed the circuit model for bundled SWCNT interconnect and demonstrated its potential for solving several major challenges facing gigascale integrated systems. Besides the applications as horizontal interconnects, bundled SWCNTs were also proposed as on-chip vias to reduce temperature rise and increase the electromigration resistance [66][67][68][69].
Unlike SWCNTs, MWCNTs are always metallic. By assuming one-third of shells are metallic, the number of conducting channels of a shell in an MWCNT can be calculated by [70] = 2.04 × 10 + 0.425, > ⁄ 2 3 ⁄ , < ⁄ where = 1300 nm ⋅ K. For an MWCNT interconnect, as shown in Figure 9c, it is usually assumed that the innermost shell diameter is half of the outermost shell diameter, and the aspect ratio is 2, i.e., two parallel MWCNTs are stacked. In general, an MWCNT possesses a longer MFP but smaller number of conducting channels than the bundled SWCNTs with the same cross-sectional dimensions. For MWCNT interconnects, Li, et al. [71] developed a multiconductor transmission line model, which was further simplified as an ESC transmission line model [40]. It was demonstrated that the ESC model can accurately predict the time delay and facilitate the simulation speed although it would result in an overestimation of peak crosstalk [72].  To further reduce the interconnect resistance, as shown in Figure 9b, the bundled SWCNTs have been proposed and manufactured [61][62][63]. It is worth noting that for the pristine SWCNTs with random distribution of chirality, one-third are metallic and two-thirds are semiconducting. Researchers have been continually tasked to improve the metallic fraction. For instance, Harutyunyan, et al. [64] successfully fabricated a bundled SWCNTs with very high metallic fraction of 0.91. Based on physical models, Naeemi, et al. [65] developed the circuit model for bundled SWCNT interconnect and demonstrated its potential for solving several major challenges facing gigascale integrated systems. Besides the applications as horizontal interconnects, bundled SWCNTs were also proposed as on-chip vias to reduce temperature rise and increase the electromigration resistance [66][67][68][69].
Unlike SWCNTs, MWCNTs are always metallic. By assuming one-third of shells are metallic, the number of conducting channels of a shell in an MWCNT can be calculated by [70] N ch = 2.04 × 10 5 TD + 0.425, D > D T /T 2/3, where D T = 1300 nm · K. For an MWCNT interconnect, as shown in Figure 9c, it is usually assumed that the innermost shell diameter is half of the outermost shell diameter, and the aspect ratio is 2, i.e., two parallel MWCNTs are stacked. In general, an MWCNT possesses a longer MFP but smaller number of conducting channels than the bundled SWCNTs with the same cross-sectional dimensions. For MWCNT interconnects, Li, et al. [71] developed a multiconductor transmission line model, which was further simplified as an ESC transmission line model [40]. It was demonstrated that the ESC model can accurately predict the time delay and facilitate the simulation speed although it would result in an overestimation of peak crosstalk [72]. Based on the ESC model, Liang, et al. [73] characterized the performance of MWCNT interconnects by using the finite-difference time-domain (FDTD) method.
On the other hand, to reduce the interconnect delay, the repeater insertion is usually employed in the design of high-performance VLSI [42]. Previous studies have been carried out to investigate the optimal repeater insertion for CNT interconnects [75,84]. Unfortunately, these studies didn't consider the impact of metal-CNT contact resistance, which would be added along with each inserted repeater and surely influence the time delay, as shown in Figure 11 [85]. To resolve this issue, an analytical expression of the optimal repeater number was derived based on the Elmore delay equation in [86]. Furthermore, the influence of inductance on the repeater design in an MWCNT interconnect was considered [87]. Using the multivariable curve fitting technique, the closed-form expressions of optimal repeater size and the optimal number of segments can be obtained. Definitely, the smaller contact resistance is, the better performance can be achieved. Here, the maximum tolerant contact resistance of MWCNT interconnect is defined, beyond which the total time delay of MWCNT interconnect would be larger than that of Cu counterpart. Figure 12 gives the minimum time delay of an MWCNT interconnect versus contact resistance. It is shown that the maximum tolerant contact resistance increases from 3.3 kΩ to 10.5 kΩ as the technology node scales from 14 nm to 7 nm. Considering the size effect, however, the contact resistance will be scaled up 4 times from 14 nm node to 7 nm node. In other words, more efforts should be put on reducing the contact resistance with the technology advanced. On the other hand, to reduce the interconnect delay, the repeater insertion is usually employed in the design of high-performance VLSI [42]. Previous studies have been carried out to investigate the optimal repeater insertion for CNT interconnects [75,84]. Unfortunately, these studies didn't consider the impact of metal-CNT contact resistance, which would be added along with each inserted repeater and surely influence the time delay, as shown in Figure 11 [85]. To resolve this issue, an analytical expression of the optimal repeater number was derived based on the Elmore delay equation in [86]. Furthermore, the influence of inductance on the repeater design in an MWCNT interconnect was considered [87]. Using the multivariable curve fitting technique, the closed-form expressions of optimal repeater size and the optimal number of segments can be obtained. Definitely, the smaller contact resistance is, the better performance can be achieved. Here, the maximum tolerant contact resistance of MWCNT interconnect is defined, beyond which the total time delay of MWCNT interconnect would be larger than that of Cu counterpart. Figure 12 gives the minimum time delay of an MWCNT interconnect versus contact resistance. It is shown that the maximum tolerant contact resistance increases from 3.3 kΩ to 10.5 kΩ as the technology node scales from 14 nm to 7 nm. Considering the size effect, however, the contact resistance will be scaled up 4 times from 14 nm node to 7 nm node. In other words, more efforts should be put on reducing the contact resistance with the technology advanced.  As the IC feature size scales down, interconnects consume more and more power. Simply ignoring the power consumed by repeaters would cause an overestimation of optimal repeater number. Therefore, some repeater insertion methodologies have been developed targeting in reducing power dissipation of conventional Cu interconnects [88,89]. Further, a repeater design methodology to reduce delay and power of CNT interconnects has been proposed in [90], with the metal-CNT contact resistance treated appropriately. In [90], the particle swarm optimization (PSO) algorithm was employed to capture the optimal values of repeater size and repeater number. To facilitate the simulation speed, the obtained data was then used to train a neural network, as shown in Figure 13a. It was demonstrated that the trained neural network can predict the optimal repeater size and number rapidly and accurately, as shown in Figure 13b. On the other hand, to reduce the interconnect delay, the repeater insertion is usually employed in the design of high-performance VLSI [42]. Previous studies have been carried out to investigate the optimal repeater insertion for CNT interconnects [75,84]. Unfortunately, these studies didn't consider the impact of metal-CNT contact resistance, which would be added along with each inserted repeater and surely influence the time delay, as shown in Figure 11 [85]. To resolve this issue, an analytical expression of the optimal repeater number was derived based on the Elmore delay equation in [86]. Furthermore, the influence of inductance on the repeater design in an MWCNT interconnect was considered [87]. Using the multivariable curve fitting technique, the closed-form expressions of optimal repeater size and the optimal number of segments can be obtained. Definitely, the smaller contact resistance is, the better performance can be achieved. Here, the maximum tolerant contact resistance of MWCNT interconnect is defined, beyond which the total time delay of MWCNT interconnect would be larger than that of Cu counterpart. Figure 12 gives the minimum time delay of an MWCNT interconnect versus contact resistance. It is shown that the maximum tolerant contact resistance increases from 3.3 kΩ to 10.5 kΩ as the technology node scales from 14 nm to 7 nm. Considering the size effect, however, the contact resistance will be scaled up 4 times from 14 nm node to 7 nm node. In other words, more efforts should be put on reducing the contact resistance with the technology advanced.  As the IC feature size scales down, interconnects consume more and more power. Simply ignoring the power consumed by repeaters would cause an overestimation of optimal repeater number. Therefore, some repeater insertion methodologies have been developed targeting in reducing power dissipation of conventional Cu interconnects [88,89]. Further, a repeater design methodology to reduce delay and power of CNT interconnects has been proposed in [90], with the metal-CNT contact resistance treated appropriately. In [90], the particle swarm optimization (PSO) algorithm was employed to capture the optimal values of repeater size and repeater number. To facilitate the simulation speed, the obtained data was then used to train a neural network, as shown in Figure 13a. It was demonstrated that the trained neural network can predict the optimal repeater size and number rapidly and accurately, as shown in Figure 13b. As the IC feature size scales down, interconnects consume more and more power. Simply ignoring the power consumed by repeaters would cause an overestimation of optimal repeater number. Therefore, some repeater insertion methodologies have been developed targeting in reducing power dissipation of conventional Cu interconnects [88,89]. Further, a repeater design methodology to reduce delay and power of CNT interconnects has been proposed in [90], with the metal-CNT contact resistance treated appropriately. In [90], the particle swarm optimization (PSO) algorithm was employed to capture the optimal values of repeater size and repeater number. To facilitate the simulation speed, the obtained data was then used to train a neural network, as shown in Figure 13a. It was demonstrated that the trained neural network can predict the optimal repeater size and number rapidly and accurately, as shown in Figure 13b.

All-Carbon 3-D Interconnects
In general, CNTs grow vertically, whereas graphene is formed horizontally. So, it is natural to develop the 3-D interconnects by combining vertical CNT vias and horizontal GNR interconnects, as shown in Figure 14. Nihei, et al. [91] firstly conceived, designed and realized the experiment to grow an MWCNT via on multilayer graphene. The critical issue to fabricate such "all-carbon" 3-D interconnects is to achieve a low electrical contact between the CNT via and the GNR interconnect. Further, Ramos, et al. [92] introduced a process to selectively grow CNTs on monolayer graphene. They demonstrated that the growth of CNTs would not damage the integrity of graphene and characterized the contact resistance between CNTs and graphene. Zhou, et al. [93] studied the CNTgraphene interface using transmission electron microscope and found that C-C bonding exists between CNT and graphene. Recently, Jiang, et al. [94] comprehensively investigated the fabrication, integration, and reliability of such "all-carbon" 3-D interconnects. Besides, it is worth noting that another "all-carbon" 3-D interconnect scheme, i.e., a dense vertical and horizontal graphene structure, has been demonstrated in [91].

All-Carbon 3-D Interconnects
In general, CNTs grow vertically, whereas graphene is formed horizontally. So, it is natural to develop the 3-D interconnects by combining vertical CNT vias and horizontal GNR interconnects, as shown in Figure 14. Nihei, et al. [91] firstly conceived, designed and realized the experiment to grow an MWCNT via on multilayer graphene. The critical issue to fabricate such "all-carbon" 3-D interconnects is to achieve a low electrical contact between the CNT via and the GNR interconnect. Further, Ramos, et al. [92] introduced a process to selectively grow CNTs on monolayer graphene. They demonstrated that the growth of CNTs would not damage the integrity of graphene and characterized the contact resistance between CNTs and graphene. Zhou, et al. [93] studied the CNT-graphene interface using transmission electron microscope and found that C-C bonding exists between CNT and graphene. Recently, Jiang, et al. [94] comprehensively investigated the fabrication, integration, and reliability of such "all-carbon" 3-D interconnects. Besides, it is worth noting that another "all-carbon" 3-D interconnect scheme, i.e., a dense vertical and horizontal graphene structure, has been demonstrated in [91].

All-Carbon 3-D Interconnects
In general, CNTs grow vertically, whereas graphene is formed horizontally. So, it is natural to develop the 3-D interconnects by combining vertical CNT vias and horizontal GNR interconnects, as shown in Figure 14. Nihei, et al. [91] firstly conceived, designed and realized the experiment to grow an MWCNT via on multilayer graphene. The critical issue to fabricate such "all-carbon" 3-D interconnects is to achieve a low electrical contact between the CNT via and the GNR interconnect. Further, Ramos, et al. [92] introduced a process to selectively grow CNTs on monolayer graphene. They demonstrated that the growth of CNTs would not damage the integrity of graphene and characterized the contact resistance between CNTs and graphene. Zhou, et al. [93] studied the CNTgraphene interface using transmission electron microscope and found that C-C bonding exists between CNT and graphene. Recently, Jiang, et al. [94] comprehensively investigated the fabrication, integration, and reliability of such "all-carbon" 3-D interconnects. Besides, it is worth noting that another "all-carbon" 3-D interconnect scheme, i.e., a dense vertical and horizontal graphene structure, has been demonstrated in [91].  Using the finite-element method (FEM), the electrothermal characteristics of all-carbon 3-D interconnects have been studied in [95]. Figure 15a shows the simulation model, which is formed by one horizontal interconnect and two vertical vias. The 3-D interconnect structure is embedded into an interlayer dielectric, whose thermal conductivity is about 0.12 W/m·K. The bottom temperature is assumed as 363 K, and the other boundaries are set as adiabatic. The out-plane electrical conductivity of the MLGNR is 1 S/m. The geometrical parameters are adopted at the 22 nm technology node from the ITRS projection [2]. With a current of 0.4 mA injected, the temperature profiles are plotted in Figure 15b-d. In the simulation, a 1 nm-thick thin plate was used to capture the influences of contact resistance. Due to the impact of quantum contact resistance, all-carbon 3-D interconnect is more resistive than Cu counterpart, thereby increasing the temperature rise. On the contrary, the CNT vias help heat dissipation from hotspots to the bottom layer. Therefore, the maximum temperature is slightly increased with the implementation of all-carbon 3-D interconnects. The results also imply that CNT vias are more suitable to be placed near bottom layer. Using the finite-element method (FEM), the electrothermal characteristics of all-carbon 3-D interconnects have been studied in [95]. Figure 15a shows the simulation model, which is formed by one horizontal interconnect and two vertical vias. The 3-D interconnect structure is embedded into an interlayer dielectric, whose thermal conductivity is about 0.12 W/m‧K. The bottom temperature is assumed as 363 K, and the other boundaries are set as adiabatic. The out-plane electrical conductivity of the MLGNR is 1 S/m. The geometrical parameters are adopted at the 22 nm technology node from the ITRS projection [2]. With a current of 0.4 mA injected, the temperature profiles are plotted in Figure 15b-d. In the simulation, a 1 nm-thick thin plate was used to capture the influences of contact resistance. Due to the impact of quantum contact resistance, all-carbon 3-D interconnect is more resistive than Cu counterpart, thereby increasing the temperature rise. On the contrary, the CNT vias help heat dissipation from hotspots to the bottom layer. Therefore, the maximum temperature is slightly increased with the implementation of all-carbon 3-D interconnects. The results also imply that CNT vias are more suitable to be placed near bottom layer.

Cu-Graphene Interconnect
During the past decades, tremendous progress has been made in the fabrication/integration of nanocarbon interconnects. However, the gap between theoretical studies and practical applications still exists. For example, the assumption of closed packed CNTs is invalid as the density of CNTs still cannot satisfy the requirements [96]. Also, the application of MLGNR interconnects encounters a serious challenge, i.e., graphene tends to behave more like graphite as the number of graphene layers increases [97]. In this perspective, Cu/low-k interconnect may be still a good choice for nextgeneration ICs [98].
In the application of Cu/low-k interconnect, a highly resistive diffusion barrier layer is required to prevent the diffusion of copper atoms into substrate. This barrier layer would occupy a certain area, thereby decreasing the conduction area of interconnects and increasing the effective resistivity. More importantly, the barrier layer thickness cannot scale as rapidly as the interconnect dimensions [4]. This problem becomes more and more serious with the technology advanced. To resolve this

Cu-Graphene Interconnect
During the past decades, tremendous progress has been made in the fabrication/integration of nanocarbon interconnects. However, the gap between theoretical studies and practical applications still exists. For example, the assumption of closed packed CNTs is invalid as the density of CNTs still cannot satisfy the requirements [96]. Also, the application of MLGNR interconnects encounters a serious challenge, i.e., graphene tends to behave more like graphite as the number of graphene layers increases [97]. In this perspective, Cu/low-k interconnect may be still a good choice for next-generation ICs [98].
In the application of Cu/low-k interconnect, a highly resistive diffusion barrier layer is required to prevent the diffusion of copper atoms into substrate. This barrier layer would occupy a certain area, thereby decreasing the conduction area of interconnects and increasing the effective resistivity. More importantly, the barrier layer thickness cannot scale as rapidly as the interconnect dimensions [4]. This problem becomes more and more serious with the technology advanced. To resolve this problem, graphene, the thinnest 2-D material in nature, has been proposed as the ultimate barrier layer [99][100][101]. It has been demonstrated that graphene barrier layer can help improving the breakdown current density, enhancing the electromigration lifetime, increasing the Cu grain size, and reducing the scattering probability at the surface [102][103][104][105][106]. Moreover, low-temperature deposition techniques for producing graphene on Cu and dielectric implies that the fabrication of graphene barrier layer can be compatible with traditional CMOS technology [101,104,107,108]. Figure 16 shows the schematic view of a Cu-graphene interconnect, i.e., Cu wire encapsulated with graphene barrier layers. To gain an in-depth understanding of such a Cu-graphene interconnect, it is necessary to develop its circuit model and evaluate its electrical and thermal performances. In [109], a distributed resistor model for Cu-graphene interconnect has been established, and the Cu-graphene interface resistance and graphene-graphene interface resistance have been considered and treated appropriately. The effective resistance of Cu-graphene interconnect can be derived as where M represents the number of segments meshed along the interconnect length, R Cu is the resistance of the central Cu wire, I 1

M×M
is the M × M unit diagonal matrix, and [A 21 ] can be obtained using the Kirchhoff's voltage law. The subscripts t, b, l, and r represent the respective corresponding quantities as graphene barrier layers are placed at the top, bottom, left, and right surfaces of the Cu wire. It was demonstrated that the graphene barrier layers can share part of the current, thereby reducing the current passing through the central Cu wire and improving the reliability. Moreover, as the interconnect length exceeds several tens of micrometers, the central Cu wire, and graphene barrier layers can be treated as being parallel connected, and the effective resistance can be simplified as , where R gr denotes the resistance of graphene barrier layer and N is the layer number [110].
Appl. Sci. 2019, 9,2174 12 of 20 graphene interface resistance and graphene-graphene interface resistance have been considered and treated appropriately. The effective resistance of Cu-graphene interconnect can be derived as where represents the number of segments meshed along the interconnect length, is the resistance of the central Cu wire, × is the × unit diagonal matrix, and can be obtained using the Kirchhoff's voltage law. The subscripts , , , and represent the respective corresponding quantities as graphene barrier layers are placed at the top, bottom, left, and right surfaces of the Cu wire. It was demonstrated that the graphene barrier layers can share part of the current, thereby reducing the current passing through the central Cu wire and improving the reliability. Moreover, as the interconnect length exceeds several tens of micrometers, the central Cu wire, and graphene barrier layers can be treated as being parallel connected, and the effective resistance can be simplified as , where denotes the resistance of graphene barrier layer and is the layer number [110].  Figure 17a depicts the effective resistivity of Cu-graphene interconnects versus temperature. According to ITRS prediction, the barrier layer thickness would scale down to 1.3 nm at the 22 nm node [2]. However, such prediction is too optimistic and too challenging. Here, the barrier layer thicknesses of 1.3 nm and 2 × 1.3 nm are considered as references. It is evident that the effective resistivity can be reduced significantly by introducing graphene barrier layer, which is mainly due to the reduced Cu surface scattering [104]. Further, Figure 17b compares the effective resistivity of Cu wire and Cu-graphene interconnect at different technology nodes. The barrier layer thickness at each node is adopted from the ITRS projection [2]. It was found that the advantage of Cu-graphene interconnect over Cu wire becomes more significant with the IC feature size scaling down.
(a) (b) Figure 16. Schematic of Cu-graphene interconnect. Figure 17a depicts the effective resistivity of Cu-graphene interconnects versus temperature. According to ITRS prediction, the barrier layer thickness would scale down to 1.3 nm at the 22 nm node [2]. However, such prediction is too optimistic and too challenging. Here, the barrier layer thicknesses of 1.3 nm and 2 × 1.3 nm are considered as references. It is evident that the effective resistivity can be reduced significantly by introducing graphene barrier layer, which is mainly due to the reduced Cu surface scattering [104]. Further, Figure 17b compares the effective resistivity of Cu wire and Cu-graphene interconnect at different technology nodes. The barrier layer thickness at each node is adopted from the ITRS projection [2]. It was found that the advantage of Cu-graphene interconnect over Cu wire becomes more significant with the IC feature size scaling down.
node [2]. However, such prediction is too optimistic and too challenging. Here, the barrier layer thicknesses of 1.3 nm and 2×1.3 nm are considered as references. It is evident that the effective resistivity can be reduced significantly by introducing graphene barrier layer, which is mainly due to the reduced Cu surface scattering [104]. Further, Figure 17(b) compares the effective resistivity of Cu wire and Cu-graphene interconnect at different technology nodes. The barrier layer thickness at each node is adopted from the ITRS projection [2]. It was found that the advantage of Cu-graphene interconnect over Cu wire becomes more significant with the IC feature size scaling down.

Cu-CNT Composite Interconnect
Generally speaking, nanocarbon and conventional metals have their own pros and cons for interconnect applications. For instance, nanocarbon has high ampacity, but their conductivity is still low due to fabrication limits. On the contrary, the fabrication and integration processes of metal interconnects are mature, but the ampacity of metals cannot satisfy the requirements [2]. Subramaniam, et al. [111] attempted to advance a possible solution to this problem by co-depositing Cu with CNTs, i.e., Cu-CNT composite interconnect. It was experimentally demonstrated that Cu-CNT composite interconnect can achieve a balance between performance and reliability. This is, such Cu-CNT composite interconnect possesses a 100 times higher ampacity, but comparable conductivity than the Cu counterpart. The presence of CNTs inside Cu wire can also alleviate the electromigration void growth rate by about four times, which is due to large Lorenz number of the CNTs [112,113]. Figure 18 shows the schematic of a Cu-CNT composite interconnect over a ground plane. In the figure, N identical CNTs are uniformly distributed inside the Cu wire. The CNTs can be SWCNTs or MWCNTs. Here, we define the CNT filling ratio as f CNT = Nπ(D + 0.31 nm) 2 /(4WT), where 0.31 nm is due to the separation between carbon and Cu atoms. The p.u.l. scattering resistance of the Cu-CNT composite interconnect can be calculated as R = 1/(σ eff WT), where [114,115]. The effective conductivity of CNTs σ CNT is given by [116] σ CNT ≈ Fm × 4L π(D + 0.31 nm) 2 1 Z CNT (10) where Fm the metallic fraction, and Z CNT is the self-impedance of an isolated CNT.

Cu-CNT Composite Interconnect
Generally speaking, nanocarbon and conventional metals have their own pros and cons for interconnect applications. For instance, nanocarbon has high ampacity, but their conductivity is still low due to fabrication limits. On the contrary, the fabrication and integration processes of metal interconnects are mature, but the ampacity of metals cannot satisfy the requirements [2]. Subramaniam, et al. [111] attempted to advance a possible solution to this problem by co-depositing Cu with CNTs, i.e., Cu-CNT composite interconnect. It was experimentally demonstrated that Cu-CNT composite interconnect can achieve a balance between performance and reliability. This is, such Cu-CNT composite interconnect possesses a 100 times higher ampacity, but comparable conductivity than the Cu counterpart. The presence of CNTs inside Cu wire can also alleviate the electromigration void growth rate by about four times, which is due to large Lorenz number of the CNTs [112,113]. Figure 18 shows the schematic of a Cu-CNT composite interconnect over a ground plane. In the figure, identical CNTs are uniformly distributed inside the Cu wire. The CNTs can be SWCNTs or MWCNTs. Here, we define the CNT filling ratio as = + 0.31 nm 4 ⁄ , where 0.31 nm is due to the separation between carbon and Cu atoms. The p.u.l. scattering resistance of the Cu-CNT composite interconnect can be calculated as = 1 ⁄ , where = 1 − + [114,115]. The effective conductivity of CNTs is given by [116] ≈ × 4 + 0.31 nm 1 (10) where the metallic fraction, and is the self-impedance of an isolated CNT.    Figure 19a compares the effective resistivities of Cu, SWCNT, and Cu-SWCNT composite interconnects. Unlike the ideally packed SWCNTs discussed earlier, it is assumed that the CNT filling ratios are 0.3, 0.45, and 0.6 in the figure. It is evident that the resistivity of such sparsely distributed SWCNTs is much larger than Cu counterpart. However, co-depositing Cu with such sparsely distributed SWCNTs can reduce the resistivity. The predicted values are close to the measured data, which ranges from 2 to 2.27 µΩ [111]. Further, the time delays of Cu, SWCNT, and Cu-SWCNT composite interconnects are plotted in Figure 19b. The Cu-SWCNT composite interconnect can provide comparable performance with Cu counterpart, while the sparsely distributed SWCNTs show much worse performance due to their large resistivity. As the CNT quality may be degraded due to fabrication limits, the cases of lower value of CNT MFP are also plotted in Figure 19b. It can be seen that the Cu-SWCNT composite interconnects are much less influenced than pure SWCNTs.   In summary, this paper reviewed the current status of research on nanocarbon interconnects from the modeling perspective. The electrical performances of GNR, CNT, and Cu-nanocarbon interconnects are analyzed and discussed, with their pros and cons illustrated in Table 1. Although Cu wires have been widely used in modern ICs, their resistivity increases significantly with the scaling of feature size, which is exacerbated by the influence of diffusion barrier layer. In comparison with Cu counterparts, nanocarbon interconnects including GNR and CNT possess long MFP, high ampacity, and high electromigration resistance. However, the electrical properties of horizontal graphene are susceptible to substrate. Moreover, as nanocarbons are anisotropic, both MLGNR and CNT interconnects would hinder the IC heat dissipation. This problem can be resolved by utilizing VGNR interconnects although there is still a long way to go in the fabrication methods.

MWCNT SWCNT CNT Cu
Graphene was recently proposed as the ultimate diffusion barrier layer for Cu interconnect technology. By coating graphene onto Cu wires, the surface scattering of electrons in Cu can be reduced, and the grain size can be increased. To maximize the effective conduction area, large grain single-layer graphene is desired, and more efforts should be devoted to the development of low temperature and transfer free graphene growth techniques on dielectric and Cu. The scheme of Cu-CNT composite interconnect was realized by co-depositing Cu with CNTs. Such interconnect can achieve a balance between performance and reliability. However, with the scaling of IC feature size, both Cu-graphene and Cu-CNT composite interconnects face the challenge of performance degradation due to the increased scattering probability. Therefore, Cu-nanocarbon interconnects are a temporary but practical solution to meet short-term interconnect challenges. Yet in long-term, pure nanocarbon interconnects are still the most promising schemes, and they can be utilized together with Cu-nanocarbon interconnects.

Conclusions
The current status of research on nanocarbon interconnects from a modeling perspective has been reviewed in this paper. Several typical nanocarbon interconnects have been evaluated and discussed. It is demonstrated that nanocarbon interconnects are theoretically superior to their Cu counterparts. However, due to the fabrication limits, the electrical performance of nanocarbon interconnects may be much worse than their theoretical estimations. Cu-nanocarbon interconnects, including Cu-graphene and Cu-CNT composite interconnects, may be a practical solution to meet the near future challenges. With the IC feature size scaling down to sub-10 nm, however, nanocarbon interconnects are the most promising schemes. This is to say, in long-term applications, Cu-nanocarbon interconnects may be used together with the ultimate nanocarbon interconnects.