An AC/DC LED Driver with Unity Power Factor and Soft Switching

: Traditional light-emitting diode (LED) drivers with pulse-width modulation (PWM)-type converters suffer the problem of hard switching, leading to low circuit efﬁciency and low reliability. LED drivers supplied by alternating current (AC) line source generally require using an additional power-factor correction (PFC) stage to satisfy the regulations on power factor (PF) and total current harmonic distortion (THDi). It results in more circuit losses, especially when the active switch of the PFC stage operates at hard switching. This paper presents an alternating current-to-direct current (AC/DC) converter for driving high-brightness LEDs with the features of soft switching and high PF. The proposed single-stage circuit is formed by integrating a buck–boost converter and a buck converter. By elaborately rearranging the wirings between the circuit components of both converters, the power MOSFETs can be switched on at zero voltage. The operating modes at steady-state are analyzed and the mathematical equations for deriving circuit parameters are conducted. Finally, a prototype circuit for driving 60-W LEDs was built and measured. Based on the experimental results, the feasibility and satisfactory performance of the proposed LED driver are proved.


Introduction
Nowadays, high-brightness light-emitting diodes (LEDs) are popularly used to replace incandescent and fluorescent lamps in many applications owing to their advantages of small size, high luminous efficiency, long lifespan, high reliability, and environmental friendliness [1][2][3]. On the purpose of increasing the utilization factor of the power electric equipment and reduce the electromagnetic interference (EMI), some regulations such as IEC 61000-3-2 and IEEE 519, are enacted to restrict the power factor (PF) and total current harmonic distortion (THDi) of the alternating current-to-direct current (AC/DC) LED drivers to a reasonable range. In order to meet these regulations, an additional converter serving as a power-factor correction (PFC) stage is added to a DC/DC converter of which the output voltage is adjusted to drive LEDs. It results in a LED driver with two power-process stages. Although the two-stage approaches have satisfactory performance, they are not cost-effective products since two converters and two corresponding control circuits are required. In addition, the two-stage approaches take two energy-conversion processes, and hence produce more losses including switching loss and conduction loss. Aiming to solve the shortcomings Among the single-stage approaches, one power switch is commonly shared by the PFC stage and the DC/DC stage. Hence, they only use one control circuit and own the benefits of less component count and simply circuit topology. Nevertheless, the shared power switch should handle the current in both power-conversion stages, leading to more conducting losses. Moreover, the power switches of the single-stage approaches usually operate at hard switching and suffer the problem of high switching losses and high voltage and current stresses.
To further improve the circuit efficiency, literature proposed single-stage converters of which the power switches can fulfill soft switching to effectively reduce the switching losses [11][12][13]. Also, high PF and low THDi can be achieved. Unfortunately, there are still some defects required to be improved. In Reference [11], a coupled inductor is used in the buck-boost converter and its leakage inductance would incur high spike voltage across the power switch. In Reference [12], a boost converter serves as the PFC converter. Figure 1 shows the circuit topology that was proposed in Reference [12]. It integrates a boost converter and a buck converter. The boost converter serves as a PFC stage while the buck converter outputs a stable voltage to drive the load. High PF can be achieved, provided that the boost converter is operated at discontinuous current mode (DCM). However, a boost-typed PFC converter needs a high DC-link voltage to ensure DCM operation. It causes the circuit to require the use of high voltage rated components. For pursuing a better solution, this paper proposes a novel AC/DC converter to drive high power LEDs. The proposed circuit mainly consists of a buck-boost converter and a buck converter. Different from the circuit of Reference [12], when the boost-buck converter operates at DCM, it can obtain high power factor without needing a high DC-link voltage. A prototype circuit of 60-W was built and tested to verify the analytical predictions. Satisfactory performance is obtained from the experimental results.

Circuit Topology
The proposed AC/DC LED driver is derived by integrating a buck-boost converter and a buck converter, as shown in Figure 2. Two MOSFETs serve as the active switches, S1 and S2. The diodes DS1 and DS2 are the intrinsic diodes of S1 and S2, respectively. The buck-boost converter is formed by Lp, S2, DS1, D5, and Cdc. The buck converter is formed by Lb, S1, DS2, D6, D7, and Co. The low-pass filter is composed of Lm and Cm. The control circuit is mainly a half-bridge controller that is widely adopted to control the active switches of a Class-D inverter. The power switches S1 and S2 are driven by two gated voltage, vGS1 and vGS2. They are nonoverlapping and complementary rectangular-wave waveform. There is a short duration called deadtime. During the deadtime, both vGS1 and vGS2 are zero volts. Neglecting the deadtime, both vGS1 and vGS2 have a duty ratio of 0.5.
As compared to the circuit topology proposed in Reference [12], the proposed one uses a buckboost converter to serve the PFC stage while that of Reference [12] uses a boost converter. It is known that both converters operating at DCM can achieve nearly unity power factor. Nevertheless, when using a boost-typed PFC converter, it requires very high DC-link voltage to ensure unity power factor

Circuit Topology
The proposed AC/DC LED driver is derived by integrating a buck-boost converter and a buck converter, as shown in Figure 2. Two MOSFETs serve as the active switches, S 1 and S 2 . The diodes D S1 and D S2 are the intrinsic diodes of S 1 and S 2 , respectively. The buck-boost converter is formed by L p , S 2 , D S1 , D 5 , and C dc . The buck converter is formed by L b , S 1 , D S2 , D 6 , D 7 , and C o . The low-pass filter is composed of L m and C m . The control circuit is mainly a half-bridge controller that is widely adopted to control the active switches of a Class-D inverter. The power switches S 1 and S 2 are driven by two gated voltage, v GS1 and v GS2 . They are nonoverlapping and complementary rectangular-wave waveform. There is a short duration called deadtime. During the deadtime, both v GS1 and v GS2 are zero volts. Neglecting the deadtime, both v GS1 and v GS2 have a duty ratio of 0.5.
Appl. Sci. 2018, 8, x FOR PEER REVIEW 3 of 12 [14]. Although the proposed circuit needs to use two additional diodes, the voltage ratings of the circuit components could be lower than that of Reference [12].

Operation Analysis
For simplifying the circuit analysis, the following assumptions are made: 1. All the semiconductor devices are ideal except that the parasitic capacitances and the intrinsic diodes of the MOSFETs are considered. 2. The DC-link capacitor Cdc and the output capacitor Co are both large enough; thus, the DC-link voltage Vdc and the output voltage Vo can be regarded as constant. 3. The switching frequency of the active switches, fs, is much higher than that of the input-line voltage, fs. Hence, the input-line voltage is considered as constant during each high-frequency cycle.
At steady-state operation, the circuit operation can be divided into six modes in one highfrequency cycle. In order to make both power switches achieve zero-voltage switching (ZVS), both converters should be operated at DCM. These six operation modes are shown in Figure 3, where vrec represents the rectified input voltage. The illustrative current and voltage waveforms of some key components are shown in Prior to this mode, S1 is on and the DC link voltage Vdc supplies the buck-inductor current ib. Mode I begins at the instant of turning off S1. Thereby, ib would discharge the parasitic capacitance (CDS2) between the drain and source of S2. As soon as the voltage across CDS2 decreases to −0.7 V, DS2 is forward-biased to conduct ib. The gated voltage vGS2 becomes high level after the short deadtime and the current flowing through DS2 diverts to flow from the source to drain of the MOSFET S2. By this way, the voltage across S2 is clamped at near zero voltage. The voltage across the buck inductor Lb is minus of the output voltage Vo and hence, ib decreases linearly.
Since S2 is on, the voltage across the buck-boost inductor Lp is equal to vrec. As compared to the circuit topology proposed in Reference [12], the proposed one uses a buckboost converter to serve the PFC stage while that of Reference [12] uses a boost converter. It is known that both converters operating at DCM can achieve nearly unity power factor. Nevertheless, when using a boost-typed PFC converter, it requires very high DC-link voltage to ensure unity power factor [14]. Although the proposed circuit needs to use two additional diodes, the voltage ratings of the circuit components could be lower than that of Reference [12].

Operation Analysis
For simplifying the circuit analysis, the following assumptions are made: 1.
All the semiconductor devices are ideal except that the parasitic capacitances and the intrinsic diodes of the MOSFETs are considered.

2.
The DC-link capacitor C dc and the output capacitor C o are both large enough; thus, the DC-link voltage V dc and the output voltage V o can be regarded as constant.

3.
The switching frequency of the active switches, f s , is much higher than that of the input-line voltage, f s . Hence, the input-line voltage is considered as constant during each high-frequency cycle.
At steady-state operation, the circuit operation can be divided into six modes in one high-frequency cycle. In order to make both power switches achieve zero-voltage switching (ZVS), both converters should be operated at DCM. These six operation modes are shown in Figure 3, where v rec represents the rectified input voltage. The illustrative current and voltage waveforms of some key components are shown in Prior to this mode, S 1 is on and the DC link voltage V dc supplies the buck-inductor current i b . Mode I begins at the instant of turning off S 1 . Thereby, i b would discharge the parasitic capacitance (C DS2 ) between the drain and source of S 2 . As soon as the voltage across C DS2 decreases to −0.7 V, D S2 is forward-biased to conduct i b . The gated voltage v GS2 becomes high level after the short deadtime and the current flowing through D S2 diverts to flow from the source to drain of the MOSFET S 2 . By this Since S 2 is on, the voltage across the buck-boost inductor where f L and V m respectively represent the frequency and the amplitude of the input-line voltage.
Since the buck-boost converter is operated at DCM, the buck-boost current i p linearly increases from zero.
In this mode, i b is higher than i p . There are two current loops for i b . Parts of i b flow through S 2 , while the rest of i b is equal to i p , which flows through L p and the line-voltage source. This mode ends when i p becomes higher than i b .
At the beginning of Mode II, i p becomes higher than i b and the current flowing through S 2 changes direction. Parts of i p flow through S 2 from its drain to source, while the rest flows to the buck converter. The current i b is zero. S 2 is kept on and i p continues to increase. Mode III ends when the gated voltage v GS2 becomes low level to turn off S 2 , and the circuit operation enters Mode IV.

Mode IV (t 3 < t < t 4 ; in Figure 3d)
The current i p reach a peak value of each high-frequency cycle at the instant of turning off S 2 . The current i p will be diverted from S 2 to discharge the parasitic capacitance (C DS1 ) between the drain and source of S 1 . As soon as the voltage across C DS1 decreases to −0.7 V, D S1 is forward biased to conduct i p . The gated voltage v GS1 becomes high level after the short deadtime and i p diverts from D S1 to flow through S 1 from its source to drain. By this way, the voltage across S 1 is clamped at near zero voltage. Now, the current loop of i p is L p -S 1 -C dc -D 5 and the DC-link capacitance C dc is charged. The voltage across L p is equal to −V dc and hence, i p decrease linearly.
On the other hand, the current i b starts to increase from zero with the current loop: L p -D 6 -L b -C o -v rec . The voltage and current equations for the buck inductor can be expressed as: In this mode, i p is higher than i b . There are two current loops for i p . Parts of i p flow through S 1 to charge C dc , while its residual is equal to i b and flows into the buck converter. This mode ends when i b becomes higher than i p .
Appl. Sci. 2018, 8, x FOR PEER REVIEW 5 of 12   At the beginning of Mode V, ib becomes higher than ip and the current flowing through S1 changes direction. There are two current loops for ib. Parts of ib are supplied from the DC-link voltage and flows through S1, D6, Lb, Co, and D7 while the rest is equal to ip and flow through D6, Lb, Co, the line voltage source and Lp. The voltages across Lb and Lp can be respectively expressed as: The current equations of ip and ip can be expressed as The current ib increases linearly. From Equation (12), ip would decrease when Vdc is designed higher than the amplitude of the input-line voltage. This mode ends when ip decreases to zero.
2.2.6. Mode VI (t5 < t < t6; in Figure 3f) In this mode, S1 is remained on. Only the current ib keeps increasing linearly with the current path Vdc-S1-D6-Lb-Co-D7. This mode ends at the time when vGS1 becomes low level to turn off S1 and the circuit operation returns to Mode I of the next high-frequency cycle.
Base on the discussion in Mode I and Mode IV, as soon as the active switch of one converter is turned off, its inductor current diverts from the active switch. The diverting current flows through the parasitic capacitance of the active switch of the other converter. The parasitic capacitance is The current equations of i p and i p can be expressed as The current i b increases linearly. From Equation (12), i p would decrease when V dc is designed higher than the amplitude of the input-line voltage. This mode ends when i p decreases to zero.
2.2.6. Mode VI (t 5 < t < t 6 ; in Figure 3f) In this mode, S 1 is remained on. Only the current i b keeps increasing linearly with the current path V dc -S 1 -D 6 -L b -C o -D 7 . This mode ends at the time when v GS1 becomes low level to turn off S 1 and the circuit operation returns to Mode I of the next high-frequency cycle.
Base on the discussion in Mode I and Mode IV, as soon as the active switch of one converter is turned off, its inductor current diverts from the active switch. The diverting current flows through the parasitic capacitance of the active switch of the other converter. The parasitic capacitance is discharged and the voltage across it decreases. When the voltage across the parasitic capacitance decreases to −0.7 V, the intrinsic diode of the active switch turns on to conduct current and the voltage across the active switch is clamped at almost zero volts (−0.7 V). The gated voltage of the active switch should become high level before the current change polarity. Now, the active switch is ready for conducting current and its voltage is almost zero. When the switch current increases to pass zero and becomes positive, the positive current will flow from the source to drain of the active switch. By this way, the active switch is turned on at ZVS. For ensuring the ZVS operation, the deadtime of the two gated voltage (v GS1 and v GS2 ) should be longer than the duration for discharging the parasitic capacitance to −0.7 V. The parasitic capacitance of the MOSFET is very small. The parasitic capacitance would be fully discharged very quickly. Therefore, the deadtime could be short. The half-bridge controller commonly used in markets generally has the deadtime long enough to meet this requirement.

Buck-Boost Converter Equations
It is known that the maximum value of the buck-boost inductor current happens at the time when the input-line voltage is at the peak point of the sinusoidal waveform. For ensuring DCM operation at the peak, the following inequality should be satisfied.
where D is the duty ratio of the active switch. If Equation (13) is satisfied, the buck-boost converter can operate at DCM within the whole cycle of the input-line voltage.
For an AC/DC buck-boost converter operating at DCM, the input-line current and the input power can be expressed as Equations (14) and (15), respectively [15].
As shown in Equation (14), the input-line current is purely sinusoidal and in phase with the input-line voltage. It means that low THDi and high PF can be achieved by operating the buck-boost converter at DCM. From Equation (15), the output power can be expressed as where η represents the energy-conversion efficiency of the proposed circuit.

Buck Converter Equations
The buck converter is also designed to operate at DCM. For ensuring DCM operation, the output voltage should be high enough to satisfy the following inequality [12].
Appl. Sci. 2018, 8, 780 8 of 12 Besides this, the average of the buck inductor current is equal to the output current and can be expressed as [12]: From Equation (17), the output power can be expressed as:

Parameters Design
A prototype circuit of 60-W was designed and built to drive sixty 1-W high brightness LEDs connected in series. The rated voltage and current of each LED is 3.25 V and 0.308 A, respectively. The specification of the proposed LED driver is shown in Table 1.
By substituting the values of v in , V o , and D into Equations (13) and (17), the constraint of V dc can be obtained. In this illustrative example, V dc is designed to be 350 V. Assuming 93% circuit efficiency, the buck-boost inductor can be calculated from Equation (16).
The buck inductor can be calculated from Equation (19).
In order to achieve a sinusoidal input current, a low-pass filter is required to cascade in front of the rectifier bridge to filter out the high-frequency current induced from the buck-boost converter. L m and C m are designed to perform the ow-pass filter. By rule of thumb, the corner frequency of a low-pass filter should be lower than one eighth of the switching frequency. Here, the corner frequency is designed to be about 5 kHz, and L m and C m are determined to be L m = 2.0 mH, C m = 0.47 µF.
The circuit parameters of this prototype circuit are listed in Table 2.

Experimental Results
From Equation (16), it is noted that the switching frequency is used to control the output power. As seen in Figure 2, the LED current is sensed by a series resistor R s . The voltage across R s which is proportional to the LED current is compared to a reference value I ref , and their difference is amplified by an operational amplifier in the error amplifier (EA). The output of the operation amplifier is sent to the half-bridge controller which mainly consists of a double-ended controller (L6599). The outputs of the half-bridge controller are two complementary waveforms (v GS1 , v GS2 ) of which the frequency is regulated [12]. By this way, the switching frequency of the active switch is controlled to regulate the LED current. Figure 5 shows the measured waveforms of the input voltage and input current. The rms values of the input voltage and current are 112.4 V and 0.57 A, respectively. It can be observed that the input current is sinusoidal and in phase with the input voltage. The power quality in the input line is measured with a power analyzer (PowerLogic PM1000, Schneider Electric, Rueil-Malmaison, France). The measured PF is greater than 0.99, and the THDi is 3.5%. The inductor currents of both converters are shown in Figure 6 to indicate the DCM operation. There are spike currents in both the buck-boost inductor and the buck inductor. Theoretically, it is impossible to have a current spike in an inductor; otherwise, the voltage across the inductor would be tremendous high. The measured spike current in the buck-boost inductor and the buck inductor is believed to result from the interference voltage when one active switch is turned off. Figure 7 shows the waveforms of the output voltage and output current, which are well consistent with the design values. The DC values of the output voltage and current are 198.5 V and 0.304 A, respectively. In addition, the input power and output power are both measured with an oscilloscope. The measured values are 64 W and 60.3 W, respectively. The circuit efficiency is calculated to be 94.2%. Figure 8 shows waveforms of the voltage and current of the active switches. As shown, the switch current always increases from negative to positive. Its intrinsic diode conducts the negative current and clamps the switch voltage at almost zero volts. The active switch would naturally turn on as the switch current becomes positive, leading to ZVS operation. In the prototype circuit, MOSFET IRF840 serves the active switch. The current rating of the source-drain current (i.e., the current rating of the intrinsic diode) is 8 A maximum. It is seen in Figure 8, the maximum value of the diode current is about 3.5 A. Besides, the current in the intrinsic diode decreases linearly to zero. It means that the intrinsic diodes would turn off at zero current. Therefore, there is no faster diode in parallel with the active switch to replace the intrinsic diode. Figure 9 shows the prototype LED driver.
positive, leading to ZVS operation. In the prototype circuit, MOSFET IRF840 serves the active switch. The current rating of the source-drain current (i.e., the current rating of the intrinsic diode) is 8 A maximum. It is seen in Figure 8, the maximum value of the diode current is about 3.5 A. Besides, the current in the intrinsic diode decreases linearly to zero. It means that the intrinsic diodes would turn off at zero current. Therefore, there is no faster diode in parallel with the active switch to replace the intrinsic diode. Figure 9 shows the prototype LED driver.

Figure 9.
The prototype LED driver. Figure 9. The prototype LED driver.

Conclusions
A novel AC/DC LED driver derived by integrating a buck-boost converter and a buck converter is proposed. The buck-boost converter serves as PFC converter to achieve high PF and low THDi while the buck converter steps down the DC-link voltage to drive high power white LEDs. A 60-W prototype circuit is built and tested to verify the theoretical analyses. Both the active switches can achieve ZVS. Experimental results show that the proposed circuit performs satisfactorily. A nearly unity PF (>0.99) and low THDi (3.5%) are achieved. With ZVS operation on both active power switches, the proposed circuit efficiency is as high as 94.2%.