Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions

: In this work, we demonstrate a strained Si single nanowire tunnel ﬁeld effect transistor (TFET) with gate-all-around (GAA) structure yielding I on -current of 15 µ A/ µ m at the supply voltage of V dd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS) at room temperature shows an average of 76 mV/dec over 4 orders of drain current I d from 5 × 10 − 6 to 5 × 10 − 2 µ A/ µ m. Optimized devices also show excellent current saturation, an important feature for analog performance.


Introduction
Scaling of complementary metal oxide semiconductor (CMOS) technology has brought about significant improvements in terms of power dissipation, device density, switching frequency, and costs reductions. Continued reduction of device dimensions into the nanometers range faces major issues with the high leakage current, unscalability of supply voltage V dd , and lowered I on /I off switching ratio. The main constraint of metal-oxide-semiconductor field-effect transistor (MOSFET) for addressing these issues is the inverse subthreshold swing SS (=dV g /dlog(I d )), which is limited to 60 mV/dec at room temperature. Therefore, any attempt to scale V dd by adjusting threshold voltage V th will lead to exponentially higher I off -current, deteriorating the switching ratio. To enable further V dd scaling, steep slope device concepts (SS < 60 mV/dec) are required. The tunnel field effect transistor (TFET) is a promising alternative following the experimental demonstration of its sub-60 mV/dec swing [1]. TFET relies on quantum band-to-band tunneling (BTBT) to inject carriers from the source to the channel while cutting off the high-energy tail of the Fermi distribution, essentially having a similar effect to cooling down the distribution. Various research studies have demonstrated TFETs with SS < 60 mV/dec based on different materials like Si [2], Ge [3], SiGe [4], and III-V [5]. In comparison to the other materials, silicon-based TFETs generally show better performance in terms of minimum SS and switching ratio, mainly due to the maturity of silicon fabrication technology. Moreover, silicon TFETs are compatible with the conventional CMOS fabrication process, which keeps the costs low and makes it feasible to realize complementary TFET circuits [6,7].
By employing innovative materials, like high-k oxide and thin strained silicon, and highly scaled device structures, like nanowires (NWs), silicon TFETs have achieved promising results for both n-and p-type devices [8]. It is worth noting that these devices were based on an array of nanowires. The final results reflect the average behavior of all the NWs, dismissing the variations of each individual NW in the array. This stems from the fact that the tunneling probability at the source of TFETs has exponential dependence on process-related parameters, such as nanowire shape and doping profile. By means of simulation, C.-J. Chen et al [9] have shown that TFETs are more susceptible to process variations than MOSFETs. Consequently, a single NW is superior for optimization of TFETs. In this work, we seek to fabricate gate-all-around (GAA) TFETs based on a single NW with a top-down approach to optimize the key fabrication processes, namely ion implantation and dopant activation, thus enabling us to draw specific conclusions at each step to further improve the I on -current and average SS.

Device Fabrication
Single nanowire GAA TFETs were fabricated on strained silicon-on-insulator (sSOI) wafers with 15 nm biaxially strained silicon (ε biax,tensile = 0.8%) and 145 nm buried oxide (BOX). Strained silicon, due to its lower effective mass m * and lower bandgap E g , can achieve better tunneling current [10]. Figure 1 shows the process steps as well as schematics of the final device structure. The single NW was fabricated by a top-down process including e-beam lithography, subsequent reactive ion etching (RIE), and HF dip to suspend the nanowire. The final NW cross-section dimensions are 35 nm × 10 nm. After cleaning the substrate using RCA procedure, 3 nm HfO 2 by atomic layer deposition (ALD) and 60 nm TiN using atomic vapor deposition (AVD) were deposited as the high-k/metal gate stack. Then it was patterned using e-beam lithography and etched back by dry and wet etching. A very thin layer of 1.7 nm Ni was deposited by physical vapor deposition (PVD) to form a high quality NiSi 2 layer at the source and drain by annealing the substrate at 550 • C in forming gas for 30 s. The unreacted Ni residuals were selectively removed in a mixture of H 2 O:H 2 SO 4 . Ni silicide formed by this method yields good gate alignment without encroachment of silicide in the channel region [11]. Implantation was carried out into the silicide using boron and phosphorous ions with various energies and tilt angles. For each step of the ion implantation, the other side of the device was protected by polymethyl methacrylate (PMMA) photoresist in order to form p + and n + junctions. After implantations, the dopants were activated at various temperatures in N 2 environment, as will be discussed in the next section. Finally, the substrate was passivated by SiO 2 and final Al contacts were formed. Figure 2 shows a side view scanning electron microscope (SEM) image of the finished structure, where the gate completely wraps around the nanowire, leading to improved electrostatic control.
Appl. Sci. 2017, 7, x FOR PEER REVIEW 2 of 7 has exponential dependence on process-related parameters, such as nanowire shape and doping profile. By means of simulation, C.-J. Chen et al [9] have shown that TFETs are more susceptible to process variations than MOSFETs. Consequently, a single NW is superior for optimization of TFETs.
In this work, we seek to fabricate gate-all-around (GAA) TFETs based on a single NW with a top-down approach to optimize the key fabrication processes, namely ion implantation and dopant activation, thus enabling us to draw specific conclusions at each step to further improve the Ion-current and average SS.

Device Fabrication
Single nanowire GAA TFETs were fabricated on strained silicon-on-insulator (sSOI) wafers with 15 nm biaxially strained silicon ( biax,tensile = 0.8%) and 145 nm buried oxide (BOX). Strained silicon, due to its lower effective mass m * and lower bandgap Eg, can achieve better tunneling current [10]. Figure 1 shows the process steps as well as schematics of the final device structure. The single NW was fabricated by a top-down process including e-beam lithography, subsequent reactive ion etching (RIE), and HF dip to suspend the nanowire. The final NW cross-section dimensions are 35 nm × 10 nm. After cleaning the substrate using RCA procedure, 3 nm HfO2 by atomic layer deposition (ALD) and 60 nm TiN using atomic vapor deposition (AVD) were deposited as the high-k/metal gate stack. Then it was patterned using e-beam lithography and etched back by dry and wet etching. A very thin layer of 1.7 nm Ni was deposited by physical vapor deposition (PVD) to form a high quality NiSi2 layer at the source and drain by annealing the substrate at 550 °C in forming gas for 30 s. The unreacted Ni residuals were selectively removed in a mixture of H2O:H2SO4. Ni silicide formed by this method yields good gate alignment without encroachment of silicide in the channel region [11]. Implantation was carried out into the silicide using boron and phosphorous ions with various energies and tilt angles. For each step of the ion implantation, the other side of the device was protected by polymethyl methacrylate (PMMA) photoresist in order to form p + and n + junctions. After implantations, the dopants were activated at various temperatures in N2 environment, as will be discussed in the next section. Finally, the substrate was passivated by SiO2 and final Al contacts were formed. Figure 2 shows a side view scanning electron microscope (SEM) image of the finished structure, where the gate completely wraps around the nanowire, leading to improved electrostatic control.

Device Characteristics
In this part, we will evaluate the effect of implantation and fabrication parameters on the optimized performance of TFETs for high Ion current and minimum average SS. The first set of devices (Set 1) were implanted with P + ions to a dose of 1 × 10 15 cm −2 at an energy of 3 keV and B + ions to a dose of 5 × 10 14 cm −2 at 1.5 keV both at 45° tilt. The reason for a lower B + dose is to suppress the nbranch of the ambipolar behavior. Samples were activated at two different temperatures of 500 °C and 600 °C for 20 s. Figure 3a depicts the measured transfer characteristics Id-Vgs of the device for a p-TFET. As evident from the figure, the TFET activated at the higher temperature shows degraded SS and lower Ion current compared to the device activated at 500 °C. This is due to the fact that the higher temperature annealing causes more extended diffusion of dopants, hence decreasing the steepness of the tunneling junction. Figure 3b shows the output Id-Vds characteristics for devices at Vov = −1 V, which is defined as Vov = Vgs − Voff = −1 V for an Ioff = 1 nA/um. The typical super-linear onset of drain current Id at small Vds is present in the Id-Vds curves. The super-linear onset stems from drain-induced barrier thinning (DIBT) [12], which can be mitigated by increasing the dopant concentration at the tunneling junction [13]. In other words, for both temperature cases the dopant concentration at the source is lower than the optimum value and needs to be further increased.

Device Characteristics
In this part, we will evaluate the effect of implantation and fabrication parameters on the optimized performance of TFETs for high I on current and minimum average SS. The first set of devices (Set 1) were implanted with P + ions to a dose of 1 × 10 15 cm −2 at an energy of 3 keV and B + ions to a dose of 5 × 10 14 cm −2 at 1.5 keV both at 45 • tilt. The reason for a lower B + dose is to suppress the n-branch of the ambipolar behavior. Samples were activated at two different temperatures of 500 • C and 600 • C for 20 s. Figure 3a depicts the measured transfer characteristics I d -V gs of the device for a p-TFET. As evident from the figure, the TFET activated at the higher temperature shows degraded SS and lower I on current compared to the device activated at 500 • C. This is due to the fact that the higher temperature annealing causes more extended diffusion of dopants, hence decreasing the steepness of the tunneling junction. Figure 3b shows the output I d -V ds characteristics for devices at V ov = −1 V, which is defined as V ov = V gs − V off = −1 V for an I off = 1 nA/um. The typical super-linear onset of drain current I d at small V ds is present in the I d -V ds curves. The super-linear onset stems from drain-induced barrier thinning (DIBT) [12], which can be mitigated by increasing the dopant concentration at the tunneling junction [13]. In other words, for both temperature cases the dopant concentration at the source is lower than the optimum value and needs to be further increased.

Device Characteristics
In this part, we will evaluate the effect of implantation and fabrication parameters on the optimized performance of TFETs for high Ion current and minimum average SS. The first set of devices (Set 1) were implanted with P + ions to a dose of 1 × 10 15 cm −2 at an energy of 3 keV and B + ions to a dose of 5 × 10 14 cm −2 at 1.5 keV both at 45° tilt. The reason for a lower B + dose is to suppress the nbranch of the ambipolar behavior. Samples were activated at two different temperatures of 500 °C and 600 °C for 20 s. Figure 3a depicts the measured transfer characteristics Id-Vgs of the device for a p-TFET. As evident from the figure, the TFET activated at the higher temperature shows degraded SS and lower Ion current compared to the device activated at 500 °C. This is due to the fact that the higher temperature annealing causes more extended diffusion of dopants, hence decreasing the steepness of the tunneling junction. Figure 3b shows the output Id-Vds characteristics for devices at Vov = −1 V, which is defined as Vov = Vgs − Voff = −1 V for an Ioff = 1 nA/um. The typical super-linear onset of drain current Id at small Vds is present in the Id-Vds curves. The super-linear onset stems from drain-induced barrier thinning (DIBT) [12], which can be mitigated by increasing the dopant concentration at the tunneling junction [13]. In other words, for both temperature cases the dopant concentration at the source is lower than the optimum value and needs to be further increased.   and B ions with a dose of 1 × 10 15 cm −2 at 1.5 keV were implanted at a tilt of +/− 45 • , respectively. The implantation doses were increased to provide enough dopant concentration at the junctions after activation. The annealing was carried out at 550 • C for 10 s to drive out the dopants to the silicide/channel interface for dopant segregation. The annealing time and temperature were decreased in order to achieve sharper junctions. Figure 4a,b shows the measured transfer characteristics I d -V gs for the Set 2 devices of both p-and n-TFETs, respectively. A TFET works in both modes, p-and n-type, due to the presence of tunneling junctions at both the source and drain side, which causes undesired ambipolar switching, a typical behavior of a TFET. Moreover, the p-TFET shows higher on current I on than n-TFET, corresponding to an I on of 2.41 µA/µm for p-TFET and 0.78 µA/µm for n-TFET respectively, at V ds = V on = V g − V off = −0.5 V for an I off = 1 nA/µm. The reason that n-TFETs show lower current could be due to the broader tunneling junction caused by faster B diffusion. For further analysis, Figure 4c,d shows the corresponding output characteristics I d -V ds for p-and n-TFET. The p-TFET shows very good current saturation and more importantly a linear onset. On the other hand, the n-TFET still shows a super-linear onset. Due to the higher diffusion coefficient of boron in silicon in comparison to phosphorus, annealing at 550 • C for 10 s is still not optimal for n-TFETs. To optimize the device performance, another set of TFETs (Set 2) were fabricated with different implantation and activation parameters. P ions with a dose 5 × 10 15 cm -2 and at an energy of 3 keV and B ions with a dose of 1 × 10 15 cm −2 at 1.5 keV were implanted at a tilt of +/− 45°, respectively. The implantation doses were increased to provide enough dopant concentration at the junctions after activation. The annealing was carried out at 550 °C for 10 s to drive out the dopants to the silicide/channel interface for dopant segregation. The annealing time and temperature were decreased in order to achieve sharper junctions. Figure 4a,b shows the measured transfer characteristics Id-Vgs for the Set 2 devices of both p-and n-TFETs, respectively. A TFET works in both modes, p-and n-type, due to the presence of tunneling junctions at both the source and drain side, which causes undesired ambipolar switching, a typical behavior of a TFET. Moreover, the p-TFET shows higher on current Ion than n-TFET, corresponding to an Ion of 2.41 μA/μm for p-TFET and 0.78 μA/μm for n-TFET respectively, at Vds = Von = Vg − Voff = −0.5 V for an Ioff = 1 nA/μm. The reason that n-TFETs show lower current could be due to the broader tunneling junction caused by faster B diffusion. For further analysis, Figure 4c,d shows the corresponding output characteristics Id-Vds for p-and n-TFET. The p-TFET shows very good current saturation and more importantly a linear onset. On the other hand, the n-TFET still shows a super-linear onset. Due to the higher diffusion coefficient of boron in silicon in comparison to phosphorus, annealing at 550 °C for 10 s is still not optimal for n-TFETs. Thus, Set 3 of TFETs was fabricated with the aim to optimize the super-linear onset of n-TFET. In this case, 1 × 10 15 cm −2 P + ions at 3 keV and 1 × 10 15 cm -2 B + ions at 0.8 keV both without tilt (in normal direction) were implanted for source and drain, respectively. The dopants were activated at 500 °C for 10 s. This combination of implantation tilt, energy, and activation were chosen to achieve steeper  Thus, Set 3 of TFETs was fabricated with the aim to optimize the super-linear onset of n-TFET. In this case, 1 × 10 15 cm −2 P + ions at 3 keV and 1 × 10 15 cm −2 B + ions at 0.8 keV both without tilt (in normal direction) were implanted for source and drain, respectively. The dopants were activated at 500 • C for 10 s. This combination of implantation tilt, energy, and activation were chosen to achieve steeper boron junctions. Figure 5a,b shows the transfer and output characteristics of the n-TFET device. The output characteristics show very good linear behavior by increasing V ds as well as excellent current saturation. The latter is a key performance parameter for analog applications, for example, a current mirror. Moreover, the on current was also improved compared to the Set 2 devices, showing I on = 15 µA/µm at V ov = V gs − V off = 0.5 V with an I off = 1 nA/µm. The average SS was also improved to 76 mV/dec over 4 orders of drain current I d . The minimum SS is still above 60 mV/dec, which could be attributed to the undesired effect of trap-assisted tunneling (TAT) caused by interface traps [14,15]. Figure 5c presents the I d -V gs characteristics for the p-i-n diode forward biased with various V d , as illustrated in the inset. The curves show typical forward p-i-n diode behavior-much higher currents than TFET and the current decreases with decreasing absolute V d . This also provides evidence of the TFET operations for the results shown in Figure 5a,b. Table 1 summarizes the fabrication parameters and the device performance.
Appl. Sci. 2017, 7, x FOR PEER REVIEW 5 of 7 boron junctions. Figure 5a,b shows the transfer and output characteristics of the n-TFET device. The output characteristics show very good linear behavior by increasing Vds as well as excellent current saturation. The latter is a key performance parameter for analog applications, for example, a current mirror. Moreover, the on current was also improved compared to the Set 2 devices, showing Ion = 15 μA/μm at Vov = Vgs − Voff = 0.5 V with an Ioff = 1 nA/μm. The average SS was also improved to 76 mV/dec over 4 orders of drain current Id. The minimum SS is still above 60 mV/dec, which could be attributed to the undesired effect of trap-assisted tunneling (TAT) caused by interface traps [14,15]. Figure 5c presents the Id-Vgs characteristics for the p-i-n diode forward biased with various Vd, as illustrated in the inset. The curves show typical forward p-i-n diode behavior-much higher currents than TFET and the current decreases with decreasing absolute Vd. This also provides evidence of the TFET operations for the results shown in Figure 5a,b. Table 1 summarizes the fabrication parameters and the device performance.  Table 1. A summary of different implantation and activation parameters and the corresponding results. I on was extracted at V ds = V on = V g − V off = −0.5 V for I off = 1 nA/µm. SS avg is the average subthreshold swing from the minimum of drain current for 4 orders of magnitude at V ds = 0.1 V.

Conclusions
By proposing the advantage of a single nanowire over an array of nanowires in studying the effect of different process steps, we have investigated how ion implantation and dopant activation parameters impact the performance of strained silicon single NW GAA TFETs. The goal was to improve the TFETs in terms of I on -current and average subthreshold swing. The best result was achieved for n-TFETs with ion implantation in the normal direction to the nanowire surface and dopant activation at a moderate temperature of 500 • C, as compared to the annealing temperature of 550 • C for p-TFETs. Such optimized n-TFETs deliver high I on -currents of 15 µA/µm at V dd = 0.5 V and a low average subthreshold swing of 76 mV/dec over 4 decades of drain current.