FPGA Implementation of a BPSK 1D-CNN Demodulator
AbstractIn this paper, we propose a field programmable gate array (FPGA) implementation of a one-dimensional convolution neural network (1D-CNN) demodulator for binary phase shift keying (BPSK). The 1D-CNN demodulator includes two 1D-CNNs and a decision module. Discrete time series of BPSK signals are imported into the well-trained 1D-CNNs. The 1D-CNNs detect the phase shifts’ moment and type, including phase shift from 0 to π and that from π to 0. The decision module combines results of the two 1D-CNNs and outputs the demodulated data. In order to improve the efficiency of resource utilization and operation speed of the FPGA circuit, a time-delay network for convolutional calculation and a structure for piecewise approximation for the activation function were designed. To enhance the performance of the 1D-CNN demodulator, universal and diversity training data considering five impact factors were generated specially. Experimental results under different channel conditions show that the proposed demodulator has good adaptability to frequency offset and short latency. The demodulation loss of the proposed demodulator can almost be kept within 2 dB. View Full-Text
Share & Cite This Article
Liu, Y.; Shen, Y.; Li, L.; Wang, H. FPGA Implementation of a BPSK 1D-CNN Demodulator. Appl. Sci. 2018, 8, 441.
Liu Y, Shen Y, Li L, Wang H. FPGA Implementation of a BPSK 1D-CNN Demodulator. Applied Sciences. 2018; 8(3):441.Chicago/Turabian Style
Liu, Yan; Shen, Yue; Li, Li; Wang, Hai. 2018. "FPGA Implementation of a BPSK 1D-CNN Demodulator." Appl. Sci. 8, no. 3: 441.
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.