A Power Processing Circuit for Indoor Wi-Fi Energy Harvesting for Ultra-Low Power Wireless Sensors

: This article proposes a complete power processing circuit for an indoor 2.45 GHz Wi-Fi energy harvesting system. The proposed power processing circuit works by using power harvested from indoor Wi-Fi transmitters. The overall system of this work is simpliﬁed as an equivalent circuit and analyzed mathematically. A two-port network is analyzed in formulating the relevant equations of the equivalent circuit. The importance of matching the impedance of a harvesting antenna to the rectiﬁer circuit is highlighted by using simulation analysis, and it is shown that the impedance matching for both components has satisﬁed the conditions for a high sensitivity circuit and radio frequency-to-direct current (RF-to-DC) power conversion. Actual experiments showed that the proposed power processing circuit could operate with an incident power as low as − 50 dBm. It has been found that the proposed harvesting system stored 0.11 J in a 200 mF supercapacitor as the storage device in 20 hours of the experimentation periods. Moreover, actual results for the overall energy harvesting system is compared with previous research, and it has been found that the proposed system has advantages over the listed works.


Introduction
The latest development of low power consumption electronic device has contributed to a variety of energy smart wireless sensors.The wireless sensor collects data such as temperature, capacitance, vital signs, etc. Table 1 shows some low power wireless sensors and their typical power consumptions presented by P cons .Mostly, the power requirements for the listed sensors are supplied by batteries.However, using batteries as an energy source has some disadvantages in the practical world, especially the replacement can be an issue when the stored energy is depleted.Alternatively, energy harvesting can be used as a new approach to powering wireless sensors.The energy harvesting system scavenges power from the ambient environment of wireless sensors, with popular ambient energy sources including thermal, vibrational, solar, electromagnetic, etc.And radio power transmitters can be used as an energy source for developling radio frequency energy harvesting systems (RFEHS), especially in urban areas where the transmitted radio frequency (RF) power is widely available at any time.

Temperature
Sensor [1] Capacitive Sensor [2] Biomedical Sensor [3] Actuator Network [4] There is some drawback when RF sources such as Wi-Fi are used as an energy source for an RFEHS.The drawback is regarding power density, especially in an indoor area, where it is often very low [5].Various RF power density levels for an outdoor environment in [6] have been summarized for several isotropic transmitters.In an indoor environment, a power density of 1 µW/cm 2 at 2.45 GHz spectrum has been used to drive low-power low duty cycle applications [7].Previous work on RFEHS has focused on single-band [8][9][10] and multi-band [11,12] operating frequencies.For multi-band frequencies energy harvesters, the amount of energy at the input can be high.However, due to the complexity of the multi-band system and the power drop at various rectifier diodes and power processing circuits, the radio frequency-to-direct current (RF-to-DC) conversion efficiency is often lower than the single-band RFEHS.
This research proposes a power processing circuit for a 2.45 GHz Wi-Fi indoor energy harvesting system which can accept the operational input power as low as −50 dBm.The proposed circuit acts also as an extension of a successful research reported in [13] with reduced charging time of the storage device.In this research, the analysis of the proposed power processing circuit with the other components of an RFEHS will be discussed using an equivalent circuit.A two-port network will be analyzed to derive the relevant equations for the equivalent circuit.Then simulation analysis on the impedance matching of the rectification circuit will show the effect of diode parameters on the operation of the proposed power processing circuit.At the end of this research, the power processing circuit will be tested in a practical environment to demonstrate its actual performance with all the components of the proposed RFEHS.

The General Block Diagram
An illustration in Figure 1 shows a general block diagram of the proposed power processing circuit together with the power management unit (PMU) of the full RFEHS system.In the block diagram, P INC is the incident power at the energy harvester.P REC is the input power of the bridgeless rectification circuit, after the losses due to the energy harvester connector is subtracted from P INC .Typically, when integrating a radio frequency component with passive devices, an impedance mismatch between them will occur, and this contributes to some of the incident power is reflected.The reflected power is denoted as P REF .The power processing circuit consists of a bridgeless rectification circuit and a push-pull circuit.The function of the circuit is to process the received instantaneous power before the power is transferred to the PMU.The bridgeless rectification circuit and the push-pull circuit function are for generating a control signal for the boosting operation of the power processing circuit.The power needed to activate the push-pull circuitry is labelled as P Control .P Loss is the power lost during the proposed circuit operation which is from the microcontroller and circuit themselves.The output power of the power processing circuit is labelled as, P OUT , where it uses the input power of the PMU.The PMU monitors and manages the output power of the circuit before storing it in an energy storage device.

The Schematic Circuit
The schematic circuit of the general block diagram is depicted in Figure 2.For the bridgeless rectification circuit, L1, L2, and C1 are the parameters of a matching LCL network.L3 is an additional boost component that functions together with L1, L2, and C1.D1 and D2 are diodes for rectification and additional to the two branches.The output filter capacitor of the bridgeless rectifier is C2.The DC voltage level of C2 is the input voltage of the push-pull circuit.The inductor L4 is the inductor used for the power processing circuit-boosting operation.As illustrated in the figure the two switches M1 and M4 are used to control a shunt connection to the common terminal.Both switches are turned to ON and OFF synchronously, and the timing depends on the value of R3 and C5.Diode D4 is turned ON and OFF with regards to the alternating push-pull signal.The push-pull circuit is an arrangement of L5, L6, M2, M3, C3, C4, R1, and R2.Diode D3 maintains the direction of the current flow to the filter capacitor C6.The power management unit and the energy storage components of the proposed system are represented as RPMU and CSTORE.

The Schematic Circuit
The schematic circuit of the general block diagram is depicted in Figure 2.For the bridgeless rectification circuit, L 1 , L 2 , and C 1 are the parameters of a matching LCL network.

The Schematic Circuit
The schematic circuit of the general block diagram is depicted in Figure 2.For the bridgeless rectification circuit, L1, L2, and C1 are the parameters of a matching LCL network.L3 is an additional boost component that functions together with L1, L2, and C1.D1 and D2 are diodes for rectification and additional to the two branches.The output filter capacitor of the bridgeless rectifier is C2.The DC voltage level of C2 is the input voltage of the push-pull circuit.The inductor L4 is the inductor used for the power processing circuit-boosting operation.As illustrated in the figure the two switches M1 and M4 are used to control a shunt connection to the common terminal.Both switches are turned to ON and OFF synchronously, and the timing depends on the value of R3 and C5.Diode D4 is turned ON and OFF with regards to the alternating push-pull signal.The push-pull circuit is an arrangement of L5, L6, M2, M3, C3, C4, R1, and R2.Diode D3 maintains the direction of the current flow to the filter capacitor C6.The power management unit and the energy storage components of the proposed system are represented as RPMU and CSTORE.

The Equivalent Circuit
An equivalent circuit simplifying the schematic circuit is presented in Figure 3. Here, the receiving antenna is represented by an AC source with an internal resistance R g .V in is the input voltage of the matching circuit, V rf is the input voltage of the rectifier/switching circuit, and V dc is the direct current voltage across C 2 .V out is the voltage measured at C 7 .Z in is the input impedance looking from the receiving antenna, and Z rf is the rectifier/switching input impedance.The impedance of the push-pull circuit is denoted as Z pp .The passive component in the equivalent circuit is transformed into complex impedances for simplifying the analysis as shown in Figure 4.At all input cycles, it is assumed that the diodes are acting as an ideal switch and the matching circuit is lossless.

The Equivalent Circuit
An equivalent circuit simplifying the schematic circuit is presented in Figure 3. Here, the receiving antenna is represented by an AC source with an internal resistance Rg.Vin is the input voltage of the matching circuit, Vrf is the input voltage of the rectifier/switching circuit, and Vdc is the direct current voltage across C2.Vout is the voltage measured at C7. Zin is the input impedance looking from the receiving antenna, and Zrf is the rectifier/switching input impedance.The impedance of the push-pull circuit is denoted as Zpp.The passive component in the equivalent circuit is transformed into complex impedances for simplifying the analysis as shown in Figure 4.At all input cycles, it is assumed that the diodes are acting as an ideal switch and the matching circuit is lossless.The input power of the circuit Pin can be calculated by where Yin = 1/Zin and ℜ{ } stands for the real part of complex variable Χ and Vin as shows in Figure 4.By applying Kirchhoff's voltage and current laws, Vac − IRg = Vin = I/Yin, where I is the current flowing through Rg, then Equation (1) can be represented as The output power of the rectenna or switching circuit is given by The rectifier and the filter capacitor C 2 are combined as a single load admittance Y R = G L + jB L .

The Equivalent Circuit
An equivalent circuit simplifying the schematic circuit is presented in Figure 3. Here, the receiving antenna is represented by an AC source with an internal resistance Rg.Vin is the input voltage of the matching circuit, Vrf is the input voltage of the rectifier/switching circuit, and Vdc is the direct current voltage across C2.Vout is the voltage measured at C7. Zin is the input impedance looking from the receiving antenna, and Zrf is the rectifier/switching input impedance.The impedance of the push-pull circuit is denoted as Zpp.The passive component in the equivalent circuit is transformed into complex impedances for simplifying the analysis as shown in Figure 4.At all input cycles, it is assumed that the diodes are acting as an ideal switch and the matching circuit is lossless.The rectifier and the filter capacitor C2 are combined as a single load admittance YR = GL + jBL.The input power of the circuit Pin can be calculated by where Yin = 1/Zin and ℜ{ } stands for the real part of complex variable Χ and Vin as shows in Figure 4.By applying Kirchhoff's voltage and current laws, Vac − IRg = Vin = I/Yin, where I is the current flowing through Rg, then Equation (1) can be represented as The output power of the rectenna or switching circuit is given by
The input power of the circuit P in can be calculated by where Y in = 1/Z in and {x} stands for the real part of complex variable X and V in as shows in Figure 4.By applying Kirchhoff's voltage and current laws, V ac − I Rg = V in = I/Y in , where I is the current flowing through R g , then Equation (1) can be represented as The output power of the rectenna or switching circuit is given by where v rf is as indicated in Figure 4, and Y L is the admittance as seen at the input of the rectifier/switching circuit.

Matched and Unmatched Antenna-Rectifier Circuit
The incident power dictates the output voltage of the matching circuit at the receiving antenna and the input impedance of the rectifying circuit.The two different matching conditions are considered; the conditions are when the antenna-rectifier is matched, and another condition is when the antenna-rectifier is unmatched.For the matched condition, the matching network as shown in Figure 4 is considered.To make sure the matching circuit conjugately matches the antenna to the rectifying circuit, the input impedance of the matching circuit needs to be equal to the antenna impedance (Z in = R g ) or Y in R g = 1.Since the matching circuit is assumed lossless, the output power is assumed to be equal to the input power, P out = P in .The antenna-rectifying voltage gain can be written as From Figure 4, the input impedance Z in for the antenna-rectifier matched condition can be calculated by For the input impedance to be equal to R g , the following two conditions must be applied which are: The real part of the input admittance is given by The circuit voltage gain for the antenna-rectifier matched condition is given by where ((B 1 + B L ))/G L is the quality factor at the output of the matching circuit.As defined in (6), the rectifier/switching circuit defines parameter G L and B L .By proper choice of B 1 , the output voltage can be decided, and the value of R g and X 1 are calculated using (9).Indirectly, it is assumed that v ac and R g are chosen individually.Moreover, these two values are interrelated through the power available from the harvesting antenna, P inc .
To calculate the output voltage at the end of the matching circuit, (6) and ( 9) are substituted into (10) to give the value of; From (10), the voltage at the input of the rectifier/switching is consequently emitted by the available power from the harvesting antenna and the real part of the input admittance of the rectifier/switching circuit.Therefore, to maximise v rf , the real admittance of the rectifier/switching circuit needs to be as low as possible.For the condition when the impedance of the harvesting antenna and the rectifier circuit is unmatched, this gives Y in R g = 1 and where The matching circuit output voltage, v rf , at this condition is written as The output voltage of the matching circuit is identical to the output voltage for the matched situation multiplied by a multiplicative factor.This factor is equal to 1 for the case when the value of G in = 1/R g and B in = 0 (matched condition) is smaller than 1 for all situations.Hence, for the voltage to reach a maximum, the harvesting antenna should be impedance matched.

Rectifier Circuit Impedance Analysis
For the bridgeless rectification, Schottky diode is preferred as the component for the rectification operation.The diode has a very fast switching action and activates with a low forward bias voltage.The illustration in Figure 5 shows the diode in a series configuration with a source V ac and load.The source has an internal resistance R g , and the load consists of a resistor R L in parallel with a capacitor C L .
Appl.Sci.2017, 7, 827 6 of 18 where The matching circuit output voltage, vrf, at this condition is written as The output voltage of the matching circuit is identical to the output voltage for the matched situation multiplied by a multiplicative factor.This factor is equal to 1 for the case when the value of = 1 ⁄ and = 0 (matched condition) is smaller than 1 for all situations.Hence, for the voltage to reach a maximum, the harvesting antenna should be impedance matched.

Rectifier Circuit Impedance Analysis
For the bridgeless rectification, Schottky diode is preferred as the component for the rectification operation.The diode has a very fast switching action and activates with a low forward bias voltage.The illustration in Figure 5 shows the diode in a series configuration with a source Vac and load.The source has an internal resistance Rg, and the load consists of a resistor RL in parallel with a capacitor CL.
A series configuration with a source and load of a diode circuit model.
The rectifier input impedance can be calculated by applying circuit analysis for the given diode model employing commercially available software.For the analysis, the value of the load capacitor, CL is assumed to be sufficiently large ≥ 0.1 μF for the frequency range between 0.1 GHz to 2.5 GHz.Hence, the load is assumed to be in short circuit condition.Table 2 lists different diode parameters that could be uses for simulating the diode performance for some commercially available Schottky diodes.Parameter n is the emission coefficient of the diode.The type of Schottky diode used in the proposed circuit is SMS7621 from SKYWORKS (Woburn, MA, USA).As labelled in Figure 4, the input voltage Vac follows from the relation between generator voltage and available incident power Pinc.The input impedance for a different commercially Schottky diode is depicted in Figure 6.In the figure, the simulation result of the real and imaginary parts of the input impedance as a function of available power Pinc for the frequency of 2.45 GHz is illustrated.The figure demonstrates that the input impedance satisfies the conditions for high sensitivity and RF-to-DC The rectifier input impedance can be calculated by applying circuit analysis for the given diode model employing commercially available software.For the analysis, the value of the load capacitor, C L is assumed to be sufficiently large (C L ≥ 0.1 µF) for the frequency range between 0.1 GHz to 2.5 GHz.Hence, the load is assumed to be in short circuit condition.Table 2 lists different diode parameters that could be uses for simulating the diode performance for some commercially available Schottky diodes.Parameter n is the emission coefficient of the diode.The type of Schottky diode used in the proposed circuit is SMS7621 from SKYWORKS (Woburn, MA, USA).As labelled in Figure 4, the input voltage V ac follows from the relation between generator voltage and available incident power P inc .The input impedance for a different commercially Schottky diode is depicted in Figure 6.In the figure, the simulation result of the real and imaginary parts of the input impedance as a function of available power P inc for the frequency of 2.45 GHz is illustrated.The figure demonstrates that the input impedance satisfies the conditions for high sensitivity and RF-to-DC power conversion as required by Equation (11).From the simulation, it has been found that the real part of the input impedance for the selected Schottky diode is low, and the imaginary part absolute value for all types of diodes is high except for the HBAT5400.The highest imaginary part value shown in the figure is for the SMS7621 diode.The input impedance of the rectifier/switching circuit is also simulated with different frequencies, as seen in Figure 7 the impedance real value is at a constant value throughout the simulated frequencies at 6.4 Ohm.The imaginary value is gradually increasing as the frequencies move closer to 3 GHz.In short, the simulation results demonstrate that the rectifier/switching circuit satisfies the requirements for obtaining a high sensitivity circuit.
Appl.Sci.2017, 7, 827 7 of 18 power conversion as required by Equation (11).From the simulation, it has been found that the real part of the input impedance for the selected Schottky diode is low, and the imaginary part absolute value for all types of diodes is high except for the HBAT5400.The highest imaginary part value shown in the figure is for the SMS7621 diode.The input impedance of the rectifier/switching circuit is also simulated with different frequencies, as seen in Figure 7 the impedance real value is at a constant value throughout the simulated frequencies at 6.4 Ohm.The imaginary value is gradually increasing as the frequencies move closer to 3 GHz.In short, the simulation results demonstrate that the rectifier/switching circuit satisfies the requirements for obtaining a high sensitivity circuit.

The Rectifying and Boost Circuit Characteristics
A mathematical approach such as Runge-Kutta (RK) has been used to analyse the DC behaviour of the circuit as in Figure 4, and the complete analysis is shown in [2].A comparative analysis could have also been applied in analysing the diode behaviour [13].In this work, the calculation of the DC  power conversion as required by Equation (11).From the simulation, it has been found that the real part of the input impedance for the selected Schottky diode is low, and the imaginary part absolute value for all types of diodes is high except for the HBAT5400.The highest imaginary part value shown in the figure is for the SMS7621 diode.The input impedance of the rectifier/switching circuit is also simulated with different frequencies, as seen in Figure 7 the impedance real value is at a constant value throughout the simulated frequencies at 6.4 Ohm.The imaginary value is gradually increasing as the frequencies move closer to 3 GHz.In short, the simulation results demonstrate that the rectifier/switching circuit satisfies the requirements for obtaining a high sensitivity circuit.

The Rectifying and Boost Circuit Characteristics
A mathematical approach such as Runge-Kutta (RK) has been used to analyse the DC behaviour of the circuit as in Figure 4, and the complete analysis is shown in [2].A comparative analysis could have also been applied in analysing the diode behaviour [13].In this work, the calculation of the DC

The Rectifying and Boost Circuit Characteristics
A mathematical approach such as Runge-Kutta (RK) has been used to analyse the DC behaviour of the circuit as in Figure 4, and the complete analysis is shown in [2].A comparative analysis could have also been applied in analysing the diode behaviour [13].In this work, the calculation of the DC output voltage after the rectifier circuit, v rf is done using Equation (10).The bridgeless rectification has been developed and the output voltage of the rectification circuit with the filter capacitor value of 10 µF is measured and reported in Figure 8.
A boost converter is accomplished in the proposed power processing circuit by switching a reactive component.Two n-channel MOSFET (NMOS) devices are used as the switches.Triggering the devices ON and OFF is done by a periodic signal generated by the push-pull circuit.When both switches are turned ON a current is flowing through the inductance L 4 .The output voltage vout is identical to v rf − v Rb where v Rb is the voltage drop due to the internal push-pull resistance.The diode is unbiased, and the output voltage vout is the voltage over the capacitor C 7 .When the switch is turned OFF, the voltage, v L4 is developed to keep the current flowing.The diode is now forward biased and the voltage v out = v rf − v Rb + v L4 is transferred to the capacitor.As the switch is turned ON again, the diode is unbiased.A resistive load is draining the charge from C 7 .Upon opening the switch, C 7 is recharged again.
Appl.Sci.2017, 7, 827 8 of 18 output voltage after the rectifier circuit, vrf is done using Equation (10).The bridgeless rectification has been developed and the output voltage of the rectification circuit with the filter capacitor value of 10 µF is measured and reported in Figure 8.
A boost converter is accomplished in the proposed power processing circuit by switching a reactive component.Two n-channel MOSFET (NMOS) devices are used as the switches.Triggering the devices ON and OFF is done by a periodic signal generated by the push-pull circuit.When both switches are turned ON a current is flowing through the inductance L4.The output voltage vout is identical to vrf − vRb where vRb is the voltage drop due to the internal push-pull resistance.The diode is unbiased, and the output voltage vout is the voltage over the capacitor C7.When the switch is turned OFF, the voltage, vL4 is developed to keep the current flowing.The diode is now forward biased and the voltage vout = vrf − vRb + vL4 is transferred to the capacitor.As the switch is turned ON again, the diode is unbiased.A resistive load is draining the charge from C7. Upon opening the switch, C7 is recharged again.

Simulation Results of the Power Processing Circuit
There are three main points concerning the proposed power processing circuit that need to be investigated.These points highlight the voltage characteristics of the proposed power processing circuit.The three different points are the voltage across capacitor C2, the differential voltage at the positive terminal of diode D3 and the output voltage of the proposed circuit which is the voltage across C7.The signal characteristics of the three stated points can be found using circuit simulation.LT Spice software is utilised for investigation purposes.The spice parameters of the Schottky diode, SMS7621, and the NMOS switch, ALD210800A are obtained from the manufacturer datasheet.

Simulation Results of the Power Processing Circuit
There are three main points concerning the proposed power processing circuit that need to be investigated.These points highlight the voltage characteristics of the proposed power processing circuit.The three different points are the voltage across capacitor C 2 , the differential voltage at the positive terminal of diode D 3 and the output voltage of the proposed circuit which is the voltage across C 7 .The signal characteristics of the three stated points can be found using circuit simulation.LT Spice software is utilised for investigation purposes.The spice parameters of the Schottky diode, SMS7621, and the NMOS switch, ALD210800A are obtained from the manufacturer datasheet.
In the simulation, the harvesting antenna is assumed as an AC source.The AC source continuously supplies the power processing circuit with a sinusoidal input signal.The push-pull circuit operation is relating to the signals of the voltage across V C3 and V C4 which the driving signal for the switching MOSFET, M 2 and M 3 .The inverting signal is measured at V C6 .Figure 9 illustrates the signals for the stated components.As depicted in the figure, the instantaneous signal at V C6 is bigger than the V AC which is normally less than 10 mV.The higher the AC signal contributes to faster charging time for the storage component.
Appl.Sci.2017, 7, 827 9 of 18 In the simulation, the harvesting antenna is assumed as an AC source.The AC source continuously supplies the power processing circuit with a sinusoidal input signal.The push-pull circuit operation is relating to the signals of the voltage across VC3 and VC4 which the driving signal for the switching MOSFET, M2 and M3.The inverting signal is measured at VC6. Figure 9 illustrates the signals for the stated components.As depicted in the figure, the instantaneous signal at VC6 is bigger than the VAC which is normally less than 10 mV.The higher the AC signal contributes to faster charging time for the storage component.There are four different alternating input voltages were tested as the input signal for the proposed circuit and the values are 2 mVp-p, 6 mVp-p, 20 mVp-p and 35 mVp-p.For all the input voltages, the frequency is at 2.45 GHz.Each value represents an input power of −50 dBm, −40 dBm, −30 dBm and −25 dBm, respectively, being supplied to a 50 Ohm impedance input terminal.As illustrated in Figure 10, there is an initialization time for the power processing circuit to start the circuit boosting operation.The initialization time occurred because the stored energy in C2 is not enough to activate the boosting circuit.However, when the stored energy in C2 is sufficient, the boost circuit will start its function.In practical, it is expected that the initialization time will be longer since this incident signal is low and in burst mode.However, with respect to time, the energy level stored in C2 will reach the required level for boost circuit operational.
The boosting signal is represented by the simulation result of VD3.The circuit initialization time becomes shorter when the input voltage is bigger.As can be seen in Figure 10a,b, the time needed for the boost circuit to start functioning is approximately 0.8 ms, as the input voltage is increased to 6 mVp-p, and the time required for initialization less, which is approximately 0.25 ms.The initialization became much faster to approximately 0.1 ms when the input voltage is bigger than 20 mVp-p.The reading for VC2 and VC7 is not much difference especially for an input voltage of 2 mVp-p and 6 mVpp.However, for higher input voltages, 20 mVp-p, and 35 mVp-p, there is a significant result obtained.The power processing circuit boosted the value of VC2 close to 3 times of the input voltage as shown in Figure 10c,d.From the simulation, it has been demonstrated that the boost circuit is functioning as expected.For a small input voltage 1 mVp (−50 dBm), the boost circuit of the proposed power processing circuit can generate 6 times bigger than the input voltage of the switching diode D3.The signal boost factor is close to 6.5 times.On average, for all the selected input voltages, the peak voltage signal measured at D3 is approximately 5.5 times greater than peak input voltage at C2.This condition shows that the power processing circuit can be used even when the input voltage value supplied is small.There are four different alternating input voltages were tested as the input signal for the proposed circuit and the values are 2 mVp-p, 6 mVp-p, 20 mVp-p and 35 mVp-p.For all the input voltages, the frequency is at 2.45 GHz.Each value represents an input power of −50 dBm, −40 dBm, −30 dBm and −25 dBm, respectively, being supplied to a 50 Ohm impedance input terminal.As illustrated in Figure 10, there is an initialization time for the power processing circuit to start the circuit boosting operation.The initialization time occurred because the stored energy in C 2 is not enough to activate the boosting circuit.However, when the stored energy in C 2 is sufficient, the boost circuit will start its function.In practical, it is expected that the initialization time will be longer since this incident signal is low and in burst mode.However, with respect to time, the energy level stored in C 2 will reach the required level for boost circuit operational.
The boosting signal is represented by the simulation result of V D3 .The circuit initialization time becomes shorter when the input voltage is bigger.As can be seen in Figure 10a,b, the time needed for the boost circuit to start functioning is approximately 0.8 ms, as the input voltage is increased to 6 mVp-p, and the time required for initialization less, which is approximately 0.25 ms.The initialization became much faster to approximately 0.1 ms when the input voltage is bigger than 20 mVp-p.The reading for V C2 and V C7 is not much difference especially for an input voltage of 2 mVp-p and 6 mVp-p.However, for higher input voltages, 20 mVp-p, and 35 mVp-p, there is a significant result obtained.The power processing circuit boosted the value of V C2 close to 3 times of the input voltage as shown in Figure 10c,d.From the simulation, it has been demonstrated that the boost circuit is functioning as expected.For a small input voltage 1 mVp (−50 dBm), the boost circuit of the proposed power processing circuit can generate 6 times bigger than the input voltage of the switching diode D 3 .The signal boost factor is close to 6.5 times.On average, for all the selected input voltages, the peak voltage signal measured at D 3 is approximately 5.5 times greater than peak input voltage at C 2 .This condition shows that the power processing circuit can be used even when the input voltage value supplied is small.

The Proposed Power Processing Circuit Performance
The matching circuit performance of the proposed power processing circuit is demonstrated by measuring the return loss at the input terminal of the circuit.A vector network analyser measured the return loss, and the result is depicted in Figure 11.As reported in the figure, the lowest return loss is approximate at −17.5 dB, which is at 2.4 GHz.At 2.45 GHz, the return loss is at −16.5 db.The proposed power processing circuit is fabricated, and the component values of the proposed power processing circuit are listed in Table 3.

The Proposed Power Processing Circuit Performance
The matching circuit performance of the proposed power processing circuit is demonstrated by measuring the return loss at the input terminal of the circuit.A vector network analyser measured the return loss, and the result is depicted in Figure 11.As reported in the figure, the lowest return loss is approximate at −17.5 dB, which is at 2.4 GHz.At 2.45 GHz, the return loss is at −16.5 db.

The Proposed Power Processing Circuit Performance
The matching circuit performance of the proposed power processing circuit is demonstrated by measuring the return loss at the input terminal of the circuit.A vector network analyser measured the return loss, and the result is depicted in Figure 11.As reported in the figure, the lowest return loss is approximate at −17.5 dB, which is at 2.4 GHz.At 2.45 GHz, the return loss is at −16.5 db.The proposed power processing circuit is fabricated, and the component values of the proposed power processing circuit are listed in Table 3.The proposed power processing circuit is fabricated, and the component values of the proposed power processing circuit are listed in Table 3.The developed power processing circuit is tested with a varying input voltage and power which is injected by an RF signal generator.This step is taken to demonstrate that the proposed power processing circuit can rectify instantaneous input signal, accordingly.For this experiment, a load resistor and a capacitor are connected to the output terminal of the circuit, and the value is 10 kΩ and 0.1 µF, respectively.The reading obtained from the experiment is reported in Figure 12, it is found that the circuit output voltage level reached 1.8 V and 35 mV, for an input of 620 mVp and −20 dBm, respectively.The developed power processing circuit is tested with a varying input voltage and power which is injected by an RF signal generator.This step is taken to demonstrate that the proposed power processing circuit can rectify instantaneous input signal, accordingly.For this experiment, a load resistor and a capacitor are connected to the output terminal of the circuit, and the value is 10 kΩ and 0.1 µF, respectively.The reading obtained from the experiment is reported in Figure 12, it is found that the circuit output voltage level reached 1.8 V and 35 mV, for an input of 620 mVp and −20 dBm, respectively.The capacitance of CSTORE is changed to 0.22 F to investigate the time required for the voltage across the capacitor to reach a constant level.The capacitance value is the lowest supercapacitor commercially available in the market.The supercapacitor is from Copper-Bussmann, and the equivalent series resistance (ESR) of the capacitor is less than 2 Ω.A signal generator supplies five different input powers at 2.45 GHz, and the voltage across CSTORE is recorded using the data logger.The measurement results are illustrated in Figure 13.From the measured value, it was noticed that the charging time could be divided into four separate phases as highlighted in Figure 13a.The period for each step is approximately ø1 = 0 s < t < 3600 s, ø2 = 3600 s < t < 5400 s, ø3 = 5400 s < t < 7200 s and ø4 = 7200 s < t < 10800 s.The voltage across CSTORE increased linearly during ø1 and steadily increased for ø2 and ø3.For the period of ø4 the voltage across the capacitor is constant.The current flow through the capacitor can be calculated by differentiating the measured voltage with respect to time ⁄ , then multiplying by the capacitance of CSTORE, and the result is shown in Figure 13b.The current flow through the capacitor is the highest during ø1 for all levels of input power, and at the lowest towards ø4 as the capacitor starts to behave in a saturation condition.By multiplying the voltage and current, the amount of power absorbed by CSTORE is depicted in Figure 13c.The energy stored in the capacitor is estimated by using = 1 2 ⁄ , and the value is reported in Figure 13d.The RF-to-DC conversion efficiency for the proposed system can be plotted as a function of DC output power over the radio frequency input power, and the result is illustrated in Figure 14.From the figure, it is noticed that the The capacitance of C STORE is changed to 0.22 F to investigate the time required for the voltage across the capacitor to reach a constant level.The capacitance value is the lowest supercapacitor commercially available in the market.The supercapacitor is from Copper-Bussmann, and the equivalent series resistance (ESR) of the capacitor is less than 2 Ω.A signal generator supplies five different input powers at 2.45 GHz, and the voltage across C STORE is recorded using the data logger.The measurement results are illustrated in Figure 13.From the measured value, it was noticed that the charging time could be divided into four separate phases as highlighted in Figure 13a.The period for each step is approximately ø 1 = 0 s < t < 3600 s, ø 2 = 3600 s < t < 5400 s, ø 3 = 5400 s < t < 7200 s and ø 4 = 7200 s < t < 10800 s.The voltage across C STORE increased linearly during ø 1 and steadily increased for ø 2 and ø 3 .For the period of ø 4 the voltage across the capacitor is constant.The current flow through the capacitor can be calculated by differentiating the measured voltage with respect to time (d v /d t ), then multiplying by the capacitance of C STORE , and the result is shown in Figure 13b.The current flow through the capacitor is the highest during ø 1 for all levels of input power, and at the lowest towards ø 4 as the capacitor starts to behave in a saturation condition.By multiplying the voltage and current, the amount of power absorbed by C STORE is depicted in Figure 13c.The energy stored in the capacitor is estimated by using E = 1/2CV 2 , and the value is reported in Figure 13d.The RF-to-DC conversion efficiency for the proposed system can be plotted as a function of DC output power over the radio frequency input power, and the result is illustrated in Figure 14.From the figure, it is noticed that the proposed system gives an efficiency of more than 1% for an input power of −50 dBm, −40 dBm, −30 dBm and 0 dBm.However, for an input power of −20 dBm and −10 dBm the efficiency is less than 1%.The RF-to-DC conversion efficiency values show that the proposed system is suitable for working with low and medium input power.This condition is not much different with another type of harvesting systems which are normally optimised to work with low input power.
Appl.Sci.2017, 7, 827 12 of 18 proposed system gives an efficiency of more than 1% for an input power of −50 dBm, −40 dBm, −30 dBm and 0 dBm.However, for an input power of −20 dBm and −10 dBm the efficiency is less than 1%.The RF-to-DC conversion efficiency values show that the proposed system is suitable for working with low and medium input power.This condition is not much different with another type of harvesting systems which are normally optimised to work with low input power.proposed system gives an efficiency of more than 1% for an input power of −50 dBm, −40 dBm, −30 dBm and 0 dBm.However, for an input power of −20 dBm and −10 dBm the efficiency is less than 1%.The RF-to-DC conversion efficiency values show that the proposed system is suitable for working with low and medium input power.This condition is not much different with another type of harvesting systems which are normally optimised to work with low input power.

Actual Experimentation of the RFEHS
In this section, the performance of the proposed power processing circuit experimented in a real environment is highlighted.In the experiment, the input terminal of the proposed power processing circuit is connected to a 50-Ohm antenna, where the antenna is designed to operate at 2.45 GHz.The energy harvester is a printed co-planar waveguide antenna.The antenna is attached to the input of the circuit through a Sub-Miniature Version A (SMA) connector.The SMA connector impedance is 50 Ohm.The actual figure of the energy harvester is depicted in Figure 15.The detailed explanation of the antenna and its performance has been reported in [14].

Actual Experimentation of the RFEHS
In this section, the performance of the proposed power processing circuit experimented in a real environment is highlighted.In the experiment, the input terminal of the proposed power processing circuit is connected to a 50-Ohm antenna, where the antenna is designed to operate at 2.45 GHz.The energy harvester is a printed co-planar waveguide antenna.The antenna is attached to the input of the circuit through a Sub-Miniature Version A (SMA) connector.The SMA connector impedance is 50 Ohm.The actual figure of the energy harvester is depicted in Figure 15.The detailed explanation of the antenna and its performance has been reported in [14].The impedance losses when the power processing circuit is attached to the harvesting antenna is another system characteristic which needs to be highlighted.The effect on impedance losses can be seen by measuring the return loss with and without the power processing circuit attached to the antenna.Figure 16 illustrates the measured return loss, S11 for both conditions.As can be seen from the figure, the impedance losses are small, and the value is above the equator of the Smith chart, reflecting the harvesting antenna and the proposed power processing circuit inductive characteristics.A PMU is attached to the output terminal of the proposed power processing circuit as shown in Figure 17.On the PMU, a supercapacitor is connected to the energy storage component.The arrangement of the harvesting antenna, the proposed power processing circuit and a PMU, made a The impedance losses when the power processing circuit is attached to the harvesting antenna is another system characteristic which needs to be highlighted.The effect on impedance losses can be seen by measuring the return loss with and without the power processing circuit attached to the antenna.Figure 16 illustrates the measured return loss, S 11 for both conditions.As can be seen from the figure, the impedance losses are small, and the value is above the equator of the Smith chart, reflecting the harvesting antenna and the proposed power processing circuit inductive characteristics.

Actual Experimentation of the RFEHS
In this section, the performance of the proposed power processing circuit experimented in a real environment is highlighted.In the experiment, the input terminal of the proposed power processing circuit is connected to a 50-Ohm antenna, where the antenna is designed to operate at 2.45 GHz.The energy harvester is a printed co-planar waveguide antenna.The antenna is attached to the input of the circuit through a Sub-Miniature Version A (SMA) connector.The SMA connector impedance is 50 Ohm.The actual figure of the energy harvester is depicted in Figure 15.The detailed explanation of the antenna and its performance has been reported in [14].The impedance losses when the power processing circuit is attached to the harvesting antenna is another system characteristic which needs to be highlighted.The effect on impedance losses can be seen by measuring the return loss with and without the power processing circuit attached to the antenna.Figure 16 illustrates the measured return loss, S11 for both conditions.As can be seen from the figure, the impedance losses are small, and the value is above the equator of the Smith chart, reflecting the harvesting antenna and the proposed power processing circuit inductive characteristics.A PMU is attached to the output terminal of the proposed power processing circuit as shown in Figure 17.On the PMU, a supercapacitor is connected to the energy storage component.The arrangement of the harvesting antenna, the proposed power processing circuit and a PMU, made a A PMU is attached to the output terminal of the proposed power processing circuit as shown in Figure 17.On the PMU, a supercapacitor is connected to the energy storage component.The arrangement of the harvesting antenna, the proposed power processing circuit and a PMU, made a complete RF energy harvesting system.During the measurement period, the radio frequency signal strength inside the selected indoor area is monitored using Wi-Fi analyser software that is installed in a notebook and using a spectrum analyser connected to a similar antenna of the energy harvester for the proposed system.It has been found that the signal strength measured using both measurement devices are in good agreement.The measured signal strength result is illustrated in Figure 18.It has been found that during the test period, the transmitted signal is low.However, even the incident power is low, there are multiple numbers of incident power received at the energy harvester, continuously, and the amount is sufficient for the operation of the proposed harvesting system.During the measurement periods, it has been found that four 2.4 GHz Wi-Fi access points are covering the selected area.
complete RF energy harvesting system.During the measurement period, the radio frequency signal strength inside the selected indoor area is monitored using Wi-Fi analyser software that is installed in a notebook and using a spectrum analyser connected to a similar antenna of the energy harvester for the proposed system.It has been found that the signal strength measured using both measurement devices are in good agreement.The measured signal strength result is illustrated in Figure 18.It has been found that during the test period, the transmitted signal is low.However, even the incident power is low, there are multiple numbers of incident power received at the energy harvester, continuously, and the amount is sufficient for the operation of the proposed harvesting system.During the measurement periods, it has been found that four 2.4 GHz Wi-Fi access points are covering the selected area.As can be seen in Figure 18, the maximum peak of the signal strength is −55 dBm, and the lowest is between −85 dBm.The available power that could be transferred from the antenna to the matching circuit can be calculated by a function of PINC = Pmeasured + 30 dBm.For an example, let us assume the transmitted power (PTx) for Wi-Fi transmitter is 0 dBm, and the average power received at the antenna is approximate −60 dBm.The losses introduced during the power transmission can be calculated by substituting the transmitted power with the average received power which gives the estimated losses to be 0 dBm-(−60 dBm) = 60 dBm.Then, the loss introduced by antennae and connector can be complete RF energy harvesting system.During the measurement period, the radio frequency signal strength inside the selected indoor area is monitored using Wi-Fi analyser software that is installed in a notebook and using a spectrum analyser connected to a similar antenna of the energy harvester for the proposed system.It has been found that the signal strength measured using both measurement devices are in good agreement.The measured signal strength result is illustrated in Figure 18.It has been found that during the test period, the transmitted signal is low.However, even the incident power is low, there are multiple numbers of incident power received at the energy harvester, continuously, and the amount is sufficient for the operation of the proposed harvesting system.During the measurement periods, it has been found that four 2.4 GHz Wi-Fi access points are covering the selected area.As can be seen in Figure 18, the maximum peak of the signal strength is −55 dBm, and the lowest is between −85 dBm.The available power that could be transferred from the antenna to the matching circuit can be calculated by a function of PINC = Pmeasured + 30 dBm.For an example, let us assume the transmitted power (PTx) for Wi-Fi transmitter is 0 dBm, and the average power received at the antenna is approximate −60 dBm.The losses introduced during the power transmission can be calculated by substituting the transmitted power with the average received power which gives the estimated losses to be 0 dBm-(−60 dBm) = 60 dBm.Then, the loss introduced by antennae and connector can be As can be seen in Figure 18, the maximum peak of the signal strength is −55 dBm, and the lowest is between −85 dBm.The available power that could be transferred from the antenna to the matching circuit can be calculated by a function of P INC = P measured + 30 dBm.For an example, let us assume the transmitted power (P Tx ) for Wi-Fi transmitter is 0 dBm, and the average power received at the antenna is approximate −60 dBm.The losses introduced during the power transmission can be calculated by substituting the transmitted power with the average received power which gives the estimated losses to be 0 dBm-(−60 dBm) = 60 dBm.Then, the loss introduced by antennae and connector can be calculated which is 60 dBm/2 = 30 dBm.Hence, P INC for the level of the signal is −30 dBm.In practical, as shown in Figure 18, if the lowest measured signal strength is −85 dBm, the available power that is transferred to the matching circuit is at −55 dBm.
The voltage across the 0.22 F super capacitor connected to the output of the PMU is measured.The value is recorded using a data logging instrument from National Instrument known as ELVIS II.For the actual experimentation, the targeted voltage across C STORE is 1 V.The time taken for the voltage to reach that level is approximately 20 h.The harvesting time approximation can be calculated by: where T is the time in an hour, and i c is approximately close to 3 µA which also has been discussed in [14].From the recorded results, the current through the capacitor, the power absorbed and the energy stored in the capacitor are calculated and reported in Figure 19.Comparison with others finding as listed in Table 4 is labeled in the figure .calculated which is 60 dBm/2 = 30 dBm.Hence, PINC for the level of the signal is −30 dBm.In practical, as shown in Figure 18, if the lowest measured signal strength is −85 dBm, the available power that is transferred to the matching circuit is at −55 dBm.The voltage across the 0.22 F super capacitor connected to the output of the PMU is measured.The value is recorded using a data logging instrument from National Instrument known as ELVIS II.For the actual experimentation, the targeted voltage across CSTORE is 1 V.The time taken for the voltage to reach that level is approximately 20 h.The harvesting time approximation can be calculated by: where T is the time in an hour, and ic is approximately close to 3 µA which also has been discussed in [14].From the recorded results, the current through the capacitor, the power absorbed and the energy stored in the capacitor are calculated and reported in Figure 19.Comparison with others finding as listed in Table 4 is labeled in the figure.The proposed system needs less than five hours to gain the minimum power requirements for all the listed sensors.The RF to DC conversion efficiency of the system is calculated by dividing the output power, Pstore, of the storage capacitor by the available input power of the matching circuit, PRF.However, since the value of Pstore increases over time as calculated, the efficiency of the system is calculated in term of ranges.If the highest signal strength recorded (≈−50 dBm) is assumed to be the dominant incident power to the proposed system over time, that gives the available power to the circuit being close to PINC = (−55 + 30) dBm = −20 dBm or 10 µW.The efficiency of the system is calculated and illustrated in Figure 19b.As shown in the figure, the efficiency of the overall system increased over time and the highest efficiency achieved is close to 30%.The efficiency dropped close to 6% as the voltage across the storage capacitor reached a constant level.As illustrated in Figure 14, the efficiency of the proposed system before the PMU is connected at the end of boost circuit is less than 1% for −20 dBm input power.However, with the addition of the PMU, the efficiency is improved with respect to time.Finally, from all the measurement values, the key features of the proposed RFEHS are listed Table 5.The proposed system needs less than five hours to gain the minimum power requirements for all the listed sensors.The RF to DC conversion efficiency of the system is calculated by dividing the output power, P store , of the storage capacitor by the available input power of the matching circuit, P RF .However, since the value of P store increases over time as calculated, the efficiency of the system is calculated in term of ranges.If the highest signal strength recorded (≈−50 dBm) is assumed to be the dominant incident power to the proposed system over time, that gives the available power to the circuit being close to P INC = (−55 + 30) dBm = −20 dBm or 10 µW.The efficiency of the system is calculated and illustrated in Figure 19b.As shown in the figure, the efficiency of the overall system increased over time and the highest efficiency achieved is close to 30%.The efficiency dropped close to 6% as the voltage across the storage capacitor reached a constant level.As illustrated in Figure 14, the efficiency of the proposed system before the PMU is connected at the end of boost circuit is less than 1% for −20 dBm input power.However, with the addition of the PMU, the efficiency is improved with respect to time.Finally, from all the measurement values, the key features of the proposed RFEHS are listed Table 5.The circuit power consumption P in = 0 dBm 18 nW The circuit equivalent impedance 50 kΩ In indoor environment (RF power density = 0.1 mW/m 2 ) DC output power RF-to-DC conversion efficiency 3 µW 30%

Harvesting System Performance Comparison
The performance of the proposed harvesting system with another previous work is summarized in Table 6.The comparison is made with others RF energy harvesting systems which used input powers approximately −50 dBm to 0 dBm.By comparing the RF-to-DC efficiency of the proposed harvesting system to the stated previous research, work in [19] has the highest efficiency.However, the result was obtained using −10 dBm input power.From the comparison table, it is clearly shown that the proposed RFEHS performs better than the dual or multiband frequencies RF energy harvesting system.The proposed RFEHS also produced a similar performance with other listed research.Moreover, the circuit has operated by using power harvested from non-dedicated RF sources.

Conclusions
This paper presents a method for designing a complete power processing circuit for an indoor RF energy harvesting system.The analytical analysis of the power processing circuit attached to an antenna and a PMU has been conducted based on an equivalent circuit.The impedance matching between the energy harvester, matching circuit and rectifier circuit have been analysed.From the simulation analysis, it has been demonstrated that the selected Schottky diode used in designing the proposed power processing circuit gave the best performance compared to other diodes.The power processing circuit works well with Wi-Fi power typically at −20 dBm, which can even go down to as low as −50 dBm.The overall RF-to-DC power efficiency of 30% is obtained from the proposed energy harvesting system.The final measurement result has demonstrated that the proposed system can charge up a 200 mF supercapacitor in 20 hours, and the stored energy of 0.11 J can be used to drive low power wireless sensors.

Figure 1 .
Figure 1.The general block diagram of the proposed system.

Figure 2 .
Figure 2. The schematic circuit of the proposed system.
L 3 is an additional boost component that functions together with L 1 , L 2 , and C 1 .D 1 and D 2 are diodes for rectification and additional to the two branches.The output filter capacitor of the bridgeless rectifier is C 2 .The DC voltage level of C 2 is the input voltage of the push-pull circuit.The inductor L 4 is the inductor used for the power processing circuit-boosting operation.As illustrated in the figure the two switches M 1 and M 4 are used to control a shunt connection to the common terminal.Both switches are turned to ON and OFF synchronously, and the timing depends on the value of R 3 and C 5 .Diode D 4 is turned ON and OFF with regards to the alternating push-pull signal.The push-pull circuit is an arrangement of L 5 , L 6 , M 2 , M 3 , C 3 , C 4 , R 1 , and R 2 .Diode D 3 maintains the direction of the current flow to the filter capacitor C 6 .The power management unit and the energy storage components of the proposed system are represented as R PMU and C STORE .

Figure 1 .
Figure 1.The general block diagram of the proposed system.

Figure 2 .
Figure 2. The schematic circuit of the proposed system.

Figure 2 .
Figure 2. The schematic circuit of the proposed system.

Figure 3 .
Figure 3.The equivalent circuit.The rectifier and the filter capacitor C2 are combined as a single load admittance YR = GL + jBL.

Figure 5 .
Figure 5.A series configuration with a source and load of a diode circuit model.

Figure 6 .
Figure 6.Radio frequency (RF) input impedance versus Pinc at f = 2.45 GHz for some commercially Schottky diodes.

Figure 7 .
Figure 7.The input impedance of the rectifier/switching circuit versus frequencies.

Figure 6 .
Figure 6.Radio frequency (RF) input impedance versus P inc at f = 2.45 GHz for some commercially Schottky diodes.

Figure 6 .
Figure 6.Radio frequency (RF) input impedance versus Pinc at f = 2.45 GHz for some commercially Schottky diodes.

Figure 7 .
Figure 7.The input impedance of the rectifier/switching circuit versus frequencies.

Figure 7 .
Figure 7.The input impedance of the rectifier/switching circuit versus frequencies.

Figure 8 .
Figure 8.The calculated and measured voltage of the rectification circuit as a function of available power for SMS7621 Schottky diodes at f = 2.45 GHz.Rg = 50 Ω.

Figure 8 .
Figure 8.The calculated and measured voltage of the rectification circuit as a function of available power for SMS7621 Schottky diodes at f = 2.45 GHz.R g = 50 Ω.

Figure 9 .
Figure 9.The signals at VC3, VC4 and VC6 for an input signal of Vac = 3 mV and frequency of 2.45 GHz.

Figure 9 .
Figure 9.The signals at V C3 , V C4 and V C6 for an input signal of V ac = 3 mV and frequency of 2.45 GHz.

Figure 10 .
Figure 10.The simulation result at the three most important testing points for the proposed power processing circuit when VAC is (a) 2 mVp-p, (b) 6 mVp-p, (c) 20 mVp-p and (d) 35 mVp-p.

Figure 10 .
Figure 10.The simulation result at the three most important testing points for the proposed power processing circuit when V AC is (a) 2 mVp-p, (b) 6 mVp-p, (c) 20 mVp-p and (d) 35 mVp-p.

Figure 10 .
Figure 10.The simulation result at the three most important testing points for the proposed power processing circuit when VAC is (a) 2 mVp-p, (b) 6 mVp-p, (c) 20 mVp-p and (d) 35 mVp-p.

Figure 12 .
Figure 12.The measured output voltage versus peak input voltage (a), and input power (b) when R PMU =10 kΩ and C STORE = 0.1 µF.

Figure 13 .
Figure 13.The measurement results of (a) Voltage across CSTORE; (b) Current through CSTORE; (c) Output power and (d) Stored energy.

Figure 14 .
Figure 14.The harvesting antenna and proposed power processing circuit RF-to-DC conversion efficiency versus time.

Figure 13 .
Figure 13.The measurement results of (a) Voltage across C STORE ; (b) Current through C STORE ; (c) Output power and (d) Stored energy.

Figure 13 .
Figure 13.The measurement results of (a) Voltage across CSTORE; (b) Current through CSTORE; (c) Output power and (d) Stored energy.

Figure 14 .
Figure 14.The harvesting antenna and proposed power processing circuit RF-to-DC conversion efficiency versus time.

Figure 14 .
Figure 14.The harvesting antenna and proposed power processing circuit RF-to-DC conversion efficiency versus time.

Figure 16 .
Figure 16.Measured impedance losses of the harvesting antenna without and after attachment of the power processing circuit at 2.45 GHz.

Figure 16 .
Figure 16.Measured impedance losses of the harvesting antenna without and after attachment of the power processing circuit at 2.45 GHz.

Figure 16 .
Figure 16.Measured impedance losses of the harvesting antenna without and after attachment of the power processing circuit at 2.45 GHz.

Figure 17 .
Figure 17.The actual figure of the proposed RF energy harvesting system.

Figure 18 .
Figure 18.Measured 2.45 GHz Wi-Fi signal strength inside the indoor area.

Figure 17 .
Figure 17.The actual figure of the proposed RF energy harvesting system.

Figure 17 .
Figure 17.The actual figure of the proposed RF energy harvesting system.

Figure 18 .
Figure 18.Measured 2.45 GHz Wi-Fi signal strength inside the indoor area.

Figure 18 .
Figure 18.Measured 2.45 GHz Wi-Fi signal strength inside the indoor area.

Figure 19 .
Figure 19.The actual measurement results, (a) Output voltage, current, power, and energy and (b) The proposed harvesting system efficiency versus time.

Figure 19 .
Figure 19.The actual measurement results, (a) Output voltage, current, power, and energy and (b) The proposed harvesting system efficiency versus time.

Table 1 .
State of the art wireless sensor power consumption.
The general block diagram of the proposed system.

Table 2 .
The parameters of Schottky diode.

Table 2 .
The parameters of Schottky diode.

Table 3 .
The proposed circuit components value.

Table 3 .
The proposed circuit components value.

Table 3 .
The proposed circuit components value.

Table 4 .
Recent low power wireless sensor characteristics.

Table 4 .
Recent low power wireless sensor characteristics.

Table 5 .
The proposed system key features.

Table 6 .
System performance comparison.A bandpass filter for a single frequency; ** Multi-bandpass filter for multiple single frequencies; *** A bandpass filter for multiple single freq; *+ Multi-bandpass filter for multiple single freq.using four-dipole antenna; *++ Multi-bandpass filter for multiple single freq.; no physical connection between two different RF channels; *+* Multi-bandpass filter for multiple single freq. *