Digital Controller Design Based on Active Damping Method of Capacitor Current Feedback for Auxiliary Resonant Snubber Inverter with LC Filter

In some high-performance applications, an LC filter must be added to the auxiliary resonant snubber inverter (ARSI) to reduce the output current ripple. However, resonance occurs due to the additional LC filter, which makes the traditional closed-loop control not suitable to be used directly. Therefore, this paper presents a double-loop digital control based on the active damping method of capacitor current feedback to stabilize the system. Most of the studies on active damping methods are focused on the grid in consideration of zero resistance. However, the load resistance should not be neglected in the drive system. Therefore, the load resistance and digital control delays are considered in this paper. Moreover, an improved loading method is proposed to improve the duty ratio range. In order to verify the effectiveness of the controller, a prototype was developed. The simulation and experimental results demonstrate that soft-switching can be realized for the entire load range. The maximum duty ratio is improved by 0.01 by using the proposed loading method. The resonance can be eliminated by using the proposed control method.


Introduction
In power electronic converters, high switching frequency is a highly desirable feature, which can not only reduce the volume and power density of converters, but also increase the dynamic response.However, high switching frequency brings about the problems of high switching loss and severe electromagnetic interference (EMI) [1,2].The soft switching technique is one of the best options to address the problems above.To date, a variety of soft-switching DC-AC topologies have been proposed.Among them, the zero-voltage-transition (ZVT) pulse-width-modulation (PWM) inverter is a typical soft-switching inverter [3][4][5][6][7][8][9][10][11].An auxiliary circuit connected parallel to the main power path is employed in the ZVT PWM inverter, which only operates for a short interval before and after the commutation period of the main switches.This makes the ZVT inverter closest to the PWM converter counterpart.Compared with other soft-switching inverters, the voltage and current stresses and conduction losses are much lower [3,4].Contributing to these advantages, the ZVT PWM inverter is well accepted.
Several topologies of the ZVT PWM inverter have been proposed.The auxiliary resonant commutated pole inverter (ARCPI) has been proposed with two auxiliary switches per phase [5,6].The ARCPI can meet the demand for high efficiency and low voltage and current stresses.However, the major drawback is the existence of the split capacitors, which cause the problems of capacitor charge unbalance.The auxiliary resonant snubber inverter (ARSI) has been proposed to eliminate the split capacitors, but the three-phase topology cannot utilize the conventional space-vector-pulse-width modulation (SVPWM) [7,8].Thus, they are more suitable for permanent magnet brushless DC motors instead of all types of motors.The single-phase topology is very attractive with only two auxiliary switches and well fit to the conventional PWM.Meanwhile, the ZVT inverter using coupled magnetics has been proposed to eliminate the split capacitors [9][10][11].However, these topologies need coupled inductors and a large number of auxiliary switches, which increases the cost and difficulty of the circuit realization.The ZVT PWM converter has been synthesized and summarized in [3,4].
In high-precision motor drive applications, an LC filter must be added in the ARSI to reduce the output current ripple.Moreover, the additional LC filter can solve problems of poor insulation that result from the overvoltage [12].However, since the additional LC filter together with the inductor of the motor forms the LCL filter, a resonance peak occurs in the system, which makes the system unstable.Recently, the passive damping method has been used to stabilize the system [13,14].The passive components of resistors, capacitors, and inductors are parallel or series-connected to the filter capacitor to damp out the resonance.The method is easy to implement; however, it reduces the efficiency of the system.The active damping method can be used to damp out the resonance at no expense of efficiency.The state variable feedback, such as filter capacitor voltage [15,16] or filter capacitor current [17,18], is introduced to provide virtual resistance.Among them, the capacitor current feedback is a typical and widely used method.
Most studies of the active damping method have focused on the grid with consideration of zero resistance.However, in the drive system, the load resistance should not be neglected.Until now, only a few researchers have studied the active damping in the motor drive system; however, they have not taken into consideration the digital control delays.In addition, previous studies on ARSI have focused on the circuit design and auxiliary current control but there has been a lack of research about the design of the closed-loop control.Thus, a step-by-step closed-loop controller design of the ARSI with LC filter is proposed in this paper, including the auxiliary current controller and the output current controller.A double-loop control based on active damping method of capacitor current feedback and PI regulator is introduced.The load resistance and digital control delays are considered.Moreover, an improved loading scheme of digital PWM (DPWM) is proposed to improve the duty ratio range of the ARSI.Finally, simulations and experiments are carried out to verify the effectiveness of the proposed method.

Control of the ARSI
Figure 1 depicts the single-phase ARSI topology analyzed in this paper, which consists of a standard H-bridge inverter, an auxiliary circuit, and an LC filter.The proper operation of the auxiliary switches S r1 and S r2 can create zero-voltage-switching (ZVS) conditions for the main switches S 1 -S 4 .Meanwhile, the auxiliary switches can realize zero-current switching (ZCS).
split capacitors, but the three-phase topology cannot utilize the conventional space-vector-pulsewidth modulation (SVPWM) [7,8].Thus, they are more suitable for permanent magnet brushless DC motors instead of all types of motors.The single-phase topology is very attractive with only two auxiliary switches and well fit to the conventional PWM.Meanwhile, the ZVT inverter using coupled magnetics has been proposed to eliminate the split capacitors [9][10][11].However, these topologies need coupled inductors and a large number of auxiliary switches, which increases the cost and difficulty of the circuit realization.The ZVT PWM converter has been synthesized and summarized in [3,4].
In high-precision motor drive applications, an LC filter must be added in the ARSI to reduce the output current ripple.Moreover, the additional LC filter can solve problems of poor insulation that result from the overvoltage [12].However, since the additional LC filter together with the inductor of the motor forms the LCL filter, a resonance peak occurs in the system, which makes the system unstable.Recently, the passive damping method has been used to stabilize the system [13,14].The passive components of resistors, capacitors, and inductors are parallel or series-connected to the filter capacitor to damp out the resonance.The method is easy to implement; however, it reduces the efficiency of the system.The active damping method can be used to damp out the resonance at no expense of efficiency.The state variable feedback, such as filter capacitor voltage [15,16] or filter capacitor current [17,18], is introduced to provide virtual resistance.Among them, the capacitor current feedback is a typical and widely used method.
Most studies of the active damping method have focused on the grid with consideration of zero resistance.However, in the drive system, the load resistance should not be neglected.Until now, only a few researchers have studied the active damping in the motor drive system; however, they have not taken into consideration the digital control delays.In addition, previous studies on ARSI have focused on the circuit design and auxiliary current control but there has been a lack of research about the design of the closed-loop control.Thus, a step-by-step closed-loop controller design of the ARSI with LC filter is proposed in this paper, including the auxiliary current controller and the output current controller.A double-loop control based on active damping method of capacitor current feedback and PI regulator is introduced.The load resistance and digital control delays are considered.Moreover, an improved loading scheme of digital PWM (DPWM) is proposed to improve the duty ratio range of the ARSI.Finally, simulations and experiments are carried out to verify the effectiveness of the proposed method.Figure 2 shows a control diagram of the ARSI.The ARSI controller consists of an output current controller and an auxiliary current controller.In the output current controller, the driving signals of the main switches are generated according to the output current.In order to dampen the resonance caused by the LC filter, a filter capacitor current feedback is introduced.The auxiliary current controller aims to control the auxiliary current to achieve ZVS of the main switches.Due to the large amount of calculations and the need for logic sequential control in the auxiliary current controller, a digital controller is required.

Control of the ARSI
Figure 2 shows a control diagram of the ARSI.The ARSI controller consists of an output current controller and an auxiliary current controller.In the output current controller, the driving signals of the main switches are generated according to the output current.In order to dampen the resonance caused by the LC filter, a filter capacitor current feedback is introduced.The auxiliary current controller aims to control the auxiliary current to achieve ZVS of the main switches.Due to the large amount of calculations and the need for logic sequential control in the auxiliary current controller, a digital controller is required.The auxiliary current control involves two methods, fixed-timing control [19] and variabletiming control [20].Owing to the advantages of lower conduction losses and achieving soft-switching for a wide load range, variable-time control methods are more widely used.By using the variabletiming control, the auxiliary current follows the magnitude of the load current adaptively.The auxiliary current controller in Figure 2 is realized based on the variable-timing control.The auxiliary controller is influenced by the output current controller, whereas the output current controller is independent of the auxiliary current controller.

Principle
Essentially, the ZVS realization of the main switches is to obtain a proper initial resonant current Ir, in order to discharge the resonant capacitors to zero voltage before the main switches are turned on.Figure 3 shows the key waveforms to realize ZVS of S1 and S4, where vds is the drain-source voltage of a MOSFET, id is the drain current of a MOSFET, vg is the gate signal, iLf is the filter inductor current, iLf_l is the lower envelope of iLf, iLf_u is the upper envelope of iLf, and iLr is the auxiliary current.When iLf_l < −Ir_min, iLf_l can create natural ZVS (NZVS) conditions for S1 and S4 without the operation of auxiliary switches.When iLf_l > −Ir_min, Sr1 is turned on before S2 and S3 are turned off.The resonant inductor Lr is charged, resulting in the linear increase of the auxiliary current.Therefore, a proper Ir can be obtained with the operation of Sr1.The auxiliary ZVS (AZVS) of S1 and S4 is realized.In order The auxiliary current control involves two methods, fixed-timing control [19] and variable-timing control [20].Owing to the advantages of lower conduction losses and achieving soft-switching for a wide load range, variable-time control methods are more widely used.By using the variable-timing control, the auxiliary current follows the magnitude of the load current adaptively.The auxiliary current controller in Figure 2 is realized based on the variable-timing control.The auxiliary controller is influenced by the output current controller, whereas the output current controller is independent of the auxiliary current controller.

Principle
Essentially, the ZVS realization of the main switches is to obtain a proper initial resonant current I r , in order to discharge the resonant capacitors to zero voltage before the main switches are turned on.Figure 3 shows the key waveforms to realize ZVS of S 1 and S 4 , where v ds is the drain-source voltage of a MOSFET, i d is the drain current of a MOSFET, v g is the gate signal, i Lf is the filter inductor current, i Lf_l is the lower envelope of i Lf , i Lf_u is the upper envelope of i Lf , and i Lr is the auxiliary current.When i Lf_l < −I r_min , i Lf_l can create natural ZVS (NZVS) conditions for S 1 and S 4 without the operation of auxiliary switches.When i Lf_l > −I r_min , S r1 is turned on before S 2 and S 3 are turned off.The resonant inductor L r is charged, resulting in the linear increase of the auxiliary current.Therefore, a proper I r can be obtained with the operation of S r1 .The auxiliary ZVS (AZVS) of S 1 and S 4 is realized.In order to fully discharge the resonant capacitors, the minimum initial resonant current must meet the following requirement: The principle of ARSI without LC filter was introduced in [21].The initial resonant current is the difference between the auxiliary current and the output current.Namely, the required auxiliary current is the sum of the output current and initial resonant current.As for the ARSI with LC filter, the auxiliary current is the sum of the filter inductor envelope current and the initial resonant current, which is different from that of the ARSI without LC filter.
to fully discharge the resonant capacitors, the minimum initial resonant current must meet the following requirement: The principle of ARSI without LC filter was introduced in [21].The initial resonant current is the difference between the auxiliary current and the output current.Namely, the required auxiliary current is the sum of the output current and initial resonant current.As for the ARSI with LC filter, the auxiliary current is the sum of the filter inductor envelope current and the initial resonant current, which is different from that of the ARSI without LC filter.The filter current ripple can be calculated as follows: (2 2 ) where vo is the output voltage, D is the duty ratio, and Ts is the switching period.The upper and lower envelopes of the filter inductor current can be calculated as follows: The ZVS realization of S1 and S4 is related to the lower envelope of the filter inductor current iLf_l shown in Figure 3. Similarly, the ZVS realization of S2 and S3 is related to the upper envelope of the filter inductor current iLf_u.Table 1 shows the ZVS types under different load conditions.

Switch
The output current can be obtained through the current sensor.Therefore, the required auxiliary current can be calculated as follows: The filter current ripple can be calculated as follows: where v o is the output voltage, D is the duty ratio, and T s is the switching period.
The upper and lower envelopes of the filter inductor current can be calculated as follows: The ZVS realization of S 1 and S 4 is related to the lower envelope of the filter inductor current i Lf_l shown in Figure 3. Similarly, the ZVS realization of S 2 and S 3 is related to the upper envelope of the filter inductor current i Lf_u .Table 1 shows the ZVS types under different load conditions.The output current can be obtained through the current sensor.Therefore, the required auxiliary current can be calculated as follows: The charging rate and the discharging rate of the resonant inductor are the same because of the same voltage V s .Therefore, the charging time of the resonant inductor t ch and the on-time of the auxiliary switch t A can be calculated as follows: After generating the driving signals of the main switches, the gate signal of the auxiliary switches can be generated from Equations ( 6) and ( 7).

Limitation of the Duty Ratio
In the ARSI, to guarantee the ZVS of one set of switches, the auxiliary circuit must be turned on before the opposite set of switches is turned off.Subsequently, the resonant inductor can be charged to the required current.Therefore, the minimum on-time of the opposite set of switches must be longer than the maximum charging time of the resonant inductor.This requirement limits the maximum duty ratio D max .
Figure 4 shows the DPWM diagram of the ARSI.The triangle carrier is adopted due to its lower harmonic compared to the sawtooth carrier [22].Moreover, the current is synchronously sampled at twice the PWM carrier interval, which can eliminate the switching current ripple from the current samples without needing low-pass filtering or complex ripple elimination filters [23].Then the calculated reference voltage v c is loaded into a modulator at the point of upper limit and lower limit of the reference voltage V upperlimit and V lowerlimit , instead of the conventional loading point V cmax and V cmin .The proposed loading method can improve the maximum duty ratio.The reason is given as follows: The charging rate and the discharging rate of the resonant inductor are the same because of the same voltage Vs.Therefore, the charging time of the resonant inductor tch and the on-time of the auxiliary switch tA can be calculated as follows: After generating the driving signals of the main switches, the gate signal of the auxiliary switches can be generated from Equations ( 6) and ( 7).

Limitation of the Duty Ratio
In the ARSI, to guarantee the ZVS of one set of switches, the auxiliary circuit must be turned on before the opposite set of switches is turned off.Subsequently, the resonant inductor can be charged to the required current.Therefore, the minimum on-time of the opposite set of switches must be longer than the maximum charging time of the resonant inductor.This requirement limits the maximum duty ratio Dmax.
Figure 4 shows the DPWM diagram of the ARSI.The triangle carrier is adopted due to its lower harmonic compared to the sawtooth carrier [22].Moreover, the current is synchronously sampled at twice the PWM carrier interval, which can eliminate the switching current ripple from the current samples without needing low-pass filtering or complex ripple elimination filters [23].Then the calculated reference voltage vc is loaded into a modulator at the point of upper limit and lower limit of the reference voltage Vupperlimit and Vlowerlimit, instead of the conventional loading point Vcmax and Vcmin.The proposed loading method can improve the maximum duty ratio.The reason is given as follows: In order to achieve ZVS from zero load to full load, the minimum on-time of the main switches must be longer than the maximum charging time of the resonant inductor: In order to achieve ZVS from zero load to full load, the minimum on-time of the main switches must be longer than the maximum charging time of the resonant inductor: The maximum charging time occurs when the output current reaches its maximum value I o_max .The minimum on-time of the main switches occurs when the duty ratio reaches D max .Figure 5 shows the DPWM diagram at the condition of I o_max and D max .Figure 5a shows the conventional loading scheme, namely loading at V cmax and V cmin .The Kth current is sampled at the point V cmin .Then the data are loaded at the next V cmax after calculation.Subsequently, S r1 can be turned on to charge the resonant inductor.Therefore, the following requirement must be met based on Equation (8): The upper limit of the reference voltage can be obtained from Equation ( 9): The maximum duty ratio D max occurs when t on_min equals t ch_max .However, Figure 5a shows that t on_min is still longer than t ch_max in this case.Only after the Kth data are loaded at V cmax , S r1 can be controlled.In this case, a short time cannot be utilized.
The maximum charging time occurs when the output current reaches its maximum value Io_max.The minimum on-time of the main switches occurs when the duty ratio reaches Dmax. Figure 5 shows the DPWM diagram at the condition of Io_max and Dmax. Figure 5a shows the conventional loading scheme, namely loading at Vcmax and Vcmin.The Kth current is sampled at the point Vcmin.Then the data are loaded at the next Vcmax after calculation.Subsequently, Sr1 can be turned on to charge the resonant inductor.Therefore, the following requirement must be met based on Equation ( 8): ) The upper limit of the reference voltage can be obtained from Equation ( 9): The maximum duty ratio Dmax occurs when ton_min equals tch_max.However, Figure 5a shows that ton_min is still longer than tch_max in this case.Only after the Kth data are loaded at Vcmax, Sr1 can be controlled.In this case, a short time cannot be utilized.In order to improve Dmax, an improved loading scheme is adopted in which the data are loaded at Vupperlimit and Vlowerlimit.In this case, Sr1 can be turned on in advance.Furthermore, this loading scheme will not influence the gate signal generation of the main switches because the reference voltage vc is limited between Vupperlimit and Vlowerlimit.Figure 5b shows that ton_min equals tch_max by using the improved loading scheme, which improves Dmax.
In the improved loading scheme, the following requirement must be satisfied based on Equation (8): ) The upper limit of the reference voltage can be obtained from Equation (11): In order to improve D max , an improved loading scheme is adopted in which the data are loaded at V upperlimit and V lowerlimit .In this case, S r1 can be turned on in advance.Furthermore, this loading scheme will not influence the gate signal generation of the main switches because the reference voltage v c is limited between V upperlimit and V lowerlimit .Figure 5b shows that t on_min equals t ch_max by using the improved loading scheme, which improves D max .
In the improved loading scheme, the following requirement must be satisfied based on Equation (8): The upper limit of the reference voltage can be obtained from Equation ( 11): From Equations ( 10) and ( 12), the limit of the reference voltage v c can be improved by adopting the improved loading scheme, resulting in larger D max .

The Model of the ARSI
Figure 6 shows the digital control model of the output current controller, where G c (z) is the proportional integral (PI) regulator, G dc (z) is the calculation and transport delay, the sampling switch stands for analog digital converter, K pwm is the gain of the ARSI, K cf is the filter capacitor current feedback coefficient, and G 1 (s) and G 2 (s) are the output impedance.In the digital controller, all the calculations and operations are discrete.Therefore, the digital controller is modeled on the z-domain.
From Equations ( 10) and ( 12), the limit of the reference voltage vc can be improved by adopting the improved loading scheme, resulting in larger Dmax.

The Model of the ARSI
Figure 6 shows the digital control model of the output current controller, where Gc(z) is the proportional integral (PI) regulator, Gdc(z) is the calculation and transport delay, the sampling switch stands for analog digital converter, Kpwm is the gain of the ARSI, Kcf is the filter capacitor current feedback coefficient, and G1(s) and G2(s) are the output impedance.In the digital controller, all the calculations and operations are discrete.Therefore, the digital controller is modeled on the z-domain.

PI Controller Design
Commonly, the sample period is short and the time constant of the controlled plant is much larger than the sample period.Therefore, the digital PI controller can be designed in the s-domain.Figure 7 shows the output current controller model in the s-domain.The PI regulator Gc(s) can be written as follows:

PI Controller Design
Commonly, the sample period is short and the time constant of the controlled plant is much larger than the sample period.Therefore, the digital PI controller can be designed in the s-domain.Figure 7 shows the output current controller model in the s-domain.
From Equations ( 10) and ( 12), the limit of the reference voltage vc can be improved by adopting the improved loading scheme, resulting in larger Dmax.

The Model of the ARSI
Figure 6 shows the digital control model of the output current controller, where Gc(z) is the proportional integral (PI) regulator, Gdc(z) is the calculation and transport delay, the sampling switch stands for analog digital converter, Kpwm is the gain of the ARSI, Kcf is the filter capacitor current feedback coefficient, and G1(s) and G2(s) are the output impedance.In the digital controller, all the calculations and operations are discrete.Therefore, the digital controller is modeled on the z-domain.

PI Controller Design
Commonly, the sample period is short and the time constant of the controlled plant is much larger than the sample period.Therefore, the digital PI controller can be designed in the s-domain.Figure 7 shows the output current controller model in the s-domain.The PI regulator Gc(s) can be written as follows: The PI regulator G c (s) can be written as follows: After the current is sampled, a sampling period delay T sp exists, which is shown in Figure 4. Therefore, the calculation and transport delay can be written as follows: where the sampling period T sp = T s /2.
In the s-domain, the sampling switch can be modeled as 1/T sp [24].The modulator can be modeled by zero-order holder (ZOH) [25], which can be expressed as: Commonly, the cutoff frequency of the LC filter is larger than the bandwidth frequency of the ARSI.Therefore, the filter inductance is much lower than the load inductance, namely L f << L o .The output impedance can be written as follows: The system open-loop transfer function can be calculated as follows: The closed-loop transfer function can be written as follows: In order not to reduce the bandwidth of the ARSI, the cutoff frequency of the LC filter is designed to be two times larger than the system bandwidth f c .Therefore, the influence of the filter capacitor can be ignored when calculating the magnitude of the loop gain at f c and frequencies lower than f c .The low-frequency controller characteristics will still be dominated by the series filter inductance.Thus, the transfer Equation ( 18) can be approximated as follows: Figure 8 shows the Bode plots of the approximation model ( 20) and the precise model (18).It demonstrates that the cutoff frequency of the system will not be influenced by using the approximation model.When the crossover frequency and phase margin are specified as ωc and φm respectively, the parameters of the PI controller can be obtained: If Kp >> Ki/ωc, Equation ( 21) can be approximated as: Figure 9 shows the Bode plot of the ARSI with different PI parameters.The circuit parameters are listed in Table 2.When Kp >> Ki/ωc, the crossover frequency ωc is determined by Kp.The larger Kp, the larger ωc and the faster the dynamic response.Regarding Ki, it will influence the low-frequency gain, which can influence the stable precision of the system.The larger Ki, the larger the lowfrequency gain and the higher the stable precision.Ki has almost no influence on the frequency characteristic around ωc when Kp >> Ki/ωc.However, when Ki/ωc is close to Kp, Ki will influence the phase margin.The larger Ki, the smaller the phase margin.When the crossover frequency and phase margin are specified as ω c and ϕ m respectively, the parameters of the PI controller can be obtained: If K p >> K i /ω c , Equation ( 21) can be approximated as: Figure 9 shows the Bode plot of the ARSI with different PI parameters.The circuit parameters are listed in Table 2.When K p >> K i /ω c , the crossover frequency ω c is determined by K p .The larger K p , the larger ω c and the faster the dynamic response.Regarding K i , it will influence the low-frequency gain, which can influence the stable precision of the system.The larger K i , the larger the low-frequency gain and the higher the stable precision.K i has almost no influence on the frequency characteristic around ω c when K p >> K i /ω c .However, when K i /ω c is close to K p , K i will influence the phase margin.The larger K i , the smaller the phase margin.

Capacitor Current Feedback Design
In Section 4.2, the influence of filter capacitor is neglected when the PI parameters are designed.However, the LC filter together with the load inductance forms the LCL filter, which leads to resonance.To analyze the stability of the ARSI, the influence of filter capacitor cannot be ignored.The filter capacitor current feedback is introduced to damp the resonance.
Because of the delay caused by the computation, the system is no longer a minimum phase system.To design the inner capacitor current loop, a discrete model must be built instead of a continuous model.Figure 10 shows the model of the inverter, which is obtained from Figure 6.

Capacitor Current Feedback Design
In Section 4.2, the influence of filter capacitor is neglected when the PI parameters are designed.However, the LC filter together with the load inductance forms the LCL filter, which leads to resonance.To analyze the stability of the ARSI, the influence of filter capacitor cannot be ignored.The filter capacitor current feedback is introduced to damp the resonance.
Because of the delay caused by the computation, the system is no longer a minimum phase system.To design the inner capacitor current loop, a discrete model must be built instead of a continuous model.Figure 10 shows the model of the inverter, which is obtained from Figure 6.

Capacitor Current Feedback Design
In Section 4.2, the influence of filter capacitor is neglected when the PI parameters are designed.However, the LC filter together with the load inductance forms the LCL filter, which leads to resonance.To analyze the stability of the ARSI, the influence of filter capacitor cannot be ignored.The filter capacitor current feedback is introduced to damp the resonance.
Because of the delay caused by the computation, the system is no longer a minimum phase system.To design the inner capacitor current loop, a discrete model must be built instead of a continuous model.Figure 10 shows the model of the inverter, which is obtained from Figure 6. where In the z-domain, the root locus is used to analyze the stability of the system.The relevant expressions can be developed from Equation (23) as follows: Equation ( 19) can be transformed as follows: 1 From Equation (26), the root locus related to K cf can be plotted in Figure 11.When the capacitor current feedback is not used, namely K cf = 0, the closed-loop poles are outside the unit circle, which demonstrates that the system is unstable.As K cf increases, the system becomes stable.However, if K cf is too large, the system becomes unstable again.
Figure 12 shows the Bode plot with different K cf which is obtained from Equation ( 24).In the magnitude-frequency characteristic, K cf hardly influences the low-frequency characteristic.As K cf increases, the open-loop gain decreases slightly around the crossover frequency ω c .Besides, the resonance peak is damped.In the phase-frequency characteristic, the phase margin decreases with the increase of K cf .When K cf is large enough, the phase-frequency curve crosses −180 • after it drops to −180 • .This makes the system unstable according to the stability criterion.In order to stabilize the system, the active damping gain Kcf must meet the requirements as follows.(The detailed proof is presented in Appendix B.) where   In order to stabilize the system, the active damping gain Kcf must meet the requirements as follows.(The detailed proof is presented in Appendix B.) where In order to stabilize the system, the active damping gain K cf must meet the requirements as follows.(The detailed proof is presented in Appendix B.) where

Design Example
The circuit parameters are listed in Table 2.The specifications are given as the crossover frequency f c ≈ 10 kHz and the phase margin ϕ m > 45 • .
(1) Determination of the initial resonant current I r : According to Equation (1), the minimum initial resonant current is given as I r_min > 2.16 A. The minimum initial resonant current and the initial resonant current for AZVS are selected as I r_min = 2.5 A and I r_A = 5 A, respectively.Therefore, when i Lf_l < −2.5 A, S r1 is not operated, achieving NZVS of S 1 and S 4 according to Table 1.Otherwise, S r1 would be turned on properly to realize AZVS of S 1 and S 4 .Regarding S 2 and S 3 , when i Lf_u < 2.5 A, S r2 must be turned on to create AZVS conditions.When i Lf_u > 2.5 A, S 2 and S 3 can achieve NZVS.
(2) Determination of the upper limit and lower limit of the DPWM (V upperlimit and V lowerlimit ) The frequency of the DPWM clock is 120 MHz.Thus, the carriers are specified as V cmax = 300 and V cmin = 0 to achieve 200 kHz switching frequency.To simplify the calculation, the filter inductor current ripple is neglected.Therefore, the maximum required auxiliary current can be obtained from Equation ( 5) as I Lrm_max = I r_A + I o_max = 13 A. The maximum charging time t ch_max can be calculated from Equation (6) as t ch_max = 357.5 ns.The upper limit can be calculated from Equation ( 12) as V upperlimit ≈ 266 by using the improved loading scheme.Thus, the lower limit V lowerlimit and maximum duty ratio D max are 34 and 0.867, respectively.Regarding the conventional loading scheme, the upper limit, lower limit, and maximum duty ratio are 257, 43, and 0.857, respectively.Table 3 shows a comparison of the parameters between the conventional and improved loading scheme.The range of the duty ratio is improved by utilizing the improved loading scheme.(3) Determination of the PI regulator parameters and active damping gain K cf The active damping gain K cf will influence the stability of the system and the phase margin will decrease due to the increase of K cf according to the analysis in Section 4.3.However, the influence of the filter capacitor is neglected to simplify the design of the PI regulator in Section 4.2.Therefore, in order to meet the requirement ϕ m > 45 • , the phase margin is specified as 60 • due to the capacitor current feedback.Thus, the parameters of the PI regulator can be calculated from Equation (21).The results are that K p = 3.6522 and K i = 70,999.To ensure the system's stability, the capacitor current feedback gain K cf must meet the requirement of 0.0158 < K cf < 0.119 according to Equation (27).The feedback gain is selected as K cf = 0.05.
Based on the above parameters, the Bode plots of the single loop and double loop can be obtained from Figure 13.The crossover frequency of the single loop is −62,900 rad/s and the phase margin is 60 • .This is in agreement with the design specifications.However, the LC filter leads to resonance, which makes the phase-frequency curve cross −180 • after it drops to −180 • .According to the stability criterion, the single-loop system is unstable.
Regarding the double-loop control, the crossover frequency is −61,000 rad/s and the phase margin is 46.4 • .Due to the capacitor current feedback, the crossover frequency and the phase margin decrease slightly.However, this outcome meets the requirement f c ≈ 10 kHz and ϕ m > 45 • .When 20log |G(jω)| ≥ 0, the phase-frequency curve does not cross −180 • .According to the stability criterion, the double-loop system is stable.
Appl.Sci.2016, 6, 377 14 of 22 (3) Determination of the PI regulator parameters and active damping gain Kcf The active damping gain Kcf will influence the stability of the system and the phase margin will decrease due to the increase of Kcf according to the analysis in Section 4.3.However, the influence of the filter capacitor is neglected to simplify the design of the PI regulator in Section 4.2.Therefore, in order to meet the requirement φm > 45°, the phase margin is specified as 60° due to the capacitor current feedback.Thus, the parameters of the PI regulator can be calculated from Equation (21).The results are that Kp = 3.6522 and Ki = 70,999.To ensure the system's stability, the capacitor current feedback gain Kcf must meet the requirement of 0.0158 < Kcf < 0.119 according to Equation (27).The feedback gain is selected as Kcf = 0.05.
Based on the above parameters, the Bode plots of the single loop and double loop can be obtained from Figure 13.The crossover frequency of the single loop is −62,900 rad/s and the phase margin is 60°.This is in agreement with the design specifications.However, the LC filter leads to resonance, which makes the phase-frequency curve cross −180° after it drops to −180°.According to the stability criterion, the single-loop system is unstable.
Regarding the double-loop control, the crossover frequency is −61,000 rad/s and the phase margin is 46.4°.Due to the capacitor current feedback, the crossover frequency and the phase margin decrease slightly.However, this outcome meets the requirement fc ≈ 10 kHz and φm > 45°.When 20 log ( ) 0 , the phase-frequency curve does not cross −180°.According to the stability criterion, the double-loop system is stable.

Simulations and Experiments
The method was implemented in the Altera Cyclone IV FPGA with the parameters given in Table 2. Figure 14 shows a photograph of the prototype.It consists of a FPGA (EP4CE22E22C7N, Altera Corporation, San Jose, CA, USA) control board, a switching power supply, a MOSFET driver, and a power circuit.The method is verified in the simulation using Saber.

Simulations and Experiments
The method was implemented in the Altera Cyclone IV FPGA with the parameters given in Table 2. Figure 14 shows a photograph of the prototype.It consists of a FPGA (EP4CE22E22C7N, Altera Corporation, San Jose, CA, USA) control board, a switching power supply, a MOSFET driver, and a power circuit.The method is verified in the simulation using Saber.Figures 19 and 20 show the simulation and experimental results of the output current with and without active damping method, respectively.Figure 19 demonstrates that strong resonance occurs in the output current without the active damping method, because closed-loop poles are outside the unit circle shown in Figure 11.After utilizing the capacitor current feedback, the poles can be moved into the unit circle.Therefore, the system can be stable both at the DC or sinusoidal output current conditions.Figure 20 also demonstrates that active damping is necessary to maintain stability and current quality.
Figures 19 and 20 show the simulation and experimental results of the output current with and without active damping method, respectively.Figure 19 demonstrates that strong resonance occurs in the output current without the active damping method, because closed-loop poles are outside the unit circle shown in Figure 11.After utilizing the capacitor current feedback, the poles can be moved into the unit circle.Therefore, the system can be stable both at the DC or sinusoidal output current conditions.Figure 20 also demonstrates that active damping is necessary to maintain stability and current quality.Figures 19 and 20 show the simulation and experimental results of the output current with and without active damping method, respectively.Figure 19 demonstrates that strong resonance occurs in the output current without the active damping method, because closed-loop poles are outside the unit circle shown in Figure 11.After utilizing the capacitor current feedback, the poles can be moved into the unit circle.Therefore, the system can be stable both at the DC or sinusoidal output current conditions.Figure 20 also demonstrates that active damping is necessary to maintain stability and current quality.

Conclusions
In some high-performance applications, an LC filter must be added to the auxiliary resonant snubber inverter (ARSI) to reduce the output current ripple.This makes the system quite different to the conventional ARSI without LC filter.This paper presents the modeling and the double-loop digital control of the ARSI with LC filter.The following points can be summarized to cover the paper: (1) An improved loading scheme that the data is updating at the upper limit and lower limit of the carrier is proposed to improve the maximum duty ratio.(2) The filter capacitor current feedback is introduced to damp the resonance caused by the LC filter.
(3) A step-by-step digital controller design method, including the auxiliary current controller and the output PI controller, is proposed, in which the computation and transport delay is considered.
The control method has been verified by simulations and experiments.The maximum duty ratio is improved by 0.01 with the proposed loading method.In addition, soft-switching can be realized for the entire load range.Also, the resonance can be eliminated with the capacitor current feedback.

Conclusions
In some high-performance applications, an LC filter must be added to the auxiliary resonant snubber inverter (ARSI) to reduce the output current ripple.This makes the system quite different to the conventional ARSI without LC filter.This paper presents the modeling and the double-loop digital control of the ARSI with LC filter.The following points can be summarized to cover the paper: (1) An improved loading scheme that the data is updating at the upper limit and lower limit of the carrier is proposed to improve the maximum duty ratio.(2) The filter capacitor current feedback is introduced to damp the resonance caused by the LC filter.
(3) A step-by-step digital controller design method, including the auxiliary current controller and the output PI controller, is proposed, in which the computation and transport delay is considered.
The control method has been verified by simulations and experiments.The maximum duty ratio is improved by 0.01 with the proposed loading method.In addition, soft-switching can be realized for the entire load range.Also, the resonance can be eliminated with the capacitor current feedback.

Conclusions
In some high-performance applications, an LC filter must be added to the auxiliary resonant snubber inverter (ARSI) to reduce the output current ripple.This makes the system quite different to the conventional ARSI without LC filter.This paper presents the modeling and the double-loop digital control of the ARSI with LC filter.The following points can be summarized to cover the paper: (1) An improved loading scheme that the data is updating at the upper limit and lower limit of the carrier is proposed to improve the maximum duty ratio.(2) The filter capacitor current feedback is introduced to damp the resonance caused by the LC filter.
(3) A step-by-step digital controller design method, including the auxiliary current controller and the output PI controller, is proposed, in which the computation and transport delay is considered.
The control method has been verified by simulations and experiments.The maximum duty ratio is improved by 0.01 with the proposed loading method.In addition, soft-switching can be realized for the entire load range.Also, the resonance can be eliminated with the capacitor current feedback. where In order to easily identify the quantity of the unstable poles, w-transform z = (1 + w)/(1 + w) is introduced.Therefore, Equation (B1) can be transformed as follows: where It can be obtained that a 0 > 0. Thus according to Routh's Method, the following requirement must be satisfied to maintain the system's stability: From Equation (B3), the filter capacitor current feedback gain K cf must meet the following requirement: where

Figure 1
Figure 1 depicts the single-phase ARSI topology analyzed in this paper, which consists of a standard H-bridge inverter, an auxiliary circuit, and an LC filter.The proper operation of the auxiliary switches Sr1 and Sr2 can create zero-voltage-switching (ZVS) conditions for the main switches S1-S4.Meanwhile, the auxiliary switches can realize zero-current switching (ZCS).

Figure 1 .
Figure 1. Circuit of the single-phase auxiliary resonant snubber inverter (ARSI) with LC filter.Figure 1. Circuit of the single-phase auxiliary resonant snubber inverter (ARSI) with LC filter.

Figure 1 .
Figure 1. Circuit of the single-phase auxiliary resonant snubber inverter (ARSI) with LC filter.Figure 1. Circuit of the single-phase auxiliary resonant snubber inverter (ARSI) with LC filter.

Figure 2 .
Figure 2. Control diagram of the ARSI.

Figure 2 .
Figure 2. Control diagram of the ARSI.

Figure 5 .
Figure 5. DPWM diagram at the condition of Io_max and Dmax: (a) conventional loading scheme; (b) improved loading scheme.

Figure 5 .
Figure 5. DPWM diagram at the condition of I o_max and D max : (a) conventional loading scheme; (b) improved loading scheme.

Figure 6 .
Figure 6.Digital control model of the output current controller.

Figure 7 .
Figure 7. Output current controller model in the s-domain.

Figure 6 .
Figure 6.Digital control model of the output current controller.

Figure 6 .
Figure 6.Digital control model of the output current controller.

Figure 7 .
Figure 7. Output current controller model in the s-domain.

Figure 7 .
Figure 7. Output current controller model in the s-domain.

Figure 8 .
Figure 8. Bode plot of the approximated model and the precise model.

Figure 8 .
Figure 8. Bode plot of the approximated model and the precise model.

Figure 9 .
Figure 9. Bode plot of the ARSI with different PI parameters: (a) different Kp; (b) different Ki.

Figure 10 .
Figure 10.Model of ARSI in digital control.

Figure 9 .
Figure 9. Bode plot of the ARSI with different PI parameters: (a) different K p ; (b) different K i .

Figure 9 .
Figure 9. Bode plot of the ARSI with different PI parameters: (a) different Kp; (b) different Ki.

Figure 10 .
Figure 10.Model of ARSI in digital control.Figure 10.Model of ARSI in digital control.

Figure 10 .
Figure 10.Model of ARSI in digital control.Figure 10.Model of ARSI in digital control.

Figure 11 .
Figure 11.Root locus of variation in active damping gain Kcf using a dual-loop controller.

Figure 12 .
Figure 12.Open-loop Bode plot with different active damping gain Kcf.

Figure 11 .
Figure 11.Root locus of variation in active damping gain K cf using a dual-loop controller.

Figure 11 .
Figure 11.Root locus of variation in active damping gain Kcf using a dual-loop controller.

Figure 12 .
Figure 12.Open-loop Bode plot with different active damping gain Kcf.

Figure 12 .
Figure 12.Open-loop Bode plot with different active damping gain K cf .

Figure 13 .
Figure 13.Bode plot of the single loop and double loop.

Figure 13 .
Figure 13.Bode plot of the single loop and double loop.

Figure 14 .
Figure 14.Photograph of the prototype.

Figures 15 and 16
Figures 15 and 16  show the simulation and experimental transitional waveforms of the main switches, respectively.During the turn-on commutation, the drain currents id3 and id4 begin increasing after the drain-source voltage vds3 and vds4 drop to zero.ZVS of S4 is achieved with the operation of Sr1, whereas the auxiliary switches are not turned on to achieve ZVS of S3.Regarding the turn-off commutation, the drain current overlaps the drain-source voltage slightly because the resonant capacitance is not large enough.Due to the parasitic components, ringing occurs during the commutation in the experiment.

Figure 15 .
Figure 15.Simulation results of the current and voltage of the main switches when io = 8 A. (a) S3; (b) S4.

Figure 14 .
Figure 14.Photograph of the prototype.

Figures 15 and 16
Figures 15 and 16  show the simulation and experimental transitional waveforms of the main switches, respectively.During the turn-on commutation, the drain currents i d3 and i d4 begin increasing after the drain-source voltage v ds3 and v ds4 drop to zero.ZVS of S 4 is achieved with the operation of S r1 , whereas the auxiliary switches are not turned on to achieve ZVS of S 3 .Regarding the turn-off commutation, the drain current overlaps the drain-source voltage slightly because the resonant capacitance is not large enough.Due to the parasitic components, ringing occurs during the commutation in the experiment.

Figure 14 .
Figure 14.Photograph of the prototype.

Figures 15 and 16
Figures 15 and 16  show the simulation and experimental transitional waveforms of the main switches, respectively.During the turn-on commutation, the drain currents id3 and id4 begin increasing after the drain-source voltage vds3 and vds4 drop to zero.ZVS of S4 is achieved with the operation of Sr1, whereas the auxiliary switches are not turned on to achieve ZVS of S3.Regarding the turn-off commutation, the drain current overlaps the drain-source voltage slightly because the resonant capacitance is not large enough.Due to the parasitic components, ringing occurs during the commutation in the experiment.

Figure 15 .
Figure 15.Simulation results of the current and voltage of the main switches when io = 8 A. (a) S3; (b) S4.Figure 15.Simulation results of the current and voltage of the main switches when i o = 8 A. (a) S 3 ; (b) S 4 .

Figure 15 .
Figure 15.Simulation results of the current and voltage of the main switches when io = 8 A. (a) S3; (b) S4.Figure 15.Simulation results of the current and voltage of the main switches when i o = 8 A. (a) S 3 ; (b) S 4 .

Figure 16 .
Figure 16.Experimental results of the current and voltage of the main switches when io = 8 A. (a) S3; (b) S4.

Figures 17
Figures 17 and 18 show the simulation and experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.The peak auxiliary switch current follows the load current with clear load adaptability.It can be seen that the lower the load current, the lower the auxiliary current.

Figure 17 .
Figure 17.Simulation waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 18 .
Figure 18.Experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 16 .
Figure 16.Experimental results of the current and voltage of the main switches when i o = 8 A. (a) S 3 ; (b) S 4 .

Figure 16 .
Figure 16.Experimental results of the current and voltage of the main switches when io = 8 A. (a) S3; (b) S4.

Figures 17
Figures 17 and 18 show the simulation and experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.The peak auxiliary switch current follows the load current with clear load adaptability.It can be seen that the lower the load current, the lower the auxiliary current.

Figure 17 .
Figure 17.Simulation waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 18 .
Figure 18.Experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 17 .
Figure 17.Simulation waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 16 .
Figure 16.Experimental results of the current and voltage of the main switches when io = 8 A. (a) S3; (b) S4.

Figures 17
Figures 17 and 18 show the simulation and experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.The peak auxiliary switch current follows the load current with clear load adaptability.It can be seen that the lower the load current, the lower the auxiliary current.

Figure 17 .
Figure 17.Simulation waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 18 .
Figure 18.Experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 18 .
Figure 18.Experimental waveforms of the auxiliary current with an 8 A, 100 Hz sinusoidal output current.

Figure 19 .Figure 20 .
Figure 19.Simulation results of the output current with and without active damping method: (a) DC output current; (b) sinusoidal output current.

Figures 21 and 22
Figures 21 and 22 show the simulation and experimental results of the load dynamic response, respectively.The results demonstrate that the output current tracks the reference current quickly.However, a bit of overshot exists in the transient response.

Figure 19 .
Figure 19.Simulation results of the output current with and without active damping method: (a) DC output current; (b) sinusoidal output current.

Figure 19 .Figure 20 .
Figure 19.Simulation results of the output current with and without active damping method: (a) DC output current; (b) sinusoidal output current.

Figures 21 and 22
Figures 21 and 22 show the simulation and experimental results of the load dynamic response, respectively.The results demonstrate that the output current tracks the reference current quickly.However, a bit of overshot exists in the transient response.

Figure 20 .
Figure 20.Experimental results of the output current (a) without and (b) with active damping method.

Figures 21 and 22
Figures 21 and 22 show the simulation and experimental results of the load dynamic response, respectively.The results demonstrate that the output current tracks the reference current quickly.However, a bit of overshot exists in the transient response.

Figure 21 .Figure 22 .
Figure 21.Simulation results of the load dynamic response: (a) a step change from 12.5% to 75% rated output power; (b) a step change from 75% to 12.5% rated output power.

Figure 21 .Figure 22 .
Figure 21.Simulation results of the load dynamic response: (a) a step change from 12.5% to 75% rated output power; (b) a step change from 75% to 12.5% rated output power.

Figure 22 .
Figure 22.Experimental results of the load dynamic response: (a) a step change from 12.5% to 62.5% rated output power; (b) a step change from 62.5% to 12.5% rated output power.

Table 1 .
Zero-voltage switching (ZVS) types of switches under different output currents.

Table 1 .
Zero-voltage switching (ZVS) types of switches under different output currents.

Table 2 .
Parameters of the circuit.

Table 2 .
Parameters of the circuit.

Table 2 .
Parameters of the circuit.

Table 3 .
Comparison of the parameters between the conventional and improved loading scheme.