Analysis and Compensation of Dead-Time Effect of a ZVT PWM Inverter Considering the Rise- and Fall-Times

: The dead-time effect, as an intrinsic problem of the converters based on the half-bridge unit, leads to distortions in the converter output. Although several dead-time effect compensation or elimination methods have been proposed, they cannot fully remove the dead-time effect of blanking delay error, because the output current polarity is difﬁcult detect accurately. This paper utilizes the zero-voltage-switching (ZVT) technique to eliminate the blanking delay error, which is the main drawback of the hard-switching inverter, although the technique initially aims to improve the efﬁciency. A typical ZVT inverter—the auxiliary resonant snubber inverter (ARSI) is analyzed. The blanking delay error is completely eliminated in the ARSI. Another error source caused by the ﬁnite rise- and fall-times of the voltage is analyzed, which was not considered in the hard-switching inverter. A compensation method based on the voltage error estimation is proposed to compensate the rise- and fall-error. A prototype was developed to verify the effectiveness of the proposed control. Both the simulation and experimental results demonstrate that the qualities of the output current and voltage in the ARSI are better than that in the hard-switching inverter due to the elimination of the blanking delay error. The total harmonic distortion (THD) of the output is further reduced by using the proposed compensation method in the ARSI.


Introduction
The half-bridge, as a basic unit, employs two stacked semiconductor switches connected across the DC voltage to realize energy transfer.In AC-DC or DC-AC applications, most of the converters consist of the half-bridge, such as the full-bridge converter and three-phase converter.The two switches in a half-bridge are complementarily conducted.Due to turn-on and turn-off delays and finite rise-time and fall-time during the commutation, a dead-time is inserted between the turn-on and the turn-off of the switches to avoid short circuiting.This results in a current-dependent switching node voltage during the dead-time, which increases the output distortion.
To date, extensive studies have focused on the problem of dead-time effect.Most of the compensation and elimination methods can be divided into three categories: the pulse-based compensation [1,2], the voltage feedforward compensation [3,4] and the dead-time elimination [5][6][7].For the pulse-based compensation method, the dead-time effect is modeled as a pulse shift error.A dead-time width pulse is added or reduced based on the shift error to compensate the dead-time effect [1,2].For the voltage feedforward compensation, the dead-time effect is modeled as an average voltage error, which is regarded as a disturbance to the output voltage.The voltage error is added to the reference voltage directly to compensate the dead-time effect [3,4].For the dead-time elimination method, the driving signal is only put on one switch, whereas the driving signal of the other switch is removed.The body diode conducts the current.Therefore, the dead-time is not required in this method [5][6][7].Theoretically, these three methods can fully compensate or eliminate the dead-time effect.In practice, however, the results depend on the detection precision of the output current polarity.Due to the output current ripple and zero current clamping, the output current polarity is difficult to detect accurately.Moreover, beyond the three methods, some other methods employing proper current control are proposed to solve the problem of dead-time effect [8][9][10][11].However, these techniques are still not capable of completely removing the dead-time effect.
In the half-bridge circuits, the voltage and current transitions can be turn-off controlled or turn-on controlled, which is influenced by the output current polarity.The turn-off controlled type refers to the case that the commutation is triggered by the turn-off of the switches.Thus, the body diodes of the next turn-on switches are conducted during the dead-time, whereas the turn-on controlled type refers to the case that the commutation is triggered by the turn-on of the switches.Different commutation type leads to different voltage error caused by the dead-time.This kind of dead-time effect is blanking delay error, which is the main error in the half-bridge-based topology [12].Essentially, the commutation type, which is related to the output current polarity, makes the dead-time effect difficult to remove completely.
Zero-voltage-switching (ZVT) soft-switching technique can be used to eliminate the blanking delay error, although the technique aims to reduce the switching loss and improve the efficiency.The transitions are all turn-off controlled in the ZVT soft-switching converters with the conduction of the anti-parallel diode during the dead-time, which is irrelevant to the output current.Therefore, the dead-time effect of blanking delay error can be completely removed by using the ZVT soft-switching technique.Until now, several topologies of the ZVT pulse-width-modulation (PWM) inverters have been proposed.The auxiliary resonant commutated pole inverter (ARCPI) has been proposed with two auxiliary switches per phase [13,14].The ARCPI can meet the demand for high efficiency, as well as low voltage and current stresses.However, the major drawback is the existence of the split capacitors, which causes capacitor charge unbalance.The auxiliary resonant snubber inverter (ARSI) has been proposed to eliminate the split capacitors, but the three-phase topology cannot utilize the conventional space-vector-pulse-width modulation (SVPWM) [15,16].Thus, they are more suitable for permanent magnet brushless DC motors than all types of motors.The single-phase topology is very attractive with only two auxiliary switches well fit to the conventional PWM.Meanwhile, the ZVT inverter using coupled magnetics has been proposed to eliminate the split capacitors [17][18][19].However, these topologies need coupled inductors and a large number of auxiliary switches, which unfortunately increase the cost and difficulty of the circuit realization.The ZVT PWM converter has been synthesized and summarized in [20,21].
Without adding the external resonant capacitors, the ZVT inverters can completely remove the dead-time effect.However, the external resonant capacitors are always required to reduce the voltage changing rate of the switches, so that the turn-off loss and electromagnetic interference (EMI) can be reduced.This will lead to output voltage distortion, which is caused by the finite commutation time.This kind of dead-time effect is quite different from that in the hard-switching inverters.Thus, this paper analyzes the dead-time effect of a typical example of ZVT PWM soft-switching inverters-ARSI.Then, a compensation method is proposed to remove the dead-time effect.Finally, the simulation and experiment are undertaken to verify the effectiveness of the proposed method.

Principle
Figure 1 depicts the single-phase ARSI topology analyzed in this paper, which consists of a standard H-bridge inverter, resonant capacitors and an auxiliary circuit.With a proper operation of In order to realize soft-switching for the entire load range and maintain a low auxiliary current, the ARSI operates in two modes of heavy load mode (HLM) and light load mode (LLM), as determined by the load condition [22].In the heavy load condition, the auxiliary circuit is only operated once in each switching period, thus achieving auxiliary ZVS (AZVS) of a set of switches.The other set of switches can achieve natural ZVS (NZVS) without the operation of auxiliary circuit.In the light load condition, the auxiliary circuit is operated twice in each switching period.Therefore, all the switches achieve AZVS.
The operating principle of the ARSI is introduced in [22].The detailed dead-time effect of LLM and HLM will be analyzed in the case of positive load current as follows.When the load current is negative, the operation is similar.
To analyze the circuit, we assume that (1) All components and devices are ideal; (2) The gate signals of the MOSFETs are ideal square-wave; (3) The output inductor Lo is high enough to be a constant current source.

Heavy Load Condition
In the heavy load condition, "AZVS + NZVS," namely achieving AZVS of a set of switches and NZVS of the other set of switches, is realized.One switching cycle of the operating waveforms are shown in Figure 2, where vds is the drain-source voltage of a MOSFET, id is the drain current of a MOSFET, vg is the actual gate signal with dead-time, vg,id is the ideal gate signal, iLr is the resonant inductor current, vab is the actual pole voltage across the load with dead-time, vab,id is the ideal pole voltage across the load and verr is the voltage error between vab and vab,id.
During the dead-time tH1-tH3, the resonant capacitors first resonate with the load inductor.Owing to the positive load current, Cr2 and Cr3 are discharged and Cr1 and Cr4 are charged.After Cr2 and Cr3 are discharged to zero-voltage at tH2, the body diodes D2 and D3 conduct the current and then the voltage is clamped to zero.Thus, S2 and S3 can be turned on at the ZVS condition.Regarding the dead-time tH1-tH3, it consists of the resonant stage and diode clamping stage.The dead-time causes the pole voltage error.As for the ARSI, the voltage error only occurs in the resonant stage, which is caused by the finite rise-and fall-times of the voltage.
During the resonant stage tH1-tH2, the actual pole voltage can be obtained as follows: Conversely, the ideal pole voltage should be as follows: , ( ) Thus, the voltage error can be given as follows: In order to realize soft-switching for the entire load range and maintain a low auxiliary current, the ARSI operates in two modes of heavy load mode (HLM) and light load mode (LLM), as determined by the load condition [22].In the heavy load condition, the auxiliary circuit is only operated once in each switching period, thus achieving auxiliary ZVS (AZVS) of a set of switches.The other set of switches can achieve natural ZVS (NZVS) without the operation of auxiliary circuit.In the light load condition, the auxiliary circuit is operated twice in each switching period.Therefore, all the switches achieve AZVS.
The operating principle of the ARSI is introduced in [22].The detailed dead-time effect of LLM and HLM will be analyzed in the case of positive load current as follows.When the load current is negative, the operation is similar.
To analyze the circuit, we assume that (1) All components and devices are ideal; (2) The gate signals of the MOSFETs are ideal square-wave; (3) The output inductor L o is high enough to be a constant current source.

Heavy Load Condition
In the heavy load condition, "AZVS + NZVS," namely achieving AZVS of a set of switches and NZVS of the other set of switches, is realized.One switching cycle of the operating waveforms are shown in Figure 2, where v ds is the drain-source voltage of a MOSFET, i d is the drain current of a MOSFET, v g is the actual gate signal with dead-time, v g,id is the ideal gate signal, i Lr is the resonant inductor current, v ab is the actual pole voltage across the load with dead-time, v ab,id is the ideal pole voltage across the load and v err is the voltage error between v ab and v ab,id .
During the dead-time t H1 -t H3 , the resonant capacitors first resonate with the load inductor.Owing to the positive load current, C r2 and C r3 are discharged and C r1 and C r4 are charged.After C r2 and C r3 are discharged to zero-voltage at t H2 , the body diodes D 2 and D 3 conduct the current and then the voltage is clamped to zero.Thus, S 2 and S 3 can be turned on at the ZVS condition.Regarding the dead-time t H1 -t H3 , it consists of the resonant stage and diode clamping stage.The dead-time causes the pole voltage error.As for the ARSI, the voltage error only occurs in the resonant stage, which is caused by the finite rise-and fall-times of the voltage.
During the resonant stage t H1 -t H2 , the actual pole voltage can be obtained as follows: Conversely, the ideal pole voltage should be as follows: Thus, the voltage error can be given as follows:  For Equation ( 1) vab(t) = −Vs, the resonant time can be obtained: Regarding the next commutation, Sr1 is turned on at tH4 to charge the resonant inductor, so that the switch current reverses at tH5.Therefore, after S2 and S3 are turned off at tH6, the resonant capacitors can resonate with the resonant inductor, which discharges Cr1 and Cr4 to zero-voltage at tH7.Subsequently, the body diodes D1 and D4 conduct the current.Thus, S1 and S4 can be zero-voltage turned on at tH8.Regarding the dead-time tH6-tH8, it also consists of the resonant stage and diode clamping stage.Only the resonant stage tH6-tH7 brings about the dead-time effect, which is caused by the finite rise-and fall-times.Some equations can be given as follows during the resonant stage.For Equation (1) v ab (t) = −V s , the resonant time can be obtained: Regarding the next commutation, S r1 is turned on at t H4 to charge the resonant inductor, so that the switch current reverses at t H5 .Therefore, after S 2 and S 3 are turned off at t H6 , the resonant capacitors can resonate with the resonant inductor, which discharges C r1 and C r4 to zero-voltage at t H7 .Subsequently, the body diodes D 1 and D 4 conduct the current.Thus, S 1 and S 4 can be zero-voltage turned on at t H8 .Regarding the dead-time t H6 -t H8 , it also consists of the resonant stage and diode clamping stage.Only the resonant stage t H6 -t H7 brings about the dead-time effect, which is caused by the finite rise-and fall-times.Some equations can be given as follows during the resonant stage.
The initial resonant condition is given as follows: i Lr (t H6 ) = I Lrm (12) According to Equations ( 5)-( 12), the inductor current and drain-source voltages of the main MOSFETs can be obtained as follows: where , Z A = L r C r , and I Lrm is the initial resonant inductor current.The pole voltage can be obtained as follows: where I boost1 is the switch current at the initial resonant time The ideal pole voltage, on the other hand, should be as follows: The voltage error during the resonant stage t H6 -t H7 can be calculated as follows: For Equation ( 16) v ab (t) = V s , the resonant time can be obtained: According to the analysis of dead-time effect in the heavy load condition, the voltage error in a switching cycle can be obtained from Equations ( 3) and ( 18): Thus, the average voltage error in a switching cycle can be calculated as follows: where T s is the switching period.

Light Load Condition
When the load current is low, the resonant capacitors cannot be discharged to zero-voltage during the dead-time.NZVS of S 2 and S 3 fails [22].Therefore, the auxiliary circuit is operated to achieve AZVS of S 2 and S 3 .One switching cycle of the operating waveforms in the LLM is shown in Figure 3.
Thus, the average voltage error in a switching cycle can be calculated as follows: where Ts is the switching period.

Light Load Condition
When the load current is low, the resonant capacitors cannot be discharged to zero-voltage during the dead-time.NZVS of S2 and S3 fails [22].Therefore, the auxiliary circuit is operated to achieve AZVS of S2 and S3.One switching cycle of the operating waveforms in the LLM is shown in Figure 3.  Before t L2 , S r2 is turned on to charge the resonant inductor L r , thus increasing the switch current.After S 1 and S 4 are turned off at t L2 , the resonant capacitors resonate with the resonant inductor.Due to the higher switch current, C r2 and C r3 can be discharged to zero-voltage.Thus, S 2 and S 3 can be turned on at the ZVS condition.The voltage error also only occurs in the resonant stage t L2 -t L3 .This resonant stage is similar to the stage t H6 -t H7 in Figure 2. The same equations can be obtained as Equations ( 5)-( 9).However, the initial resonant conditions are different as follows: Therefore, the inductor current and drain-source voltages of the main MOSFETs can be obtained as follows according to Equations ( 5)-( 9) and ( 22)-( 24): where I boost2 is the switch current at the initial resonant time I boost2 = I Lrm2 + i o Thus, the actual pole voltage can be calculated as follows, whereas the ideal pole voltage is: The voltage error caused by the resonant stage can be calculated as follows: For Equation (28) v ab (t) = −V s , the resonant time can be obtained: Regarding the dead-time t L8 -t L10 , the principle is the same as t H6 -t H8 in the heavy load condition, which is caused by the rise-and fall-times of the pole voltage.Therefore, the voltage error and the resonant time can be obtained: where I boost3 is the switch current at the initial resonant time The voltage error in a switching cycle can be obtained from Equations ( 30) and (32) in the light load condition: Thus, the average voltage error in a switching cycle can be calculated as follows:

Compared with the Hard-Switching Inverter
According to the analysis in Section 2.1, the essential principle of ZVS both in the light and heavy load condition is that the resonant capacitors that are parallelly connected to the next turn-on switches are discharged to zero-voltage and then the body diodes conduct the current.Thus, the switches can be turned on with zero-voltage.The dead-time consists of the resonant stage and diode clamping stage.However, the dead-time effect only exists in the resonant stage, which is caused by the finite rise-and fall-times of the voltage.Figure 4 shows the dead-time effect of a single pole, S 1 and S 3 , both in the HLM and LLM where v a is the actual pole voltage and v a,id is the ideal pole voltage.In order to summarize the dead-time effect both in the HLM and LLM, all the rise-and fall-times are considered to be linearly changed in Figure 4.
Thus, the average voltage error in a switching cycle can be calculated as follows:

Compared with the Hard-Switching Inverter
According to the analysis in Section 2.1, the essential principle of ZVS both in the light and heavy load condition is that the resonant capacitors that are parallelly connected to the next turn-on switches are discharged to zero-voltage and then the body diodes conduct the current.Thus, the switches can be turned on with zero-voltage.The dead-time consists of the resonant stage and diode clamping stage.However, the dead-time effect only exists in the resonant stage, which is caused by the finite rise-and fall-times of the voltage.Figure 4 shows the dead-time effect of a single pole, S1 and S3, both in the HLM and LLM where va is the actual pole voltage and va,id is the ideal pole voltage.In order to summarize the dead-time effect both in the HLM and LLM, all the rise-and fall-times are considered to be linearly changed in Figure 4.As for the hard-switching inverter, the dead-time effect is different from that of the ARSI.To analyze the dead-time effect, the assumption is the same as that of the ARSI. Figure 5 shows the operating stages and key waveforms of the hard-switching inverter with a single pole.
Regarding the dead-time t1-t3, the body diode D3 conducts the current after S1 is turned off at t1.The actual pole voltage is clamped to zero, which equals the ideal pole voltage.As for the dead-time t4-t6, the current is diverted from S3 to its body diode D3 rather than D1 after the S3 is turned off, because of the positive load current.The pole voltage is clamped to zero, whereas the ideal pole voltage is Vs.Therefore, the voltage loss occurs during the dead-time t4-t6.Only after S1 is turned on can the current be diverted to S1.The dead-time causes voltage loss when the output current is positive.However, when the output current is negative, the dead-time leads to voltage gain.
The dead-time effect of the hard-switching inverter is related to the output current polarity, which causes the blanking delay error, whereas the dead-time effect of the ARSI has no relation to the current polarity.Only the rise-and fall-error occurs in the ARSI, rather than the blanking delay error.Essentially, the voltage error caused by the finite commutation time of the voltage also occurs in the hard-switching inverter due to the junction capacitances of the switches.However, compared with blanking delay error, this error can be neglected.Regarding the ARSI, the lower the resonant As for the hard-switching inverter, the dead-time effect is different from that of the ARSI.To analyze the dead-time effect, the assumption is the same as that of the ARSI. Figure 5 shows the operating stages and key waveforms of the hard-switching inverter with a single pole.
Regarding the dead-time t 1 -t 3 , the body diode D 3 conducts the current after S 1 is turned off at t 1 .The actual pole voltage is clamped to zero, which equals the ideal pole voltage.As for the dead-time t 4 -t 6 , the current is diverted from S 3 to its body diode D 3 rather than D 1 after the S 3 is turned off, because of the positive load current.The pole voltage is clamped to zero, whereas the ideal pole voltage is V s .Therefore, the voltage loss occurs during the dead-time t 4 -t 6 .Only after S 1 is turned on can the current be diverted to S 1 .The dead-time causes voltage loss when the output current is positive.However, when the output current is negative, the dead-time leads to voltage gain.
The dead-time effect of the hard-switching inverter is related to the output current polarity, which causes the blanking delay error, whereas the dead-time effect of the ARSI has no relation to the current polarity.Only the rise-and fall-error occurs in the ARSI, rather than the blanking delay error.Essentially, the voltage error caused by the finite commutation time of the voltage also occurs in the hard-switching inverter due to the junction capacitances of the switches.However, compared with blanking delay error, this error can be neglected.Regarding the ARSI, the lower the resonant capacitances, the smaller the voltage error.The dead-time effect can be fully eliminated if the resonant capacitances are zero and the junction capacitances are not considered.

Compensation Method
In the HLM, the ZVS realization of the main switches is "AZVS + NZVS."In the LLM, the ZVS realization is "AZVS + AZVS."To distinguish the HLM and LLM, the threshold current Ith is used, which is given as follows.
2 r s th dead When the magnitude of the load current is lower than Ith, the load current cannot discharge the resonant capacitors to zero-voltage.Thus, the ARSI operates in LLM.When the magnitude of the load current is higher than Ith, the HLM is adopted.Table 1 shows the realization type of ZVS from zero load to full load.The ARSI can reduce the switching loss, whereas the conduction loss is increased due to the auxiliary current.To maintain a low conduction loss, the auxiliary current should be as low as possible.Thus, the initial resonant current Iboost is controlled to be constant from zero load to full load as follows.

Compensation Method
In the HLM, the ZVS realization of the main switches is "AZVS + NZVS."In the LLM, the ZVS realization is "AZVS + AZVS."To distinguish the HLM and LLM, the threshold current I th is used, which is given as follows.
When the magnitude of the load current is lower than I th , the load current cannot discharge the resonant capacitors to zero-voltage.Thus, the ARSI operates in LLM.When the magnitude of the load current is higher than I th , the HLM is adopted.Table 1 shows the realization type of ZVS from zero load to full load.The ARSI can reduce the switching loss, whereas the conduction loss is increased due to the auxiliary current.To maintain a low conduction loss, the auxiliary current should be as low as possible.Thus, the initial resonant current I boost is controlled to be constant from zero load to full load as follows.
The dead-time effect in the case of positive output current is introduced in Section 2.1.When the output current is negative, the dead-time effect is similar.Therefore, the voltage error caused by the dead-time can be obtained based on Equations ( 21), ( 35) and (37): The voltage error is related to the resonant time.Due to the same I boost , the voltage error is zero in the LLM.As for the HLM, the voltage error occurs because the resonant time is adaptively related to the output current to achieve NZVS, whereas the commutation time to achieve AZVS is constant.
Due to the dead-time effect, a voltage error occurs between the actual pole voltage and ideal pole voltage.The ARSI can be modeled as a proportional gain K pwm without consideration of delays.K pwm is the ratio between the DC voltage and peak value of the carrier in the PWM modulator.The reference voltage v c is amplified K pwm , thus obtaining the ideal pole voltage v ab,id .The actual pole voltage can be obtained by adding the voltage error v err .Figure 6 shows the transfer function of the ARSI.
The dead-time effect in the case of positive output current is introduced in Section 2.1.When the output current is negative, the dead-time effect is similar.Therefore, the voltage error caused by the dead-time can be obtained based on Equations ( 21 The voltage error is related to the resonant time.Due to the same Iboost, the voltage error is zero in the LLM.As for the HLM, the voltage error occurs because the resonant time is adaptively related to the output current to achieve NZVS, whereas the commutation time to achieve AZVS is constant.
Due to the dead-time effect, a voltage error occurs between the actual pole voltage and ideal pole voltage.The ARSI can be modeled as a proportional gain Kpwm without consideration of delays.Kpwm is the ratio between the DC voltage and peak value of the carrier in the PWM modulator.The reference voltage vc is amplified Kpwm, thus obtaining the ideal pole voltage vab,id.The actual pole voltage can be obtained by adding the voltage error verr.Figure 6 shows the transfer function of the ARSI.The output current can be calculated as follows.
, 1 1 where the actual voltage The voltage error caused by the dead-time effect is considered as a disturbance in the ARSI.To compensate the voltage error, the feedforward method can be utilized, which is shown in Figure 7.After the feedforward compensation is utilized, the output current can be calculated as follows.The output current can be calculated as follows.
where the actual voltage v ab,id = K pwm v c .The voltage error caused by the dead-time effect is considered as a disturbance in the ARSI.To compensate the voltage error, the feedforward method can be utilized, which is shown in Figure 7.
The dead-time effect in the case of positive output current is introduced in Section 2.1.When the output current is negative, the dead-time effect is similar.Therefore, the voltage error caused by the dead-time can be obtained based on Equations ( 21 The voltage error is related to the resonant time.Due to the same Iboost, the voltage error is zero in the LLM.As for the HLM, the voltage error occurs because the resonant time is adaptively related to the output current to achieve NZVS, whereas the commutation time to achieve AZVS is constant.
Due to the dead-time effect, a voltage error occurs between the actual pole voltage and ideal pole voltage.The ARSI can be modeled as a proportional gain Kpwm without consideration of delays.Kpwm is the ratio between the DC voltage and peak value of the carrier in the PWM modulator.The reference voltage vc is amplified Kpwm, thus obtaining the ideal pole voltage vab,id.The actual pole voltage can be obtained by adding the voltage error verr.Figure 6 shows the transfer function of the ARSI.The output current can be calculated as follows.
, 1 1 where the actual voltage The voltage error caused by the dead-time effect is considered as a disturbance in the ARSI.To compensate the voltage error, the feedforward method can be utilized, which is shown in Figure 7.After the feedforward compensation is utilized, the output current can be calculated as follows.After the feedforward compensation is utilized, the output current can be calculated as follows.
According to Equations ( 39) and (40), the dead-time effect can be eliminated by using the proposed compensation method theoretically.

Simulation and Experiment
The proposed compensation method was implemented in the Altera Cyclone IV FPGA of a digitally controlled ARSI prototype using the parameters listed in Table 2. Figure 8 shows the photograph of the prototype, which consists of a FPGA (Altera Corporation EP4CE22E22C7N) control board, a switching power supply, a MOSFET driver and a power circuit.In addition, the method is also verified in the simulation using Saber.According to Equations ( 39) and (40), the dead-time effect can be eliminated by using the proposed compensation method theoretically.

Simulation and Experiment
The proposed compensation method was implemented in the Altera Cyclone IV FPGA of a digitally controlled ARSI prototype using the parameters listed in Table 2. Figure 8 shows the photograph of the prototype, which consists of a FPGA (Altera Corporation EP4CE22E22C7N) control board, a switching power supply, a MOSFET driver and a power circuit.In addition, the method is also verified in the simulation using Saber.Figure 9 shows the open-loop control diagram of the ARSI with proposed dead-time effect compensation.FPGA samples the output current in each switching cycle.Then the mode judgement is completed according to Table 1.The voltage error can be calculated from Equation (38).Therefore, the voltage error can be compensated in the reference voltage.As for the auxiliary current control, the on-time of the auxiliary switches can be calculated after the mode judgement.Finally, the gate signals of the switches can be generated from the compensated reference voltage and the on-time of the auxiliary switches.
The compensation method is based on the model of the voltage error.The more accurate the model, the more precise the compensation result.Figure 10 shows the calculated voltage error vs. output current according to Equation (38).The voltage error only occurs in the HLM.A voltage error about 1.2 V occurs at the threshold current 3A.As the output current increases, the voltage error decreases first before increasing.Figure 9 shows the open-loop control diagram of the ARSI with proposed dead-time effect compensation.FPGA samples the output current in each switching cycle.Then the mode judgement is completed according to Table 1.The voltage error can be calculated from Equation (38).Therefore, the voltage error can be compensated in the reference voltage.As for the auxiliary current control, the on-time of the auxiliary switches can be calculated after the mode judgement.Finally, the gate signals of the switches can be generated from the compensated reference voltage and the on-time of the auxiliary switches.
The compensation method is based on the model of the voltage error.The more accurate the model, the more precise the compensation result.Figure 10 shows the calculated voltage error vs. output current according to Equation (38).The voltage error only occurs in the HLM.A voltage error about 1.2 V occurs at the threshold current 3A.As the output current increases, the voltage error decreases first before increasing.11 shows the resonant time vs. the switching current both in the calculation and simulation, where the switching current of AZVS is Iboost and the switching current of NZVS is io.The resonant time of AZVS is nonlinear related to the switching current.When the switching current is high enough, the resonant time of AZVS is close to that of NZVS.The calculation of the resonant time is in good agreement with the simulation results, which is related to the voltage error.
Figure 12 shows the output voltage and current of the hard-switching inverter when the modulation index is 0.4 in an open-loop configuration.To measure the output voltage vo, a filter is added to attenuate the carrier harmonics of the pole voltage vab.A serious distortion occurs both in the output current and voltage due to the long dead-time of 0.5 μs.   Figure 11 shows the resonant time vs. the switching current both in the calculation and simulation, where the switching current of AZVS is Iboost and the switching current of NZVS is io.The resonant time of AZVS is nonlinear related to the switching current.When the switching current is high enough, the resonant time of AZVS is close to that of NZVS.The calculation of the resonant time is in good agreement with the simulation results, which is related to the voltage error.
Figure 12 shows the output voltage and current of the hard-switching inverter when the modulation index is 0.4 in an open-loop configuration.To measure the output voltage vo, a filter is added to attenuate the carrier harmonics of the pole voltage vab.A serious distortion occurs both in the output current and voltage due to the long dead-time of 0.5 μs. Figure 11 shows the resonant time vs. the switching current both in the calculation and simulation, where the switching current of AZVS is I boost and the switching current of NZVS is i o .The resonant time of AZVS is nonlinear related to the switching current.When the switching current is high enough, the resonant time of AZVS is close to that of NZVS.The calculation of the resonant time is in good agreement with the simulation results, which is related to the voltage error.
Figure 12 shows the output voltage and current of the hard-switching inverter when the modulation index is 0.4 in an open-loop configuration.To measure the output voltage v o , a filter is added to attenuate the carrier harmonics of the pole voltage v ab .A serious distortion occurs both in the output current and voltage due to the long dead-time of 0.5 µs.The auxiliary circuit is operated twice with bidirectional current in a switching cycle in the LLM.An obvious distortion occurs in the output voltage at the mode switching point.However, the distortion of the output current and voltage is less than that of the hard-switching inverter in Figure 12, owing to the absence of blanking delay error in the ARSI. Figure 13b shows the voltage error between the actual output voltage and ideal output voltage.The simulation results are in good agreement with the calculation results in Figure 10 without consideration of the ripple.The maximum voltage error is about 2 V and occurs at the mode switching point.Figure 17 shows the magnitudes of the 2nd-10th harmonic components with respect to the fundamental component in the output voltage and current.The power analysis module DPO4PWR is used to analyze the total harmonic distortions (THDs) of the current and voltage.Figure 17a demonstrates that THD of the output voltage with the compensation method is 3.48% which is less than 6.29% than without dead-time effect compensation.The magnitudes of the 2nd-10th harmonics are reduced, except for the 8th harmonic.Figure 17b indicates that THD of the output current is reduced from 1.57% to 0.712% by using the proposed compensation method.Figure 17 shows the magnitudes of the 2nd-10th harmonic components with respect to the fundamental component in the output voltage and current.The power analysis module DPO4PWR is used to analyze the total harmonic distortions (THDs) of the current and voltage.Figure 17a demonstrates that THD of the output voltage with the compensation method is 3.48% which is less than 6.29% than without dead-time effect compensation.The magnitudes of the 2nd-10th harmonics are reduced, except for the 8th harmonic.Figure 17b indicates that THD of the output current is reduced from 1.57% to 0.712% by using the proposed compensation method.Figure 17 shows the magnitudes of the 2nd-10th harmonic components with respect to the fundamental component in the output voltage and current.The power analysis module DPO4PWR is used to analyze the total harmonic distortions (THDs) of the current and voltage.Figure 17a demonstrates that THD of the output voltage with the compensation method is 3.48% which is less than 6.29% than without dead-time effect compensation.The magnitudes of the 2nd-10th harmonics are reduced, except for the 8th harmonic.Figure 17b indicates that THD of the output current is reduced from 1.57% to 0.712% by using the proposed compensation method.Figure 18 shows the experimental voltage and current THDs under different load conditions.As the modulation index increases, the THDs of the output voltage and current both decrease.Through using the dead-time compensation strategy, the THDs of the output voltage and current are clearly reduced.

Conclusions
In this paper, the dead-time effect of a typical zero-voltage-switching (ZVT) inverter-the auxiliary resonant snubber inverter (ARSI)-is analyzed.The ARSI can fully eliminate the blanking delay error which is the main drawback of the hard-switching inverter.Only the rise-and fall-error caused by the resonant capacitors occurs in the ARSI, which is not considered in the hard-switching inverter.In the simulation and experiment, the quality of the output in the ARSI is significantly better than that in the hard-switching inverter, even if the dead-time compensation strategy is not used.
Furthermore, a feed-forward compensation method based on the voltage error estimation is proposed to compensate the rise-and fall-error of dead-time effect.Both the simulation and experimental results show that the compensation strategy can effectively reduce the THDs of the outputs.

Conclusions
In this paper, the dead-time effect of a typical zero-voltage-switching (ZVT) inverter-the auxiliary resonant snubber inverter (ARSI)-is analyzed.The ARSI can fully eliminate the blanking delay error which is the main drawback of the hard-switching inverter.Only the rise-and fall-error caused by the resonant capacitors occurs in the ARSI, which is not considered in the hard-switching inverter.In the simulation and experiment, the quality of the output in the ARSI is significantly better than that in the hard-switching inverter, even if the dead-time compensation strategy is not used.
Furthermore, a feed-forward compensation method based on the voltage error estimation is proposed to compensate the rise-and fall-error of dead-time effect.Both the simulation and experimental results show that the compensation strategy can effectively reduce the THDs of the outputs.

Figure 2 .
Figure 2. Key waveforms of the the auxiliary resonant snubber inverter (ARSI) in the heavy load condition.

Figure 2 .
Figure 2. Key waveforms of the the auxiliary resonant snubber inverter (ARSI) in the heavy load condition.

Figure 3 .
Figure 3. Key waveforms of the ARSI in the light load condition.Figure 3. Key waveforms of the ARSI in the light load condition.

Figure 3 .
Figure 3. Key waveforms of the ARSI in the light load condition.Figure 3. Key waveforms of the ARSI in the light load condition.

Figure 4 .
Figure 4. Dead-time effect of the ARSI.

Figure 4 .
Figure 4. Dead-time effect of the ARSI.

Figure 5 .
Figure 5. Dead-time effect of hard-switching inverter with single pole (a) the operating stages when io > 0; (b) the key waveforms when io > 0; (c) the key waveforms when io < 0.

Figure 5 .
Figure 5. Dead-time effect of hard-switching inverter with single pole (a) the operating stages when i o > 0; (b) the key waveforms when i o > 0; (c) the key waveforms when i o < 0.

Figure 6 .
Figure 6.Transfer function of the ARSI.

Figure 7 .
Figure 7. Transfer function of the ARSI with feedforward compensation.

Figure 6 .
Figure 6.Transfer function of the ARSI.

Figure 6 .
Figure 6.Transfer function of the ARSI.

Figure 7 .
Figure 7. Transfer function of the ARSI with feedforward compensation.

Figure 7 .
Figure 7. Transfer function of the ARSI with feedforward compensation.

Figure 8 .
Figure 8. Photograph of the prototype.

Figure 8 .
Figure 8. Photograph of the prototype.

Figure 9 .
Figure 9. Open-loop control diagram of the ARSI with proposed dead-time effect compensation.

Figure 10 .
Figure 10.Average voltage error vs. output current in the calculation

Figure
Figure 11  shows the resonant time vs. the switching current both in the calculation and simulation, where the switching current of AZVS is Iboost and the switching current of NZVS is io.The resonant time of AZVS is nonlinear related to the switching current.When the switching current is high enough, the resonant time of AZVS is close to that of NZVS.The calculation of the resonant time is in good agreement with the simulation results, which is related to the voltage error.Figure12shows the output voltage and current of the hard-switching inverter when the modulation index is 0.4 in an open-loop configuration.To measure the output voltage vo, a filter is added to attenuate the carrier harmonics of the pole voltage vab.A serious distortion occurs both in the output current and voltage due to the long dead-time of 0.5 μs.

Figure 9 .
Figure 9. Open-loop control diagram of the ARSI with proposed dead-time effect compensation.

Figure 9 .
Figure 9. Open-loop control diagram of the ARSI with proposed dead-time effect compensation.

Figure 10 .
Figure 10.Average voltage error vs. output current in the calculation

Figure 10 .
Figure 10.Average voltage vs. output current in the calculation.

Figure 11 .Figure 12 .
Figure 11.Resonant time vs. the switching current both in the calculation and simulation.

Figures 13 and 14 Figure 11 .
Figures13 and 14show the simulation and experimental results of ARSI without dead-time compensation, respectively, when the modulation index is 0.4 in an open-loop configuration.The auxiliary circuit is operated twice with bidirectional current in a switching cycle in the LLM.An obvious distortion occurs in the output voltage at the mode switching point.However, the distortion of the output current and voltage is less than that of the hard-switching inverter in Figure12, owing to the absence of blanking delay error in the ARSI.Figure13bshows the voltage error between the actual output voltage and ideal output voltage.The simulation results are in good agreement with

Figure 11 .Figure 12 .
Figure 11.Resonant time vs. the switching current both in the calculation and simulation.

Figures 13 and 14 Figure 12 .
Figures 13 and 14  show the simulation and experimental results of ARSI without dead-time compensation, respectively, when the modulation index is 0.4 in an open-loop configuration.The auxiliary circuit is operated twice with bidirectional current in a switching cycle in the LLM.An obvious distortion occurs in the output voltage at the mode switching point.However, the distortion of the output current and voltage is less than that of the hard-switching inverter in Figure12, owing to the absence of blanking delay error in the ARSI.Figure13bshows the voltage error between the actual output voltage and ideal output voltage.The simulation results are in good agreement with

Figures 13 and 14
Figures 13 and 14 show the simulation and experimental results of ARSI without dead-time compensation, respectively, when the modulation index is 0.4 in an open-loop configuration.The auxiliary circuit is operated twice with bidirectional current in a switching cycle in the LLM.An obvious distortion occurs in the output voltage at the mode switching point.However, the distortion of the output current and voltage is less than that of the hard-switching inverter in Figure12, owing to the absence of blanking delay error in the ARSI.Figure13bshows the voltage error between the actual output voltage and ideal output voltage.The simulation results are in good agreement with

Figure 13 .
Figure 13.Simulation waveforms of ARSI without dead-time compensation when the modulation index is 0.4 in an open-loop configuration.(a) simulation results; (b) voltage error.

Figure 14 .Figure 15 .Figure 13 .Figure 13 .
Figure 14.Experimental waveforms of ARSI without dead-time compensation when the modulation index is 0.4 in an open-loop configuration.Figures 15 and 16 show the simulation and experimental results, respectively, when the proposed compensation method is used in the ARSI.The output voltage distortion is reduced in Figures 15a and 16 without increasing the auxiliary current iLr. Figure 15b demonstrates that the voltage error is reduced.

Figure 14 .Figure 15 .Figure 14 .
Figure 14.Experimental waveforms of ARSI without dead-time compensation when the modulation index is 0.4 in an open-loop configuration.Figures 15 and 16 show the simulation and experimental results, respectively, when the proposed compensation method is used in the ARSI.The output voltage distortion is reduced in Figures 15a and 16 without increasing the auxiliary current iLr. Figure 15b demonstrates that the voltage error is reduced.

Figure 13 .
Figure 13.Simulation waveforms of ARSI without dead-time compensation when the modulation index is 0.4 in an open-loop configuration.(a) simulation results; (b) voltage error.

Figure 14 .Figure 15 .Figure 15 .
Figure 14.Experimental waveforms of ARSI without dead-time compensation when the modulation index is 0.4 in an open-loop configuration.Figures 15 and 16 show the simulation and experimental results, respectively, when the proposed compensation method is used in the ARSI.The output voltage distortion is reduced in Figures 15a and 16 without increasing the auxiliary current iLr. Figure 15b demonstrates that the voltage error is reduced.

Figure 16 .
Figure 16.Experimental waveforms of ARSI with dead-time compensation when the modulation index is 0.4 in an open-loop configuration.

Figure 17 .Figure 16 .
Figure 17.Magnitudes of the 2nd-10th harmonic components in respect to the fundamental component (a) output voltage; (b) output current.

Figure 16 .
Figure 16.Experimental waveforms of ARSI with dead-time compensation when the modulation index is 0.4 in an open-loop configuration.

Figure 17 .Figure 17 .
Figure 17.Magnitudes of the 2nd-10th harmonic components in respect to the fundamental component (a) output voltage; (b) output current.

Figure 18 Figure 18 .
Figure18shows the experimental voltage and current THDs under different load conditions.As the modulation index increases, the THDs of the output voltage and current both decrease.Through using the dead-time compensation strategy, the THDs of the output voltage and current are clearly reduced.

Figure 18 .
Figure 18.Experimental and current THDs under different load condition (a) voltage THD; (b) current THD.

Table 1 .
Realization type of ZVS from zero load to full load.

Table 1 .
Realization type of ZVS from zero load to full load.

Table 2 .
Parameters of the circuit.

Table 2 .
Parameters of the circuit.