Real-Time Method and Implementation of Head-Wave Extraction for Ultrasonic Imaging While Drilling

: Extracting head waves and subsequently uploading their results from the downhole to the surface system in real time could improve the real-time guidance of ultrasonic imaging logging while drilling (UILWD) for drilling operations. To realize the downhole real-time extraction of head waves in this logging, three aspects were explored in this study. First, an improved energy ratio head-wave arrival extraction algorithm based on the weighting coefficients and characteristic functions, along with an amplitude detection method relying on peak-to-peak values, was proposed. Second, an echo reception pre-processing analog circuit and a digital signal processing circuit based on FPGA were designed. A pipeline algorithm was developed in FPGA to extract the arrival time and amplitude of the head wave. Finally, software simulations, laboratory tests, and field experiments related to this method were conducted. Our results showed that the real-time head-wave extraction method demonstrated a strong anti-noise ability in real time. The maximum relative error of the arrival time was less than 5%. The relative error of the amplitude was acceptable, and 90% of this value was within 5%. Through the measurement, the time of processing a single-channel waveform by a downhole algorithm was less than 15 ms, thus meeting the requirements for the real-time processing of downholes.


Introduction
Ultrasonic imaging logging is an effective method that is commonly used in oil-gas exploration and development.This method uses ultrasonic transducers to detect wellbore media in a self-transmission and reception manner, and this logging can then accurately identify and measure the wellbore diameter, assess the shape and potential development of wellbore cavities and fractures in the open hole, and also evaluate casing damage and cementing quality in cased holes [1][2][3][4][5].Wireline ultrasonic logging is relatively widely used, such as CAST, UBI, MUST, and MUIL [6,7].
Compared with the wireline method, ultrasonic imaging logging while drilling (UILWD) can obtain formation data more accurately.The tool developed by our group comprises three ultrasonic transducers distributed with a circumferential interval of 120 • , effectively ensuring the optimal imaging resolution of the borehole wall.However, the amount of data acquisition per second is up to 6 MB and cannot be uploaded to the surface system in real time.The tool can only work as downhole storage and move data to the surface system (once back to the surface) for further processing.However, this method cannot provide the user with timely information related to borehole wall abnormalities so as to ensure drilling safety and does not have the advantages of drilling and logging integration [8,9].Consequently, a possible solution to this problem could be to use the working mode of processing echo signals in a downhole tool in real time and subsequently upload the extracted head-wave results only after storing all the data.
Currently, there are two methods for achieving head-wave extraction-the downhole analogue circuit method and the surface computer software method.The former includes special circuits for determining the arrival time and peaks of the head wave, which are widely used in conventional acoustic logging tools [10,11].Although this method is simple and has a fast response time, it is considerably affected by various factors, such as the temperature, drilling noise, mud density, and wellbore lithology, which may render threshold level determination difficult and also lead to low accuracy or even detection failure missing detection in UILWD.There are many algorithms for calculating the arrival time and amplitude of the head wave in the surface computer software method.According to the information used, head-wave arrival time extraction methods can be divided into three types.The first type is based on the instantaneous form of waveform recording, such as the short-term to long-term average (STA/LTA) method proposed by Stevenson et al. and the improved energy ratio algorithm published by other scholars [12][13][14][15].However, despite the fact that this method has good response sensitivity and occupies less hardware resources, it is sensitive to noise and also works poorly with data that have a low signal-to-noise ratio (SNR).The second type uses the overall waveform recording form, such as the cross-correlation method of adjacent waveforms, the autoregressive arrival detection method and the AIC algorithm based on statistical laws [15][16][17].This method has a certain anti-noise ability, but the processing result is poor when dealing with complex waveform recording forms.Finally, the third type utilizes multi-dimensional information recorded in waveforms, such as the arrival time detection method based on an artificial neural network, wavelet transform, and fractal dimension [18][19][20].Although this approach can suppress noise and improve the accuracy of head-wave extraction, it is a rather complex and inefficient method.The head-wave amplitude detection mainly involves peak-to-peak, main-frequency amplitude, and envelope amplitude methods [21].These algorithms are based on post-measurement processing methods in the surface computer but offer limited real-time guidance while drilling.
Recently, downhole digital signal processing has emerged as a promising solution because it can overcome the disadvantages of the poor stability and low accuracy of the analog circuit method but also provide real-time guidance while drilling [22][23][24].After the UILWD echo signal is digitized in the downhole, head-wave information data can be extracted according to the difference between the useful signal and ambient noise.Then, the extracted result needs to be simply uploaded to the surface.This method reduces the amount of uploaded data and also ensures the real-time surface observation of borehole conditions.Thus, it is beneficial to the integration of drilling and logging operations.The amount of computation for head-wave extraction is large, thereby necessitating a certain amount of logic resources and a high processing speed.FPGA has rich logic gate resources and supports hardware parallel operation.It can also meet the requirements set by the algorithm and ensure the real-time performance of downhole data processing.Li et al. developed a two-branch hybrid framework for LWD sonic logging to predict hydratebearing sediments based on existing logging data.One branch based on the seismic rock physics model is used to generate the background elastic wave velocity profile, and the other deep learning branch is used to compensate for the residual between the actual observations and the branch output of the physical model.The hybrid model improves the prediction accuracy of the physical process model.The method can be extended to apply appropriate inputs and physical models to predict other types of logging or reservoir parameters [25,26].It provides a new reference for the feature extraction of UILWD data.
The paper concerns the formulation of an algorithm for signal analysis in the time domain.The subject of the paper is the issues of identifying specific features of the recorded pulse signal, taking into account interference and low signal quality.On the basis of previous studies, an improved energy ratio head-wave arrival extraction algorithm, which is based on the weighting coefficient and characteristic function, and an amplitude detection method based on peak-to-peak values are proposed herein.An echo reception pre-processing analog circuit and a digital signal processing circuit based on FPGA are designed to realize a pipeline algorithm that can measure the arrival time and amplitude extraction of head waves.Software simulations, laboratory tests, and field experiments related to this method are also conducted to validate the performance and efficiency of the method.

Digital Extraction Method of Echo Head Waves
The improved energy ratio head-wave arrival extraction algorithm is based on the STA/LTA method.The STA/LTA method focuses on the time-domain characteristics of waveform recordings to detect the head wave using two types of information-the amplitude (energy) difference between the noise and echo signals and the notable change in signal energy before and after the arrival of the head wave.The expression of this method is shown in Equation (1), where R(n) is the average ratio of STA/LTA at the sample point n, LTAn and STAn are the average energies of long and short windows, respectively, NS and NL are the number of samples contained in short and long windows, respectively, i is the sample point number and x(i) represents the discrete waveform record.STAn quickly responds to waveform amplitude changes, unlike LTAn, whose response is much slower.Thus, the energy ratio STAn/LTAn can represent waveform amplitude changes.
In actual processing, R(n) is calculated by sliding the time window on the waveform record.When R(n) is greater than the preset threshold α, the echo signal is considered to have already arrived.However, in cases of echo signals with a poor SNR, setting α too low may result in false detection, whereas the opposite (setting α too high) may result in head waves being missed.The anti-noise performance of the algorithm can be improved by replacing the energy function with the characteristic function and introducing the weighted coefficient to calculate the mean ratio of both long and short windows [27].
According to the characteristics of FPGA, an improved long-short window energy ratio function Z(n) was defined (Equation ( 2)), which effectively combines the characteristic function method and the weighting coefficient method.The expression of CF(i) is shown in Equation (3).
Figure 1 demonstrates the effect of using either the STA/LTA method or the improved STA/LTA method to process a low-SNR UILWD echo signal.It can be seen that the response of the improved STA/LTA method to the reflected echo is greatly improved.Meanwhile, the response to the noise signal remains basically unchanged, thereby providing a broader threshold setting range for the algorithm while greatly improving its anti-noise ability.
In the peak-to-peak amplitude detection method, the amplitude is equal to the maximum peak of the echo signal minus the maximum trough value.The expression is shown in Equation ( 4), where Amp is the amplitude value and x(i) is the discrete waveform record.In the peak-to-peak amplitude detection method, the amplitude is equal to the maximum peak of the echo signal minus the maximum trough value.The expression is shown in Equation ( 4), where Amp is the amplitude value and x(i) is the discrete waveform record.

Hardware Design
To optimize the extraction of the head wave of the UILWD echo signal, a real-time head-wave extraction method was designed, consisting of two parts-echo reception preprocessing and echo digital signal processing based on FPGA.The former is mainly a hardware circuit, whereas the latter is mainly a processing algorithm.

Overall Design
The hardware principle of the echo head-wave real-time extraction is shown in the dotted line box in Figure 2. In this approach, FPGA is used as the processor of the echo digital signal processing.The remaining modules are used for pre-processing the echo signal reception and provide a high-SNR signal for FPGA to carry out the subsequent digital signal processing work.As the main controller of real-time head-wave extraction, FPGA realizes the following functions: (1) it extracts the head waves of the echo signal, (2) it sends the gain control command to the front-end control module in response to the amplitude information of

Hardware Design
To optimize the extraction of the head wave of the UILWD echo signal, a real-time head-wave extraction method was designed, consisting of two parts-echo reception preprocessing and echo digital signal processing based on FPGA.The former is mainly a hardware circuit, whereas the latter is mainly a processing algorithm.

Overall Design
The hardware principle of the echo head-wave real-time extraction is shown in the dotted line box in Figure 2. In this approach, FPGA is used as the processor of the echo digital signal processing.The remaining modules are used for pre-processing the echo signal reception and provide a high-SNR signal for FPGA to carry out the subsequent digital signal processing work.In the peak-to-peak amplitude detection method, the amplitude is equal to the maximum peak of the echo signal minus the maximum trough value.The expression is shown in Equation ( 4), where Amp is the amplitude value and x(i) is the discrete waveform record.

Hardware Design
To optimize the extraction of the head wave of the UILWD echo signal, a real-time head-wave extraction method was designed, consisting of two parts-echo reception preprocessing and echo digital signal processing based on FPGA.The former is mainly a hardware circuit, whereas the latter is mainly a processing algorithm.

Overall Design
The hardware principle of the echo head-wave real-time extraction is shown in the dotted line box in Figure 2. In this approach, FPGA is used as the processor of the echo digital signal processing.The remaining modules are used for pre-processing the echo signal reception and provide a high-SNR signal for FPGA to carry out the subsequent digital signal processing work.As the main controller of real-time head-wave extraction, FPGA realizes the following functions: (1) it extracts the head waves of the echo signal, (2) it sends the gain control command to the front-end control module in response to the amplitude information of As the main controller of real-time head-wave extraction, FPGA realizes the following functions: (1) it extracts the head waves of the echo signal, (2) it sends the gain control command to the front-end control module in response to the amplitude information of the head wave, (3) it controls the AD conversion module to convert the echo analog signal into a digital one, which is then entered into the FPGA, and (4) it communicates with other transmission and storage units, such as DSP and Flash.
The amplitude limitation protection module has two Zener diodes in a series that form a bidirectional limiting circuit.This module uses high-power resistors to limit the current and avoid the impact of transmitting high-voltage pulses on the receiver circuit.The programmable gain amplification module amplifies the echo signal to a reasonable range to anticipate potentially notable variations in the echo amplitude waveform recording due to different downhole conditions.The programmable gain control is then completed by the front-end control module, which uses CPLD as its controller.The gain of the programmable amplifier circuit is adjusted by the front-end control module based on the main control command from FPGA.A Butterworth filter was selected as the band-pass filter module, and a Sallen-key structure was used as the design unit, whose aim was to reduce the low-frequency environmental noise caused by drill collars and the high-frequency electromagnetic interference in the electronic circuit, respectively.The AD conversion module converts the filtered echo analog signal into a digital signal under the control of FPGA, which is then fed into the FPGA for the extraction of the head wave.
Figure 3 shows the design scheme of the analog band-pass filter circuit.In the actual circuit, in order to achieve the optimal filtering effect, three second-order filters are interactively cascaded with the amplifier circuit as independent design units, and the cascaded mode is resistance-capacitance coupling.into a digital one, which is then entered into the FPGA, and (4) it communicates with other transmission and storage units, such as DSP and Flash.
The amplitude limitation protection module has two Zener diodes in a series that form a bidirectional limiting circuit.This module uses high-power resistors to limit the current and avoid the impact of transmitting high-voltage pulses on the receiver circuit.The programmable gain amplification module amplifies the echo signal to a reasonable range to anticipate potentially notable variations in the echo amplitude waveform recording due to different downhole conditions.The programmable gain control is then completed by the front-end control module, which uses CPLD as its controller.The gain of the programmable amplifier circuit is adjusted by the front-end control module based on the main control command from FPGA.A Butterworth filter was selected as the band-pass filter module, and a Sallen-key structure was used as the design unit, whose aim was to reduce the low-frequency environmental noise caused by drill collars and the high-frequency electromagnetic interference in the electronic circuit, respectively.The AD conversion module converts the filtered echo analog signal into a digital signal under the control of FPGA, which is then fed into the FPGA for the extraction of the head wave.
Figure 3 shows the design scheme of the analog band-pass filter circuit.In the actual circuit, in order to achieve the optimal filtering effect, three second-order filters are interactively cascaded with the amplifier circuit as independent design units, and the cascaded mode is resistance-capacitance coupling.

Second-order active low-pass filter
Second-order active high-pass filter Second-order active low-pass filter The resonant frequency of the transducer used in the ultrasonic imaging logging tool is 250 kHz, and the signal sampling frequency is 2.5 MHz.Consequently, the band-pass filtering circuit is designed with a center frequency of 250 kHz, and the band-pass spans from 180 kHz to 320 kHz, with a bandwidth of 140 kHz.After the band-pass frequency is determined, the R (resistance) and C (capacitance) parameters in the filter circuit are calculated.The calculation results of the parameters are shown in Figure 4.The resonant frequency of the transducer used in the ultrasonic imaging logging tool is 250 kHz, and the signal sampling frequency is 2.5 MHz.Consequently, the band-pass filtering circuit is designed with a center frequency of 250 kHz, and the band-pass spans from 180 kHz to 320 kHz, with a bandwidth of 140 kHz.After the band-pass frequency is determined, the R (resistance) and C (capacitance) parameters in the filter circuit are calculated.The calculation results of the parameters are shown in Figure 4. into a digital one, which is then entered into the FPGA, and (4) it communicates with other transmission and storage units, such as DSP and Flash.
The amplitude limitation protection module has two Zener diodes in a series that form a bidirectional limiting circuit.This module uses high-power resistors to limit the current and avoid the impact of transmitting high-voltage pulses on the receiver circuit.The programmable gain amplification module amplifies the echo signal to a reasonable range to anticipate potentially notable variations in the echo amplitude waveform recording due to different downhole conditions.The programmable gain control is then completed by the front-end control module, which uses CPLD as its controller.The gain of the programmable amplifier circuit is adjusted by the front-end control module based on the main control command from FPGA.A Butterworth filter was selected as the band-pass filter module, and a Sallen-key structure was used as the design unit, whose aim was to reduce the low-frequency environmental noise caused by drill collars and the high-frequency electromagnetic interference in the electronic circuit, respectively.The AD conversion module converts the filtered echo analog signal into a digital signal under the control of FPGA, which is then fed into the FPGA for the extraction of the head wave.
Figure 3 shows the design scheme of the analog band-pass filter circuit.In the actual circuit, in order to achieve the optimal filtering effect, three second-order filters are interactively cascaded with the amplifier circuit as independent design units, and the cascaded mode is resistance-capacitance coupling.

Second-order active low-pass filter
Second-order active high-pass filter Second-order active low-pass filter The resonant frequency of the transducer used in the ultrasonic imaging logging tool is 250 kHz, and the signal sampling frequency is 2.5 MHz.Consequently, the band-pass filtering circuit is designed with a center frequency of 250 kHz, and the band-pass spans from 180 kHz to 320 kHz, with a bandwidth of 140 kHz.After the band-pass frequency is determined, the R (resistance) and C (capacitance) parameters in the filter circuit are calculated.The calculation results of the parameters are shown in Figure 4.

Programmable Gain Amplification Module
The programmable gain amplification module is a key component of echo reception pre-processing because it can efficiently adjust the amplitude of the echo signal to an appropriate range while improving the SNR. Figure 5 shows that our module comprises four submodules-pre-differential amplification, continuous gain amplification, two-stage amplification, and post-differential amplification.
The programmable gain amplification module is a key component of echo reception pre-processing because it can efficiently adjust the amplitude of the echo signal to an appropriate range while improving the SNR. Figure 5 shows that our module comprises four submodules-pre-differential amplification, continuous gain amplification, two-stage amplification, and post-differential amplification.In our design, we selected an instrument amplifier in the pre-differential amplification submodule to amplify the differential signal and subsequently convert it into a singleended one.The two-stage amplification submodule can amplify the signal by 0 or 30 dB under the control of an analog switch, which is used to expand the gain range of the programmable gain amplification module.The on-off of the analogue switch is controlled by CPLD.The post-differential amplification submodule converts the single-end signal into a differential one, which is then used for transmission, achieving high-performance ADC.
The continuous gain amplification submodule has AD603 as its core, and the gain is precisely controlled by a voltage, which can continuously change within a certain range.The control voltage is obtained after the front-end controller CPLD performs digital-toanalog conversion, operation, and filtering on the decoding result of the FPGA command.The operation circuit converts the 0-2.5 V voltage output from the DA conversion to the allowable input range (−500-500 mV) of the AD603 control voltage.The filter circuit uses a second-order active low-pass filter with a cut-off frequency of 112 kHz to filter out highfrequency noise.

Discussion
The software design for real-time head-wave extraction consisted of distinct parts: front-end control, digital filtering, and real-time head-wave extraction.All codes are written in the VHDL language.The front-end control program is implemented in CPLD, while the digital filtering and head-wave extraction program is implemented in FPGA by using a pipeline mode.

Front-End Control
Figure 6 illustrates the structure diagram of the front-end control program.The CPLD receives the serial command from FPGA and then performs serial-parallel conversion through the shift register group.After an eight-word command is received, it is analyzed by the command-parsing module to obtain programmable gain control and logic control data.On the one hand, the programmable gain control data are used to control the In our design, we selected an instrument amplifier in the pre-differential amplification submodule to amplify the differential signal and subsequently convert it into a single-ended one.The two-stage amplification submodule can amplify the signal by 0 or 30 dB under the control of an analog switch, which is used to expand the gain range of the programmable gain amplification module.The on-off of the analogue switch is controlled by CPLD.The post-differential amplification submodule converts the single-end signal into a differential one, which is then used for transmission, achieving high-performance ADC.
The continuous gain amplification submodule has AD603 as its core, and the gain is precisely controlled by a voltage, which can continuously change within a certain range.The control voltage is obtained after the front-end controller CPLD performs digital-toanalog conversion, operation, and filtering on the decoding result of the FPGA command.The operation circuit converts the 0-2.5 V voltage output from the DA conversion to the allowable input range (−500-500 mV) of the AD603 control voltage.The filter circuit uses a second-order active low-pass filter with a cut-off frequency of 112 kHz to filter out high-frequency noise.

Discussion
The software design for real-time head-wave extraction consisted of distinct parts: front-end control, digital filtering, and real-time head-wave extraction.All codes are written in the VHDL language.The front-end control program is implemented in CPLD, while the digital filtering and head-wave extraction program is implemented in FPGA by using a pipeline mode.

Front-End Control
Figure 6 illustrates the structure diagram of the front-end control program.The CPLD receives the serial command from FPGA and then performs serial-parallel conversion through the shift register group.After an eight-word command is received, it is analyzed by the command-parsing module to obtain programmable gain control and logic control data.On the one hand, the programmable gain control data are used to control the continuous gain of AD603, while on the other hand, the logic control data are used to select the direction of the analog switch in the two-stage amplification module.In practice, the programmable gain control module is designed by the Mealy state machine.During the excitation of the transducer, the program changes from the idle to the fixed, low-gain state, in which the gain of the programmable gain amplification module is −10 dB.When the counter is greater than the transmission duration, the gain control signal enters a linear growth state, and when the gain arrives at a predetermined value, the program enters the state of gain holding.The output gain remains unchanged until the receipt signal is over, and the program returns back to the idle state.

Digital Filtering
A finite impulse response (FIR) filter is used to filter out thermal and quantization noise in the circuit.FIR filtering is an efficient way to calculate the convolution of discrete signals and filter coefficients in the time domain.The calculation expression is shown in Equation (5), where x(i) is the original discrete signal, h(i) is the filter coefficient, y(i) is the filtered discrete signal, and N is the filter order.
In the present work, we used a single-rate type band-pass filter with a cut-off frequency of 180-320 kHz, an order of 46, and filter coefficients after rounding.Equation (5) shows that the implementation of the FIR filter involves the processes of shifting, multiplication, and accumulation, suggesting that its implementation in FPGA can be mainly divided into the three stages of the pipeline.The calculation process is shown in Figure 7, where the arrow represents the direction of the data flow, the black hollow circle represents x(i), the black solid circle represents h(i), the red hollow circle reflects the productterm of x(i) and h(i), and the red solid circle represents the output of the filter y(i).Since the filtering coefficient h(i) is symmetric, the y(i) calculation can be simplified as follows: first, the input x(i) is shifted by the shift register group in FPGA, and the original shifted signals are added symmetrically.Then, the calculation result of the adder output is fed into the multiplier, where it is multiplied by h(i).Finally, the product-term is added into the accumulator to calculate the filtering output.In practice, the programmable gain control module is designed by the Mealy state machine.During the excitation of the transducer, the program changes from the idle to the fixed, low-gain state, in which the gain of the programmable gain amplification module is −10 dB.When the counter is greater than the transmission duration, the gain control signal enters a linear growth state, and when the gain arrives at a predetermined value, the program enters the state of gain holding.The output gain remains unchanged until the receipt signal is over, and the program returns back to the idle state.

Digital Filtering
A finite impulse response (FIR) filter is used to filter out thermal and quantization noise in the circuit.FIR filtering is an efficient way to calculate the convolution of discrete signals and filter coefficients in the time domain.The calculation expression is shown in Equation (5), where x(i) is the original discrete signal, h(i) is the filter coefficient, y(i) is the filtered discrete signal, and N is the filter order.
In the present work, we used a single-rate type band-pass filter with a cut-off frequency of 180-320 kHz, an order of 46, and filter coefficients after rounding.Equation (5) shows that the implementation of the FIR filter involves the processes of shifting, multiplication, and accumulation, suggesting that its implementation in FPGA can be mainly divided into the three stages of the pipeline.The calculation process is shown in Figure 7, where the arrow represents the direction of the data flow, the black hollow circle represents x(i), the black solid circle represents h(i), the red hollow circle reflects the product-term of x(i) and h(i), and the red solid circle represents the output of the filter y(i).Since the filtering coefficient h(i) is symmetric, the y(i) calculation can be simplified as follows: first, the input x(i) is shifted by the shift register group in FPGA, and the original shifted signals are added symmetrically.Then, the calculation result of the adder output is fed into the multiplier, where it is multiplied by h(i).Finally, the product-term is added into the accumulator to calculate the filtering output.

Real-Time Head-Wave Extraction
To improve the operation efficiency and reduce the extraction time, Equation ( 2) can be rewritten into Equation (6).In this way, can also be calculated in parallel.The algorithm can be decomposed into multiple steps and accelerated by a pipeline mode.

( ) (
) Figure 8 demonstrates the program structure of head-wave extraction, which primarily comprises the shift register group, multipliers, accumulators, dividers, counters, comparators, and other modules.Each module cooperates with one another and processes data in a pipeline mode to extract the arrival time and amplitude of the head wave in real time.After the filtered 16-bit digital echo signal enters the FPGA's shift register, the FPGA starts to receive data and counts.When counting to the end of transducer excitation, the data-processing module starts operating.

Real-Time Head-Wave Extraction
To improve the operation efficiency and reduce the extraction time, Equation ( 2) can be rewritten into Equation (6).In this way,N 2 L /N 2 S can be set as a constant, which is then directly stored into the register, and x(i) 2 and x(i − 1)•x(i + 1) can also be calculated in parallel.The algorithm can be decomposed into multiple steps and accelerated by a pipeline mode.
Figure 8 demonstrates the program structure of head-wave extraction, which primarily comprises the shift register group, multipliers, accumulators, dividers, counters, comparators, and other modules.Each module cooperates with one another and processes data in a pipeline mode to extract the arrival time and amplitude of the head wave in real time.After the filtered 16-bit digital echo signal enters the FPGA's shift register, the FPGA starts to receive data and counts.When counting to the end of transducer excitation, the data-processing module starts operating.

Real-Time Head-Wave Extraction
To improve the operation efficiency and reduce the extraction time, Equation ( 2) can be rewritten into Equation (6).In this way, can also be calculated in parallel.The algorithm can be decomposed into multiple steps and accelerated by a pipeline mode.

( ) (
) Figure 8 demonstrates the program structure of head-wave extraction, which primarily comprises the shift register group, multipliers, accumulators, dividers, counters, comparators, and other modules.Each module cooperates with one another and processes data in a pipeline mode to extract the arrival time and amplitude of the head wave in real time.After the filtered 16-bit digital echo signal enters the FPGA's shift register, the FPGA starts to receive data and counts.When counting to the end of transducer excitation, the data-processing module starts operating.The parallel computation processes of short-and long-window energies are shown above and below the dotted line in Figure 6, respectively.Multiplier 11 and multiplier 21 are used to calculate, and multiplier 12 and multiplier 22 are used to calculate at the same time.The results of the above multipliers enter the corresponding accumulators and participate in the accumulation and summation operation.When the count reaches the window length, both short-and long-window subtractors perform subtraction operations on the corresponding accumulator output.Multiplier 13 and multiplier 23 perform square calculation on the output of the subtractor.A hardware divider is designed at the outlet of these two multipliers, which operates through data shift, comparison, and other steps for calculating the energy ratio between the short and the long window.
When the calculation result of the divider R(n) is greater than the threshold α, the current counter value corresponds to the arrival time of the head wave, which is then cached and output by the head-wave arrival register.At that time, the digital comparator is set to output a flag to enable the echo amplitude detection process.The echo amplitude comparator screens the peaks and troughs of the received waveform and then feeds the calculation result into the echo amplitude register.

Test and Analysis
As part of our analyses, we performed software simulations, laboratory tests, and field experiments to validate the performance and accuracy of our design.

Algorithm Simulation
Figure 9 presents the simulation results obtained by the head-wave extraction algorithm.As shown in Figure 9a, when the energy ratio (Ratio) is greater than α, the flag of the head-wave arrival (ArrFlag) is set to logic-high.The current counter represents the arrival time of the head wave, which is stored in ArrNum.In this case, the head-wave arrival time is the 184th sampling point.Figure 9b demonstrates the result of head-wave amplitude detection.The echo amplitude detection is completed once the amplitude output flag (Tx_Amplitude) is set, and in this case, the head-wave amplitude (AD value) is 31,753.The results of the arrival time and amplitude detection are consistent with the waveform of the acquired data, which is shown in Figure 9c, and the expected processing results, thereby indicating that the head-wave extraction algorithm based on FPGA is correct and can meet the downhole requirement.
Appl.Sci.2024, 14, x FOR PEER REVIEW 9 of 15 The parallel computation processes of short-and long-window energies are shown above and below the dotted line in Figure 6, respectively.Multiplier 11 and multiplier 21 are used to calculate, and multiplier 12 and multiplier 22 are used to calculate at the same time.The results of the above multipliers enter the corresponding accumulators and participate in the accumulation and summation operation.When the count reaches the window length, both short-and long-window subtractors perform subtraction operations on the corresponding accumulator output.Multiplier 13 and multiplier 23 perform square calculation on the output of the subtractor.A hardware divider is designed at the outlet of these two multipliers, which operates through data shift, comparison, and other steps for calculating the energy ratio between the short and the long window.
When the calculation result of the divider R(n) is greater than the threshold α, the current counter value corresponds to the arrival time of the head wave, which is then cached and output by the head-wave arrival register.At that time, the digital comparator is set to output a flag to enable the echo amplitude detection process.The echo amplitude comparator screens the peaks and troughs of the received waveform and then feeds the calculation result into the echo amplitude register.

Test and Analysis
As part of our analyses, we performed software simulations, laboratory tests, and field experiments to validate the performance and accuracy of our design.

Algorithm Simulation
Figure 9 presents the simulation results obtained by the head-wave extraction algorithm.As shown in Figure 9a, when the energy ratio (Ratio) is greater than α, the flag of the head-wave arrival (ArrFlag) is set to logic-high.The current counter represents the arrival time of the head wave, which is stored in ArrNum.In this case, the head-wave arrival time is the 184th sampling point.Figure 9b demonstrates the result of head-wave amplitude detection.The echo amplitude detection is completed once the amplitude output flag (Tx_Amplitude) is set, and in this case, the head-wave amplitude (AD value) is 31,753.The results of the arrival time and amplitude detection are consistent with the waveform of the acquired data, which is shown in Figure 9c, and the expected processing results, thereby indicating that the head-wave extraction algorithm based on FPGA is correct and can meet the downhole requirement.

Laboratory Tests
We then performed various tests on the function correctness, high temperature resistance, and system performance of the echo reception pre-processing module in our laboratory.Figure 10 shows the actual image and test results of the reception pre-processing module during the temperature resistance test.Figure 10b reveals that our module exhibited good temperature resistance; it could work stably for a long time in a downhole environment of 150 • C. In the test, the gain control program of CPLD is set to a constant gain output mode, and the gain is fixed to 36 dB.According to the test results of Figure 10b, the error between the measured gain and the theoretical value is small, indicating that the circuit performance is basically stable at different temperatures.
R PEER REVIEW 10 of 15

Laboratory Tests
We then performed various tests on the function correctness, high temperature resistance, and system performance of the echo reception pre-processing module in our laboratory.Figure 10 shows the actual image and test results of the reception pre-processing module during the temperature resistance test.Figure 10b reveals that our module exhibited good temperature resistance; it could work stably for a long time in a downhole environment of 150 °C.In the test, the gain control program of CPLD is set to a constant gain output mode, and the gain is fixed to 36 dB.According to the test results of Figure 10b, the error between the measured gain and the theoretical value is small, indicating that the circuit performance is basically stable at different temperatures.In the quantitative response test, the gain control program of FPGA is set to the constant gain output mode, and the gain size is set by the program, which is manually adjusted during the test.The frequency of the fixed sinusoidal input signal is 250 kHz.
Table 1 is the data record and calculation results of the quantitative response test.It can be seen from the table that the measured gain of the circuit is basically consistent with the theoretical gain under different gain conditions, and the maximum relative error is −2.75%.It can be shown that the pre-processing module has a stable programmable dynamic amplification function.Under different gain modes, the amplification accuracy meets the design requirements of downhole applications.In the quantitative response test, the gain control program of FPGA is set to the constant gain output mode, and the gain size is set by the program, which is manually adjusted during the test.The frequency of the fixed sinusoidal input signal is 250 kHz.
Table 1 is the data record and calculation results of the quantitative response test.It can be seen from the table that the measured gain of the circuit is basically consistent with the theoretical gain under different gain conditions, and the maximum relative error is −2.75%.It can be shown that the pre-processing module has a stable programmable dynamic amplification function.Under different gain modes, the amplification accuracy meets the design requirements of downhole applications.11.The first wave and arrival time extraction algorithms are run using FPGA (instrument used) and DSP (28377D) circuits, respectively, and the results are compared.The Table 2 data show that the results calculated by the two platforms are relatively close, indicating the reliability of the algorithm.The FPGA runs the algorithm for 14 ms per waveform, the DSP is 18 ms per waveform, and the efficiency of the FPGA is higher.So, the FPGA is used as the controller to process the collected data in the actual instrument, which improves the efficiency of real-time data processing.and the results are compared.The Table 2 data show that the results calculated by the two platforms are relatively close, indicating the reliability of the algorithm.The FPGA runs the algorithm for 14 ms per waveform, the DSP is 18 ms per waveform, and the efficiency of the FPGA is higher.So, the FPGA is used as the controller to process the collected data in the actual instrument, which improves the efficiency of real-time data processing.

Field Experiment
To further verify the head-wave extraction method, we used an assembled UILWD tool to conduct field tests in an experimental drilling well.The result of the downhole realtime processing was compared with that of surface processing to verify the reliability of the proposed downhole method.
Figure 12 demonstrates the head-wave arrival time extraction from the waveforms of the three channels.Among them, the black curves represent the original data of ultrasonic logging, while the red curve reflects the arrival time of the head wave extracted in a realtime downhole.It can be seen that the extracted arrival time of the head wave is consistent with the actual situation.

Field Experiment
To further verify the head-wave extraction method, we used an assembled UILWD tool to conduct field tests in an experimental drilling well.The result of the downhole real-time processing was compared with that of surface processing to verify the reliability of the proposed downhole method.
Figure 12 demonstrates the head-wave arrival time extraction from the waveforms of the three channels.Among them, the black curves represent the original data of ultrasonic logging, while the red curve reflects the arrival time of the head wave extracted in a realtime downhole.It can be seen that the extracted arrival time of the head wave is consistent with the actual situation.Furthermore, Figure 13 shows the extraction of the head-wave amplitude.The blue dotted curve represents the actual head-wave amplitude obtained by surface data processing, while the red solid curve reflects the head-wave amplitude extracted by downhole hardware.It can be seen that both results basically coincide.Furthermore, Figure 13 shows the extraction of the head-wave amplitude.The blue dotted curve represents the actual head-wave amplitude obtained by surface data processing, while the red solid curve reflects the head-wave amplitude extracted by downhole hardware.It can be seen that both results basically coincide.To quantitatively verify the accuracy of downhole head-wave extraction, a comparative statistical analysis of the downhole extraction result and the surface processing result was performed.Table 3 presents the error analysis of the downhole real-time processing result.Notably, the maximum relative error of the head-wave arrival is <5%, and the proportion of the error that is <3% is 95.55%.This means that the maximum true error of the arrival time of the head wave does not exceed 2 µs (five sampling points) in the actual acquired data.The maximum relative error of the head-wave amplitude is <15%, and the proportion of errors less than 5% is 92.23%.To quantitatively verify the accuracy of downhole head-wave extraction, a comparative statistical analysis of the downhole extraction result and the surface processing result was performed.Table 3 presents the error analysis of the downhole real-time processing result.Notably, the maximum relative error of the head-wave arrival is <5%, and the proportion of the error that is <3% is 95.55%.This means that the maximum true error of the arrival time of the head wave does not exceed 2 µs (five sampling points) in the actual acquired data.The maximum relative error of the head-wave amplitude is <15%, and the proportion of errors less than 5% is 92.23%.

Conclusions
To realize the downhole real-time extraction of head waves in UILWD, an improved algorithm for extracting the head-wave arrival time based on the energy ratio and a method for detecting the peak-to-peak amplitude were proposed in the present paper.An echo reception pre-processing analog circuit was designed to improve the SNR of the echo signal.Additionally, a pipelined real-time extraction algorithm of the head-wave arrival time and amplitude was developed in FPGA.
Our test results showed that the downhole real-time head-wave extraction method has strong anti-noise ability.It can extract the head wave in real time, and relative errors pertaining to the arrival time and amplitude are within the acceptable range.
This method meets the requirement of the downhole real-time processing of echo signals and was applied in the UILWD tool.Compared with the conventional analog circuit detection method, head-wave extraction based on a digital circuit could significantly enhance both the accuracy and stability of head-wave extraction.In addition, the highresolution borehole image generated by the tool can accurately reflect the shape of the borehole, identify the characteristics of cracks, pores, bedding, etc., and play an important role in monitoring the status and quality of borehole engineering.

Figure 1 .
Figure 1.Effect comparison between the STA/LTA and improved STA/LTA methods.

Figure 2 .
Figure 2. Diagram of the principal hardware used for head-wave real-time extraction.

Figure 1 .
Figure 1.Effect comparison between the STA/LTA and improved STA/LTA methods.

Figure 1 .
Figure 1.Effect comparison between the STA/LTA and improved STA/LTA methods.

Figure 2 .
Figure 2. Diagram of the principal hardware used for head-wave real-time extraction.

Figure 2 .
Figure 2. Diagram of the principal hardware used for head-wave real-time extraction.

Figure 3 .
Figure 3. Structure diagram of the analog band-pass filter circuit.

Figure 4 .
Figure 4.The calculated parameters of the band-pass filter circuit.

Figure 3 .
Figure 3. Structure diagram of the analog band-pass filter circuit.

Figure 3 .
Figure 3. Structure diagram of the analog band-pass filter circuit.

Figure 4 .
Figure 4.The calculated parameters of the band-pass filter circuit.Figure 4. The calculated parameters of the band-pass filter circuit.

Figure 4 .
Figure 4.The calculated parameters of the band-pass filter circuit.Figure 4. The calculated parameters of the band-pass filter circuit.

Figure 5 .
Figure 5. Composition of the programmable gain amplification module.

Figure 5 .
Figure 5. Composition of the programmable gain amplification module.

Figure 6 .
Figure 6.Structure of the front-end control program.

Figure 6 .
Figure 6.Structure of the front-end control program.

Figure 7 .
Figure 7. Calculation flow of digital filtering.

Figure 8 .
Figure 8. Program structure of head-wave extraction.

Figure 7 .
Figure 7. Calculation flow of digital filtering.

Figure 8 .
Figure 8. Program structure of head-wave extraction.

Figure 9 .
Figure 9. Simulation results of head-wave extraction: (a) Head wave arrival detection; (b) Head wave amplitude detection; (c) Verification of simulation.

Figure 9 .
Figure 9. Simulation results of head-wave extraction: (a) Head wave arrival detection; (b) Head wave amplitude detection; (c) Verification of simulation.

Figure 10 .
Figure 10.Actual image and test result of the echo reception pre-processing module.(a) Actual image; (b) Gain at different temperatures.

Figure 10 .
Figure 10.Actual image and test result of the echo reception pre-processing module.(a) Actual image; (b) Gain at different temperatures.

Table 1 .
The performance test results of the pre-processing module.

Table 1 .
The performance test results of the pre-processing module.In another test, 10 different depths of waveform data are used to test the circuit and program performance, as shown in Figure

Table 2 .
Comparison of extracted data between DSP and FPGA chips.

Table 2 .
Comparison of extracted data between DSP and FPGA chips.

Table 3 .
Error analysis of downhole processing.