Enhanced Quasi Type-1 PLL-Based Multi-Functional Control of Single-Phase Dynamic Voltage Restorer

: This paper considers the reference signal generation problem for the multi-functional operation of single-phase dynamic voltage restorers. For this purpose, a single-phase quasi type-1 phase-locked loop (QT1-PLL) is proposed. The pre-loop ﬁlter part of this PLL is composed of a frequency-ﬁxed delayed signal cancellation method and a two-stage all-pass ﬁlter. Thanks to the frequency-ﬁxed nature, the pre-loop ﬁlter is easy to implement and can provide rejection of any measurement offset. Moreover, this PLL beneﬁts from the excellent harmonic robustness property of the conventional QT1-PLL. Small-signal modeling and gain tuning procedures are detailed in this paper. In order to track the reference voltage signals generated by the proposed PLL, a super-twisting sliding mode controller is also presented, which helps to achieve fast dynamic responses. Laboratory-scale prototype-based experimental studies were conducted to validate the developed reference generator and the controller. Experimental results show that the proposed method is fast in detecting and compensating any grid voltage anomalies to maintain constant load voltage despite voltage sag, swell, and harmonic distortions.


Introduction
Power quality problems such as voltage sag, swell, and harmonics can significantly affect the performance of critical loads that are used in hospital, water treatment plant, data center, etc. In addition to harmonics, voltage sag and swells are quite common in power grid and can be caused by many reasons such as lightning strike, accident, short circuit, over loading, switching on or off large electrical loads, etc. In the case of water treatment plant, voltage sag/swell can interrupt the treatment process including dissolved air flotation, filtration, and disinfection. Any interruption in the process can take up to 8 h to resolve, causing one-third production loss for the day. This highlights the importance of mitigating voltage-related power quality problems.
In order to address power quality issues such as voltage sag, swell, and harmonics, the dynamic voltage restorer (DVR) became very popular in recent times [1][2][3][4]. DVR can compensate voltage sag, swell, and harmonics to maintain desired constant voltage at the critical load side. In the literature, various topologies of DVR are proposed. However, the most basic DVR topology is made of any dc voltage source such as battery, photovoltaic panel, etc., together with a voltage source inverter with LC filter and a transformer. The transformer provides galvanic isolation between the inverter and its secondary is connected between the grid voltage and the load in series. The control system of DVR constantly monitors grid voltage and injects compensation voltage when it detects any deviation from the desired voltage. This results in maintaining desired load voltage despite various power quality disturbances at the grid.
The detection of voltage sag, swell, and harmonics plays a vital role in ensuring the effective operation of DVR. Voltage sag and swells are typically short-lived incidents with a time range of few milliseconds to a minute [5]. As such, fast and accurate detection of sag and swell is essential for fast responsive DVR operation. In the ideal case, voltage sag/swell can be detected very quickly by comparing the voltage magnitude with respect to the ideal magnitude. However, calculating the magnitude can be tricky in the presence of nonlinearities such as harmonics.
The first step in compensation voltage calculation is to generate the reference voltage, which should be in-phase with the measured grid voltage. If the grid voltage is ideal, i.e., has a frequency of 50 Hz (or 60 Hz) and contains no harmonics, then generating the reference voltage is straightforward. However, this is not the case in practice. According to the European standard EN 50160 [6], grid voltage can vary between −3 Hz and +2 Hz of the nominal frequency. However, the grid frequency has to be within 1% of the nominal value, i.e., ±0.5 Hz for 99.5% of the time. Moreover, harmonics are almost always present in the grid due to the ever increasing penetration of nonlinear loads and converter-interfaced distributed energy sources. All these factors complicate the reference voltage calculation.
In order to address the non-ideal characteristics of the measured grid voltage, researchers often rely on phase-locked loop (PLL) [7][8][9][10][11][12][13][14][15] or similar techniques to generate the reference voltage for DVR. Using PLL, first, the instantaneous phase of the grid voltage fundamental component is estimated. This can then be used as the unit template for the reference voltage. By multiplying the unit template with the desired amplitude, the actual reference grid voltage can be calculated. In this study, we are considering a single-phase DVR. However, traditional PLLs in the form of synchronous reference frame (SRF) PLLs work only for three-phase systems. For single-phase systems, an additional orthogonal signal generator (OSG) is required to implement SRF-PLL. In the single-phase DVR literature, various OSGs have already been used. In [16], a second-order generalized integrator (SOGI) is used as the OSG. The effect of DC offset is not considered in [16]. Moreover, despite having band-pass filtering property, traditional SOGI-PLL cannot completely reject the dominant harmonics. Thus, multiple SOGIs need to be placed in parallel in order to reduce the effect of dominant harmonic components. This can make the overall system computationally complex. It is to be noted here that the conventional SRF-PLL can be made robust to harmonics and DC offset by considering a slow loop-filter, i.e., by reducing the bandwidth. This has been considered in [17]. Although this is an interesting practical solution, this strategy is suitable for voltage compensation but not harmonics.
Self-tuning filter (STF) is similar to SOGI; however, in the case of STF, the error feedback is independent of the grid frequency. In [18,19], the authors have applied STF as the reference generator without considering frequency adaptation. As such, the reference generator in [18,19] can be limiting when the grid frequency varies significantly. Quarterdelay is another popular method for generating orthogonal signal. This approach is considered in [20]. However, in off-nominal frequency condition, the required delay would be fractional which increases computational complexity. In [21], an adaptive notch filter (ANF) is used as the reference generator. However, the considered ANF did not use gain normalization. This can make the convergence time slow in the presence of voltage sag.
Based on the literature review, it is clear that there is demand for a reference generator that is robust to harmonics and DC offset while at the same time is computationally simple to implement. For this purpose, in this study, a quasi type-1 PLL [22][23][24] is considered. This PLL has been selected for several reasons. Firstly, it can provide amplitude normalization without using any low-pass filter unlike conventional SRF-PLL, cf. [25]. Use of additional low-pass filter in the amplitude normalization block will introduce tuning complexity as there is one more gain to tune. Secondly, this PLL provides good harmonic robustness thanks to the use of a moving-average filter. Finally, it has only one gain to tune unlike SRF-PLL where the loop-filter has two tuning parameters. However, this PLL can work only for three-phase system. Thus, a single-phase version of this PLL is proposed in this study.
For this purpose, first, a half-cycle delayed signal cancellation method is applied to reject the DC offset. Then, a frequency-fixed all-pass filter (APF) [26] is applied to generate the orthogonal signal. However, single-stage APFs will generate double frequency oscillations in off-nominal frequency conditions. As such, a two-stage APF is considered that can eliminate the double frequency error. The APF is selected in this study as it can generate orthogonal signals without using any tuning gain unlike other choices available in the literature such as SOGI [16,27], ANF [21], etc. This is beneficial from the tuning simplicity point of view. Finally, the filtered grid voltage signal and its orthogonal component are used as the inputs to the quasi type-1 PLL. A small-signal model of the proposed PLL is developed and validated. Finally, tuning of the PLL gain is also presented. Compared to conventional PLL techniques summarized in [28], our approach is very simple to tune as it has only one tuning gain. All the techniques summarized in [28] have at least three parameters to tune if amplitude normalization is considered. Unlike most of the techniques in [28], our quadrature signal generator is frequency non-adaptive. As such, there is no frequency feedback which may be beneficial from the stability point of view.
Once the reference signal is generated, the role of control system is to follow/track the reference. In the literature, synchronous frame approach in the form of proportional-integral (PI) controllers [29] are widely used. Although this controller can be easily designed and implemented, the dynamic response can be slow. In order to enhance dynamic performance, advanced controllers such as model predictive control (MPC) [7,8], H ∞ [30], and sliding mode control (SMC) [31][32][33] are proposed in the literature. MPC can be sensitive to model parameters mismatch. Computational complexity can be an issue for H ∞ controllers. SMC is often a suitable choice for controlling nonlinear systems in the presence of parameter mismatch and/or external perturbations. As such, this technique has been selected in this study.
The rest of this article is organized as follows: Section 2 explains the operation of the proposed DVR together with the error model for controller development. Development of the proposed reference signal generator is provided in detail in Section 3. Development of the sliding-mode controller is provided in Section 4. Experimental results on a laboratoryscale prototype together with simulation results are provided in Section 5. Finally, Section 6 concludes this paper.

DVR Modeling and Problem Formulation
In this study, we consider a single-phase DVR. A connection diagram of the DVR is given in Figure 1. In this configuration, the DVR, which is a full-bridge voltage source inverter, is connected in series through a transformer to the protected load. Isolation between the load the DVR is provided by the transformer. Grid voltage sensor is used to continuously monitor the deviation from the reference voltage, and the appropriate compensation voltage is injected by the DVR to maintain the ideal voltage at the protected load terminal. Filter current and compensation voltage dynamics of the DVR are given by the following: where , and C f denote the input voltage by the DVR, grid voltage, compensation voltage, filter current, filter inductance, and filter capacitance, respectively. The DVR voltage can be expressed as v i = uV dc where the DC-link voltage is denoted by V dc , and the control signal is given by u. Moreover, in the ideal case, one can also write the following. In normal operating condition, the compensation voltage given by (3) will be zero. However, in practice, the grid voltage is never ideal. Various grid anomalies such as voltage sag/swell, harmonics, noise, etc., are present. In this case, (3) can no longer be used for the compensation voltage calculation. In order to ensure that the sensitive load voltage remains as close as possible to the desired voltage, reference voltage needs to be calculated and this voltage should be in-phase with the grid voltage fundamental for the efficient operation by the DVR. Let us consider that the reference voltage is denoted by v ref c . Then, the tracking error and its derivative are given by the following.
Then, by substituting the DVR dynamical Equations (1) and (2) into (4) and (5), the DVR tracking error dynamics can be obtained as follows: where the coefficient δ = 1/ L f C f and the perturbation term w(t) is given by the following.
It is assumed that the perturbation term w(t) has a bounded derivative and is upper bounded by | dw dt |≤ W,W > 0. Thus, the control of DVR is essentially divided into two parts. In part 1, the problem is to generate the reference voltage v ref c from the measured grid voltage v g . In part 2, the problem is to find the control signal u that will ensure that the tracking errors converge asymptotically to zero. These two issues are addressed in the following two sections.

Reference Signal Generator
In this Section, reference voltage v ref c will be generated from the measured grid voltage v g . For this purpose, let us consider the singe-phase grid voltage signal model in timedomain as provided below: where |v 0 | ≥ 0, V p , and θ g = ω g dt, θ g (0) = φ are the DC offset, amplitude, and instantaneous phase with ω g being the grid frequency, and φ is the initial phase angle. The frequency is ω g = ω n + δ ω , where ω n = 100π is the nominal frequency and δ ω is the deviation from the nominal frequency. For efficient operation of the DVR, the reference voltage should be in phase with the instantaneous phase of the grid voltage θ g . Thus, the process of extracting θ g from the measured voltage v g is considered in this section. For this purpose, a PLL-based approach has been considered in this study. Details are provided below.

DC Offset Rejection
Measurement offset v 0 causes estimation error in the estimated phase. Thus, rejection of this offset is essential in order to eliminate the steady-state error. For this purpose, the halfcycle delayed signal cancellation (DSC) method is a popular choice in the literature [34,35]. The same approach is considered here. For this purpose, let us consider half-cycle delayed version of the signal v g as follows: where t d = T 2 with T = 2π ω g being the period of the grid voltage signal. Then, the DC offset can be eliminated by the following operation.
In implementing Equation (10), the actual period of the grid voltage is required. In the off-nominal frequency condition, the amount of required dely could be a fraction, thereby increasing computational complexity. A potential solution is to use the nominal period; however, this will introduce amplitude and phase attenuation in the off-nominal condition. In this study, only extracting the phase is required. thus, appropriate compensation of the phase delay is necessary to eliminate the error. For this purpose, let us consider the transfer function of the DSC operation (10) as provided by the following: where the estimated value is indicated byˆ. The discrete-time version of the transfer function (11) is given by the following: where the required delay is given by as N d = t d f s with f s being the sampling frequency. By substituting s = jω g , the phase angle of the transfer function (11) is given by the following.
In calculating (13), it is assumed that ω n = 2π/T. Equation (13) shows that the use of nominal period in (10) causes a phase delay of −k dc δ ω in the off-nominal frequency case. This phase needs to be compensated in the loop-filter to eliminate the phase error in the off-nominal frequency condition.

Tuning-Free Fixed-Frequency Orthogonal Signal Generator
Once the DC offset is eliminated, the signal v ∅ g can be used to generate an orthogonal signal component. In this study, we are considering an all-pass filter (APF) [26,36]. APF is a first-order filter, and it can be used to generate orthogonal signals without any tuning gain. This filter can be used either as frequency-adaptive or non-adaptive configurations. In this study, a frequency-fixed operation is considered same as the DC offset rejection method, as highlighted in Section 3.1. The frequency-fixed APF transfer function is given by the following: v ∅⊥ where superscript ⊥ indicates orthogonal signals. A time-domain block diagram of APF is provided in Figure 2. Similarly to Section 3.1, the frequency-fixed operation of the APF will introduce amplitude and phase attenuation in the estimated orthogonal signal. As such, characterization of the APF is needed to determine the necessary compensation mechanism. Phase-angle of the transfer function (14) is given by the following.
For small frequency drift, i.e., δ ω ≈ 0, it can be assumed that ω g + ω n ≈ 2ω g . Then, the phase angle (15) can be approximated as follows. By ignoring the high-order (2nd and above) terms from the Taylor series expansion in (16), this equation can be simplified as follows.

∠APF(s)
As shown in (17), the first two terms are frequency independent while the third term depends on frequency variation. This term, i.e., k φ = 1/2ω n , needs to compensated.
It is well known that single-phase grid voltage can be represented by an unbalanced two phase-system. It was shown in [36] that single-stage frequency-fixed APF cannot effectively remove the unbalanced component as the bandwidth of the unbalanced component rejection part is very narrow. As such, the unbalanced component will appear as double the fundamental frequency component after Park transformation. Thus, in order to eliminate this error, the double frequency component needs to be rejected. This issue can be solved by increasing the bandwidth of the notch component. In the literature, a two-stage APF has been suggested for this purpose. The two-stage APF effectively increases notch bandwidth and enables frequency-fixed APFs to reject off-nominal frequency unbalanced components. However, the two-stage APF will double the phase delay in the off-nominal frequency condition. As such, the required phase compensation value is computed by k φ = 2k φ = 1/ω n .

Implementation in PLL
The previous two subsections detailed the procedure for obtaining DC offset eliminated signal v ∅ g and its orthogonal component v ∅⊥ g . These signals can be used as the input to PLL. The overall block diagram of the proposed PLL is provided in Figure 3. This section details the operating principle of this PLL. Before describing the phase detector operation of this PLL in our case, let us consider APF-filtered signals in the steady-state: where δ φ is the off-nominal frequency phase attenuation by each stage of the APF. As per Figure 3, using the signal v ∅ The phase detector of the considered PLL is provided by the following.
Then, direct-axis and quadrature-axis voltages can be obtained directly from (21). By applying a quasi-locked condition, i.e., ω −ω ≈ 0, the direct-axis and quadrature-axis voltages can be rewritten as follows.
Double frequency components in (22) and (23) can easily be filtered by applying moving average filter (MAF) with half-cycle window length. The transfer functions of MAF in continuous and discrete domain are provided by the following.
By applying MAF to (22) and (23) and also assuming negligible off-nominal frequency phase shift, filtered v d and v q can be approximated as follows.
Filtered voltages are then fed to the loop-filter of QT1-PLL, as shown in Figure 3.

Small-Signal Modeling and Tuning
A small-signal model of the proposed PLL can be obtained by considering the signal flow in Figure 3. For this purpose, first, the small-signal model of the pre-loop filters needs to be developed. The first pre-loop filter is the delayed signal cancellation block, which is given by transfer function (11). This transfer function can be converted into synchronous reference frame by substituting s = s + jω n .
The transfer function of the APF in synchronous reference frame can be obtained by applying the Park transformation to single-stage APF and is given by the following Gautam et al. [26].
In our study, a two-stage APF is considered. As such, the effective transfer function is given by the following.
Considering the pre-loop filters, the small-signal model is shown in Figure 4, where γ = k dc + k φ is the overall phase compensation gain. The proposed PLL has only one parameter to tune, which is the frequency estimation gain k f . This gain can be tuned in several ways. Two of the popular approaches are based on open-loop phase margin and settling time. The later is considered in this study. In order to tune gain k f using this method, a +2 Hz frequency step is considered. Considering a 2% settling time, settling time versus the gain k f is given in Figure 5. From this figure, k f = 89 has been found to provide the fastest settling time. This value has been considered as the optimal gain for k f . Considering this value of k f ,validation of the small-signal model is provided in Figure 6.  Once the phase of the grid voltage fundamental component is estimated, the reference compensation voltage can be calculated as follows: where reference magnitude is provided by V ref p . The design of the control signal u based on the reference grid voltage (31) is detailed in the next section.

Super Twisting Sliding Mode Controller Design
In this Section, tracking error dynamics (6) and (7) will be used for the control design. For this purpose, let us consider that the control signal is composed of u = u 0 + u n , where u 0 is the nominal control signal and u n is the nonlinear part of the control signal. If we consider u 0 = (1/V dc )ξ 1 and u n = u ST /(δV dc ), then the total control signal can be written as follows.
Then, the tracking error dynamics (6) and (7) can be rewritten as follows.
Tracking error dynamics (33) and (34) can be viewed as a perturbed second-order integrator. Numerous control techniques can be employed to stabilize the error under the presence of perturbation w(t). In this study, we consider a second-order SMC [31,37] in the form of super-twisting SMC [38]. In order to design the super-twisting SMC, let us consider the following sliding surface.
Then, the controller u ST in (34) can be designed as follows: where sgn(.) is the conventional signum function and the gains λ 2 and λ 3 are selected as follows.
Let us consider the following variables.
Then, the dynamics of the sliding surface (38) can be rewritten as follows.
Then, for the selected control gain (37), finite-time convergence of the variables ζ 1 and ζ 2 can easily be established by using the results presented in Levant [37]. In order to implement the super-twisting controller, (32), (35), and (36) are required. An implementation block diagram of the super-twisting sliding-mode controller is provided in Figure 7.

Simulation and Experimental Results
In this Section, simulation and experimental results are reported. The experimental setup used in this study is demonstrated in Figure 8. Here, a Texas Instrument C2000 series micro-controller is used to implement the proposed control and estimation algorithm. Parameters of the setup and control gains are provided in Table 1.

System and Control Parameters Values
Controller gains PLL gain k f = 89 Grid: voltage and frequency 120 V (rms) 50 Hz Grid: impedance R g = 1 mΩ, L g = 0.1 µH Transformer turns ratio 1:1 DC link voltage, V dc 120 V LC filter L f = 0.8 mH, C f = 50 µF Sensitive series load R = 100 Ω Numerical simulation using Matlab/Simulink is conducted by considering the same values.
In the first test, the grid voltage suddenly experiences a ≈30% sag. From approximately 170 V (peak), the grid voltage dropped to roughly 120 V (peak). Experimental results are provided in Figure 9. The results show that in order to mitigate the effect of grid voltage sag at the sensitive load side, the DVR was very quick to react and supplied the necessary 50 V in-phase compensation voltage. As a result, constant voltage was maintained at the load side. In the second test, voltage swell was considered, and the results are provided in Figure 10. Here, grid voltage increased to 210 V, which is roughly a 25% change from the nominal value. Unlike the first test, here, out-of-phase compensation voltage needs to be generated in order to reduce the voltage at the sensitive load end. As shown in Figure 10, the proposed enhanced QT1-PLL was very successful in generating the required roughly 40 V out-of-phase compensation voltage, and the sliding mode controller ensured the tracking of the reference compensation voltage by the DVR. These results show that the proposed approach can handle both sag and swell conditions. In the real grid, in addition to voltage sag/swell, harmonics are also a problem. The presence of harmonics will render the sensitive load voltage distorted. As a result, power quality degrades. In order to mitigate this issue, harmonic compensation is also required. In the final test, the grid voltage suddenly became distorted, and the results are provided in Figure 11. The proposed PLL can extract the fundamental component with high harmonic robustness. As a result, quick estimation of the grid harmonics was performed by PLL, and DVR injected the necessary harmonic compensation voltage to ensure very low distortion at the load side. The results in Figure 11 validate the suitability of the proposed PLL in a distorted grid condition.   In order to check the robustness of the used controller, we have used numerical simulations. In the simulation test, voltage sag and harmonics are considered. The nominal value of the filter inductor is 0.8 mH. This value is used to synthesize the control law. Simulation results with ±25% variation in the filter inductor are provided in Figure 12. The results in Figure 12 show that the response of DVR is very similar when the system parameter experienced a ±25% change from the nominal value. This shows that the sliding mode controller is robust to parameter variations.
Experimental results as shown in Figures 9-11 independently considered voltage sag, swell, and harmonics. In practice, in addition to these characteristics, phase and/or frequency of the grid voltage may also change simultaneously in the worst case scenario. In order to asses the performance of the proposed method, two additional simulation studies were considered. In the first test, grid voltage experienced −0.5 p.u. sag and −25 • phase change simultaneously. In the second test, in addition to the sag, the grid voltage also experienced +25 • phase change and +1 Hz frequency change. In both cases, the fault cleared after 100 ms and the grid became distorted after fault clearance. Numerical simulation results for the first and second test are provided in Figures 13 and 14. Results show that the proposed control method is very fast (roughly 1 cycle convergence time) despite very abrupt changes in grid voltage parameters. However, it is to be noted here that the load voltage transients are not that smooth compared to the case when only one parameter changed, such as in Figure 12. Smooth transient load voltage scan be obtained by either freezing the PLL or by using a very slow one [17]. However, this type of solution will not be able to provide efficient harmonic compensation. As such, a trade-off between the dynamic response and smooth transient behavior has to be made in PLL parameter selection.  (c) (c)

Conclusions
In this paper, an enhanced single-phase quasi type-1 PLL was proposed to generate the reference compensation voltage for the multi-functional operation of a single-phase dynamic voltage restorer. A super-twisting sliding-mode controller was also proposed to track the reference voltage. The developed PLL is highly robust to grid voltage harmonics, which resulted in very low total harmonic distortion at the sensitive load-side. Moreover, thanks to a super-twisting controller, fast tracking of the compensation voltage was also achieved. Stability analysis and tuning of the PLL are presented by using small-signal modeling. The developed control method has been validated in a laboratory-scale prototype. The experimental results show that the proposed controller is very effective in compensating any grid voltage abnormalities, which in turn contributes to keeping the voltage at the sensitive load-side to remain very close to the ideal reference voltage.