Energy-Efﬁcient Ampliﬁers Based on Quasi-Floating Gate Techniques

: Energy efﬁciency is a key requirement in the design of ampliﬁers for modern wireless applications. The use of quasi-ﬂoating gate (QFG) transistors is a very convenient approach to achieve such energy efﬁciency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efﬁcient class AB ampliﬁers. A new super class AB QFG ampliﬁer is presented as a design example, including some of the techniques described. The ampliﬁer has been fabricated in a 130 nm CMOS test chip prototype. Measurement results conﬁrm that low-voltage, ultra-low-power ampliﬁers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.


Introduction
Today, we are facing significant challenges in the design of electronic circuits. Many emerging wireless connectivity and Internet of Things edge computing applications require ultra-low-power wireless devices providing high performance in both indoor and outdoor environments. Energy efficiency is mandatory in such applications in order to increase battery lifetime. In fact, due to maintenance costs, battery replacement or manual recharge becomes impractical or even unfeasible in several scenarios with hard-to-reach wireless nodes (e.g., large civil infrastructures, vast natural ecosystems or implantable medical devices), requiring energy-autonomous wireless devices with batteries lasting several years. In some cases, the limited and often intermittent residual energy harvested from the environment (light, thermal gradients, vibrations, etc.) must be enough to operate the wireless device [1].
Aside from this, modern nanometer integrated circuit (IC) processes pose further challenges since device scaling directly impacts electronic design. Intrinsic gain reduction degrades DC gain. Supply voltage lower than 1 V becomes commonplace to reduce power consumption and to avoid gate oxide breakdown of nanometer devices. To complicate things, transistor threshold voltage cannot scale at the same rate as the supply voltage to keep subthreshold leakage currents low, so the available voltage swing reduces [2].
Preserving circuit performance in these demanding scenarios of energy scarcity and very low-voltage operation is a real challenge, and conventional circuit design techniques are often no longer valid in this framework. Innovative design techniques are required to meet these new demands. A critical block in modern mixed-signal ICs is the amplifier,

Quasi-Floating Gate Transistors
In this section, the fundamentals of QFG transistors are briefly presented, and their application to the design of low-voltage class AB amplifiers is discussed.

Wideband Capacitive Coupling Using Quasi-Floating Gate Transistors
Capacitive (or AC) coupling is widely used to isolate the DC bias setting circuit of active devices from the driving signal source. A typical example is shown in Figure 1a, where a resistive divider sets the quiescent gate voltage of the transistor. Coupling capacitor C blocks the input DC voltage and allows the input signal to pass through to the gate. A more general biasing scheme is shown in Figure 1b, where DC bias voltage V B is set using resistor R B . Note that the circuit of Figure 1a can be regarded as a particular case of Figure 1b, using the Thévenin's theorem, where V B = (V DD − V SS )·R 2 /(R 1 + R 2 ) and R B = R 1 ||R 2 . The circuit of Figure 1b provides a first-order, low-pass filtering from input VB to the gate and a first-order, high-pass filtering from input Vsig to the gate, both with time constant RB·C. Due to the limited practical values of on-chip passive resistors and capacitors, this time constant cannot be too large. Hence, despite the name "AC coupling," this technique is rather employed in ICs for RF narrowband signals with frequencies above the relatively large cutoff frequency of the high-pass input filter. However, several relevant applications require processing of very low frequency signals (such as biomedical systems, structural health monitoring, geoenvironmental monitoring, etc.) or wideband signals with significant content at low frequencies (for instance, baseband processing circuits in a direct conversion receiver). In these cases, DC-blocking circuits able to allow near-DC frequency components pass through are required. An efficient approach to achieve the large time constant required is replacing resistor RB in Figure  1b by a pseudo-resistor (also known as quasi-infinite resistor, QIR) [6,7]. The resulting circuit is shown in Figure 1c, which is known as a QFG transistor [5]. Pseudo-resistors are small-area integrated devices that can provide extremely large incremental resistances (in the order of GΩ-TΩ) when they are properly biased. Therefore, very large RC time constants can be obtained using small capacitors that can be implemented on-chip.
From Figure 1c, the transfer functions from inputs VB and Vsig to Vg are: with τ = RB·(C + Cg) as the time constant, Cg the parasitic capacitance at the gate terminal and α = C/(C + Cg). Note that input VB is low pass filtered with an extremely large time constant τ, so that the DC bias voltage VBIAS is set to the gate, and any AC noise or interference coming from this input is rejected. The signal at input Vsig is high pass filtered with the same time constant, so, in practice, only the DC level at this input is blocked. This input signal is also attenuated by a factor α, due to the nonzero parasitic gate capacitance Cg. The value of Cg sets the minimum required value for C to avoid excessive attenuation. The circuit of Figure 1b provides a first-order, low-pass filtering from input V B to the gate and a first-order, high-pass filtering from input V sig to the gate, both with time constant R B ·C. Due to the limited practical values of on-chip passive resistors and capacitors, this time constant cannot be too large. Hence, despite the name "AC coupling," this technique is rather employed in ICs for RF narrowband signals with frequencies above the relatively large cutoff frequency of the high-pass input filter.
However, several relevant applications require processing of very low frequency signals (such as biomedical systems, structural health monitoring, geoenvironmental monitoring, etc.) or wideband signals with significant content at low frequencies (for instance, baseband processing circuits in a direct conversion receiver). In these cases, DCblocking circuits able to allow near-DC frequency components pass through are required. An efficient approach to achieve the large time constant required is replacing resistor R B in Figure 1b by a pseudo-resistor (also known as quasi-infinite resistor, QIR) [6,7]. The resulting circuit is shown in Figure 1c, which is known as a QFG transistor [5]. Pseudoresistors are small-area integrated devices that can provide extremely large incremental resistances (in the order of GΩ-TΩ) when they are properly biased. Therefore, very large RC time constants can be obtained using small capacitors that can be implemented on-chip.
From Figure 1c, the transfer functions from inputs V B and V sig to V g are: with τ = R B ·(C + C g ) as the time constant, C g the parasitic capacitance at the gate terminal and α = C/(C + C g ). Note that input V B is low pass filtered with an extremely large time constant τ, so that the DC bias voltage V BIAS is set to the gate, and any AC noise or interference coming from this input is rejected. The signal at input V sig is high pass filtered with the same time constant, so, in practice, only the DC level at this input is blocked. This input signal is also attenuated by a factor α, due to the nonzero parasitic gate capacitance C g . The value of C g sets the minimum required value for C to avoid excessive attenuation. Multiple-input QFG transistors can also be used [5], allowing weighted averaging of signals in a simple and compact way.
Note the different behavior of the circuit of Figure 1c for DC and AC small-signal and large-signal dynamic (or transient) operation. Capacitor C is an open circuit in DC, so the quiescent gate voltage is V g Q = V BIAS , since there is not current flowing through the pseudo-resistor. Hence, the bias point can be accurately set. For AC small-signal operation, the capacitor acts as a short circuit (more precisely, as an attenuator, due to the input capacitive divider), so that the AC gate voltage is v g = αv ac , with v ac the AC voltage at input V sig . For transient operation with input frequencies larger than 1/τ (in practice from near DC), C acts as a floating battery with voltage V BIAS -V DC , with V DC the DC voltage at input V sig . This is because C cannot be discharged rapidly through the pseudo-resistor. The signal is thus level-shifted by V BIAS -V DC and attenuated by factor α when it reaches the gate. In practice, nonlinearity of the pseudo-resistor may lead to nonlinear distortion and offset in the gate voltage. These issues are more relevant for large voltage swings at the pseudo-resistor terminals and depend on the implementation of the pseudo-resistors. Some of the most common fixed and tunable pseudo-resistors are shown in Figures 2 and 3, respectively. Multiple-input QFG transistors can also be used [5], allowing weighted averaging of signals in a simple and compact way. Note the different behavior of the circuit of Figure 1c for DC and AC small-signal and large-signal dynamic (or transient) operation. Capacitor C is an open circuit in DC, so the quiescent gate voltage is Vg Q = VBIAS, since there is not current flowing through the pseudoresistor. Hence, the bias point can be accurately set. For AC small-signal operation, the capacitor acts as a short circuit (more precisely, as an attenuator, due to the input capacitive divider), so that the AC gate voltage is vg = αvac, with vac the AC voltage at input Vsig. For transient operation with input frequencies larger than 1/τ (in practice from near DC), C acts as a floating battery with voltage VBIAS-VDC, with VDC the DC voltage at input Vsig. This is because C cannot be discharged rapidly through the pseudo-resistor. The signal is thus level-shifted by VBIAS-VDC and attenuated by factor α when it reaches the gate. In practice, nonlinearity of the pseudo-resistor may lead to nonlinear distortion and offset in the gate voltage. These issues are more relevant for large voltage swings at the pseudo-resistor terminals and depend on the implementation of the pseudo-resistors. Some of the most common fixed and tunable pseudo-resistors are shown in Figures 2 and 3, respectively.  The simplest pseudo-resistor is a diode-connected PMOS transistor operating in deep subthreshold, as shown in Figure 2a [5,35,36]. It is very compact, but the resistance obtained cannot be modified once fabricated, and it is very sensitive to PVT variations. Moreover, the I-V characteristics are asymmetric, so it becomes nonlinear for large voltage swings. These drawbacks are usually of minor concern when the pseudo-resistor is used in high-gain amplifiers operating in negative feedback, as long as the resistance remains high enough for the QFG transistor to process the lowest frequency of the input signal Vsig in Figure 1c. When symmetric I-V characteristics are required, elementary devices can be mirrored either in series or in parallel, as shown in Figure 2b,c, respectively, for the case of two elements [8]. The series connection is useful when large resistance values for wide voltage ranges are needed.
Some applications require tunable pseudo-resistors, where tuning can be achieved using a DC voltage [8,12] or a DC current [13], as shown in Figure 3. Further details and examples of pseudo-resistors can be found in [8]. Figure 4 illustrates various techniques based on QFG transistors that can be exploited to achieve low-voltage, energy-efficient amplifiers. They are described below. Multiple-input QFG transistors can also be used [5], allowing weighted averaging of signals in a simple and compact way. Note the different behavior of the circuit of Figure 1c for DC and AC small-signal and large-signal dynamic (or transient) operation. Capacitor C is an open circuit in DC, so the quiescent gate voltage is Vg Q = VBIAS, since there is not current flowing through the pseudoresistor. Hence, the bias point can be accurately set. For AC small-signal operation, the capacitor acts as a short circuit (more precisely, as an attenuator, due to the input capacitive divider), so that the AC gate voltage is vg = αvac, with vac the AC voltage at input Vsig. For transient operation with input frequencies larger than 1/τ (in practice from near DC), C acts as a floating battery with voltage VBIAS-VDC, with VDC the DC voltage at input Vsig. This is because C cannot be discharged rapidly through the pseudo-resistor. The signal is thus level-shifted by VBIAS-VDC and attenuated by factor α when it reaches the gate. In practice, nonlinearity of the pseudo-resistor may lead to nonlinear distortion and offset in the gate voltage. These issues are more relevant for large voltage swings at the pseudo-resistor terminals and depend on the implementation of the pseudo-resistors. Some of the most common fixed and tunable pseudo-resistors are shown in Figures 2 and 3, respectively.  The simplest pseudo-resistor is a diode-connected PMOS transistor operating in deep subthreshold, as shown in Figure 2a [5,35,36]. It is very compact, but the resistance obtained cannot be modified once fabricated, and it is very sensitive to PVT variations. Moreover, the I-V characteristics are asymmetric, so it becomes nonlinear for large voltage swings. These drawbacks are usually of minor concern when the pseudo-resistor is used in high-gain amplifiers operating in negative feedback, as long as the resistance remains high enough for the QFG transistor to process the lowest frequency of the input signal Vsig in Figure 1c. When symmetric I-V characteristics are required, elementary devices can be mirrored either in series or in parallel, as shown in Figure 2b,c, respectively, for the case of two elements [8]. The series connection is useful when large resistance values for wide voltage ranges are needed.

Application of QFG Transistors to Energy-Efficient Amplifier Design
Some applications require tunable pseudo-resistors, where tuning can be achieved using a DC voltage [8,12] or a DC current [13], as shown in Figure 3. Further details and examples of pseudo-resistors can be found in [8]. Figure 4 illustrates various techniques based on QFG transistors that can be exploited to achieve low-voltage, energy-efficient amplifiers. They are described below. The simplest pseudo-resistor is a diode-connected PMOS transistor operating in deep subthreshold, as shown in Figure 2a [5,35,36]. It is very compact, but the resistance obtained cannot be modified once fabricated, and it is very sensitive to PVT variations. Moreover, the I-V characteristics are asymmetric, so it becomes nonlinear for large voltage swings. These drawbacks are usually of minor concern when the pseudo-resistor is used in high-gain amplifiers operating in negative feedback, as long as the resistance remains high enough for the QFG transistor to process the lowest frequency of the input signal V sig in Figure 1c. When symmetric I-V characteristics are required, elementary devices can be mirrored either in series or in parallel, as shown in Figure 2b,c, respectively, for the case of two elements [8]. The series connection is useful when large resistance values for wide voltage ranges are needed.

Application of QFG Transistors to Energy-Efficient Amplifier Design
Some applications require tunable pseudo-resistors, where tuning can be achieved using a DC voltage [8,12] or a DC current [13], as shown in Figure 3. Further details and examples of pseudo-resistors can be found in [8]. Figure 4 illustrates various techniques based on QFG transistors that can be exploited to achieve low-voltage, energy-efficient amplifiers. They are described below.

QFG Input Differential Pair
A QFG differential pair can be used at the input of the amplifier to get AC coupling, as shown in Figure 4a, where the general case of N inputs is depicted [5]. Assuming matched input capacitors Ck, the differential AC voltage at the gates vGd is a weighted averaging of the AC differential inputs vkd = vk+ − vk-set by Ck/CT capacitor ratios: with Ck as the coupling capacitance of the k-th input and CT as the total capacitance at each gate node, which is approximately

QFG Input Differential Pair
A QFG differential pair can be used at the input of the amplifier to get AC coupling, as shown in Figure 4a, where the general case of N inputs is depicted [5]. Assuming matched input capacitors C k , the differential AC voltage at the gates v Gd is a weighted averaging of the AC differential inputs v kd = v k+ − v k-set by C k /C T capacitor ratios: with C k as the coupling capacitance of the k-th input and C T as the total capacitance at each gate node, which is approximately with C PR as the parasitic capacitance of the pseudo-resistor at the gate node. Usually, the first term in Equation (4) is dominant, so all the parasitic terms are negligible. Frequently, two-input QFG transistors are used to provide not only capacitive input coupling but also capacitive feedback.
Various implementation examples are presented in Section 3. Figure 4b shows how a QFG transistor can be used to implement an adaptive bias current source. In quiescent operation (V sig = 0), the circuit works as a current mirror and the quiescent output current is accurately set to I Q despite PVT variations. This current may be very low to save quiescent power. However, in dynamic operation (V sig =0), large output currents not limited by I Q can be generated, due to the AC coupling of V sig .

Class AB Output Stage
A basic scheme of a class AB output stage is shown at the left side of Figure 4c. A floating battery V AB allows biasing the NMOS transistor and transfers input signal variations from node A to node B, providing output currents larger than the quiescent current. A QFG implementation is shown at the right side of Figure 4c, where the circuit of Figure 4b is used as active load of the input transistor, with V sig = V in . Note that the QFG technique allows an optimal implementation of the floating battery, since it does not influence the biasing of the NMOS transistor, which is set by a matched diode-connected transistor, as in a class A topology. The value of V AB can be either positive or negative; it is adapted to the supply voltage employed, preserving the quiescent gate voltages. This is not the case in conventional implementations of V AB using, e.g., diode-connected transistors or resistors biased by DC current sources [65]. Moreover, the QFG implementation of V AB does not require additional supply voltage or quiescent power and does not add extra nodes.

Dynamic Cascode Biasing
In class AB amplifiers, cascode transistors may restrict the V DS voltage of the transistors that generate the large dynamic currents, making these transistors enter ohmic region and limiting slew rate. To avoid this effect, dynamic biasing of the cascode transistors is required. It is typically done as shown on the left side of Figure 4d. A floating battery V B transfers a level-shifted version of the input signal in A to node B, so that the cascode gate voltage increases for large signals, increasing the V DS of the input transistor. Again, an efficient implementation of the floating battery can be made by using a QFG cascode transistor, as shown on the right side of Figure 4d. As before, the implemented value of V B is not fixed; it is the difference between the quiescent cascode bias voltage V CN and the quiescent input voltage, so it is insensitive to PVT variations. As before, no extra quiescent power or supply voltage requirements are needed.

Class AB Current Mirrors
Current mirrors are widely used in amplifier design as current followers, i.e., to convey currents from a low-impedance input node to a high-impedance output node. For instance, they are used in current mirror (symmetric) amplifiers to convey (and optionally scale) the differential pair current to the output node. When these current mirrors must process bidirectional signal currents, class AB operation is required to achieve a class AB amplifier [22]. A schematic diagram of a class AB current mirror is shown on the left side of Figure 4e. Again, a floating battery V AB translates signal variations from node A to B, allowing dynamic currents larger than the quiescent currents. A QFG implementation is shown in Figure 4e [31], which consists, basically, on the replacement of the PMOS current sources on the left side by a two-output adaptive current source, like in Figure 4b. As before, this implementation features accurate quiescent currents not dependent on PVT variations. V AB is set by the difference between quiescent voltages at nodes A and B and can be either positive or negative. No extra supply voltage or quiescent power is required.

Energy-Efficient Amplifiers Based on QFG Techniques
In this section, the application of the QFG techniques and circuits to low-voltage power-efficient amplifiers is illustrated.

AC-Coupled Amplifiers
AC-coupled amplifiers allow accurate amplification (set by capacitance ratios), providing, at the same time, blocking of near-DC inputs. They are widely used to remove electrode offsets in physiological signals and also in interface circuits for monitoring of seismic activity or mechanical vibrations. For instance, electrode-skin interfaces may lead to offsets larger than 1 V [6], which can limit dynamic range and even saturate the amplifier if they are not removed.
Efficient AC-coupled amplifier implementations can be made using QFG input transistors, as shown in Figure 5 [5,6]. The circuit of Figure 5a can be used for singled-ended input and output, while Figure 5b provides single-ended output for differential inputs. The circuits of Figure 5c,d are fully differential topologies. Note that one (Figure 5a) or two (the other topologies) two-input QFG transistors are employed at the amplifier input. The QFG input capacitor C 1 goes to the input terminal, and the other QFG input capacitor C 2 is connected to the output. The midband gain is, in all cases, C 2 /C 1 . Note that the QFG pseudo-resistor is connected to the output in Figure 5a-c to provide DC-negative feedback. This is not the case in Figure 5d, where the amplifier is in open loop in DC. Hence, adequate design is required, in this case, to avoid saturation of the output [5]. An advantage of Figure 5d is that the amplifier DC input V BIAS can be set to a supply rail, so the circuit can work with ultra-low-supply voltages. Another advantage is that the pseudoresistor experiences little voltage swings, so a simple pseudo-resistor implementation can be used [5]. sources on the left side by a two-output adaptive current source, like in Figure 4b. As before, this implementation features accurate quiescent currents not dependent on PVT variations. VAB is set by the difference between quiescent voltages at nodes A and B and can be either positive or negative. No extra supply voltage or quiescent power is required.

Energy-Efficient Amplifiers Based on QFG Techniques
In this section, the application of the QFG techniques and circuits to low-voltage power-efficient amplifiers is illustrated.

AC-Coupled Amplifiers
AC-coupled amplifiers allow accurate amplification (set by capacitance ratios), providing, at the same time, blocking of near-DC inputs. They are widely used to remove electrode offsets in physiological signals and also in interface circuits for monitoring of seismic activity or mechanical vibrations. For instance, electrode-skin interfaces may lead to offsets larger than 1 V [6], which can limit dynamic range and even saturate the amplifier if they are not removed.
Efficient AC-coupled amplifier implementations can be made using QFG input transistors, as shown in Figure 5 [5,6]. The circuit of Figure 5a can be used for singled-ended input and output, while Figure 5b provides single-ended output for differential inputs. The circuits of Figure 5c,d are fully differential topologies. Note that one (Figure 5a) or two (the other topologies) two-input QFG transistors are employed at the amplifier input. The QFG input capacitor C1 goes to the input terminal, and the other QFG input capacitor C2 is connected to the output. The midband gain is, in all cases, C2/C1. Note that the QFG pseudo-resistor is connected to the output in Figure 5a-c to provide DC-negative feedback. This is not the case in Figure 5d, where the amplifier is in open loop in DC. Hence, adequate design is required, in this case, to avoid saturation of the output [5]. An advantage of Figure 5d is that the amplifier DC input VBIAS can be set to a supply rail, so the circuit can work with ultra-low-supply voltages. Another advantage is that the pseudoresistor experiences little voltage swings, so a simple pseudo-resistor implementation can be used [5].

Single-Stage Class AB Amplifiers
In terms of energy efficiency and silicon area, single-stage amplifiers are the best option, since they are load-compensated [65] and can feature near-optimal current efficiency if properly designed [5]. The single-stage differential pair amplifier provides simplicity and high current efficiency. A class AB QFG fully differential implementation can be achieved, as shown in Figure 6a

Single-Stage Class AB Amplifiers
In terms of energy efficiency and silicon area, single-stage amplifiers are the best option, since they are load-compensated [65] and can feature near-optimal current efficiency if properly designed [5]. The single-stage differential pair amplifier provides simplicity and high current efficiency. A class AB QFG fully differential implementation can be achieved, as shown in Figure 6a [17], where the common-mode feedback (CMFB) circuit is not shown. Transistors M1A-M2A are adaptively biased using two cross-coupled DC level shifters implemented by flipped voltage followers (FVF) [66] M1B-M1C and M2B-M2C. This adaptive biasing doubles the gain-bandwidth product (GBW) and allows dynamic currents in M1A and M2A larger than IB. The active load is implemented by adaptive QFG current sources M3B and M3C, like in Figure 4b.  To provide more DC gain, preserving current efficiency, a class AB telescopic cascode implementation can be used, as shown in Figure 6b [20]. In this case, adaptive biasing of the differential pair is also implemented by two FVFs, but in this case, the FVF outputs are connected. Hence, both FVFs act as a winner-take-all (WTA) circuit [67], setting the maximum of the input voltages level shifted by a DC voltage V B = V SG7, 8 Q to the common source of M 1 -M 2 . This, again, allows differential pair currents much larger than the quiescent current I B . Dynamic QFG cascode biasing, as in Figure 4d, is used to avoid that transistors M 1 -M 2 and M 3 -M 4 enter triode region when such large dynamic currents are generated.
Despite the high power efficiency of the amplifiers of Figure 6a,b, output swing is limited, since the input transistors are at the output branch. Alternative single-stage configurations with increased output swing can be obtained by including a current follower or a current amplifier to convey (and eventually scale) the differential pair current to the output terminal. This current follower/amplifier can be implemented by either a current mirror or a common-gate configuration, leading to the current-mirror (symmetric) and folded cascode amplifiers, respectively [22]. An example of class AB current mirror amplifier is presented in [23]. If high gain is required, a cascode current mirror implementation can be used, as shown in Figure 6c, in fully differential version (CMFB circuit not shown) [22]. The same adaptive biasing of Figure 6a is used, and two class AB cascode current mirrors, following the idea of Figure 4e, convey the current of the input transistors to the output terminals. A class AB folded cascode topology is shown in Figure 6d [19]. The same adaptive bias circuit is used for the input pair, and the NMOS current sources at the folding nodes are replaced by adaptively bias current sources following the scheme in Figure 4b. Dynamic biasing of cascode transistors can be used in Figure 6c,d to prevent slew rate (SR) degradation, as done in Figure 6b.

Multistage Class A/AB Amplifiers
When both high gain and high output swing are required, usually multistage amplifier topologies are employed. For instance, the conventional Miller amplifier can provide class AB output by employing the circuit of Figure 4c at the output stage [25]. The resulting circuit is shown in Figure 7a, yielding output currents much larger than the bias current I B and increasing GBW, due to the extra transconductance provided by M 8 . It is denoted as a class A/AB amplifier, since the input stage operates in class A and the output stage in class AB. Other examples of class A/AB amplifiers can be found in [26,27].

Multistage Class AB/AB Amplifiers
A drawback of class A/AB amplifiers is that the input stage can limit slew rate if it is not able to drive the compensation capacitor fast enough. To solve this drawback, class AB operation can also be included at the input stage, leading to class AB/AB topologies. Any of the class AB circuits of Figure 6 can be used at the first stage to this aim. A slightly different approach is shown in Figure 7b [28], where a scaled replica of the current in the output transistor M 5 is fed back to the differential pair. Another example of class AB/AB QFG implementation can be found in [29]. Appl. Sci. 2021, 11, x FOR PEER REVIEW 10 of 19

Multistage Class AB/AB Amplifiers
A drawback of class A/AB amplifiers is that the input stage can limit slew rate if it is not able to drive the compensation capacitor fast enough. To solve this drawback, class AB operation can also be included at the input stage, leading to class AB/AB topologies. Any of the class AB circuits of Figure 6 can be used at the first stage to this aim. A slightly different approach is shown in Figure 7b [28], where a scaled replica of the current in the output transistor M5 is fed back to the differential pair. Another example of class AB/AB QFG implementation can be found in [29].

Design Example: Super Class AB QFG Amplifier in a 130 nm CMOS Process
To illustrate the different approaches that can be employed to design energy-efficient amplifiers, a novel topology is presented in this section. It combines various techniques to achieve high performance and very low power consumption. Some of these techniques have been described above and some others are introduced here.

Requirements and Figures of Merit for Energy Efficiency
An ideal amplifier, in terms of energy efficiency, should achieve the highest smallsignal and large-signal performance for a given (and small) quiescent current. A usual way to quantify these requirements is using two conventional figures of merit [68]. The first one is FoML = SR·CL/Isupply = ImaxL/Isupply, with SR as the Slew Rate, CL the load capacitance, ImaxL = SR·CL as the maximum load current and Isupply as the total quiescent current consumption. FoML quantifies the large-signal performance for a given Isupply. The second one is FoMS = GBW·CL/Isupply, which quantifies the small-signal performance for a given Isupply.

Design Example: Super Class AB QFG Amplifier in a 130 nm CMOS Process
To illustrate the different approaches that can be employed to design energy-efficient amplifiers, a novel topology is presented in this section. It combines various techniques to achieve high performance and very low power consumption. Some of these techniques have been described above and some others are introduced here.

Requirements and Figures of Merit for Energy Efficiency
An ideal amplifier, in terms of energy efficiency, should achieve the highest smallsignal and large-signal performance for a given (and small) quiescent current. A usual way to quantify these requirements is using two conventional figures of merit [68]. The first one is FoM L = SR·C L /I supply = I maxL /I supply , with SR as the Slew Rate, C L the load capacitance, I maxL = SR·C L as the maximum load current and I supply as the total quiescent current consumption. FoM L quantifies the large-signal performance for a given I supply . The second one is FoM S = GBW·C L /I supply , which quantifies the small-signal performance for a given I supply . A power-efficient amplifier should also maximize current utilization [69], defined as the portion of supply current delivered to the load, which is optimal when the large dynamic currents are generated directly at the output branch without internal replication of them.
An optimal choice in terms of energy efficiency is the so-named super class AB amplifiers [69]. They are single-stage topologies combining adaptive biasing at the input differential pair and nonlinear current amplifiers to convey and additionally boost the differential pair current to the output. Super class AB amplifiers can potentially achieve very large FoM L , due to this double current boosting process, and can also achieve very large FoM S if the adaptive biasing and nonlinear current amplifiers employed provide enhanced transconductance. Moreover, current utilization is very high, as the large dynamic currents achieved are generated directly at the output transistors of the nonlinear current amplifier, right at the output branch. Figure 8a shows the proposed circuit, which is based on a recycling folded cascode topology [70]. The same adaptive bias circuit used in Figure 6b portion of supply current delivered to the load, which is optimal when the large dynam currents are generated directly at the output branch without internal replication of them An optimal choice in terms of energy efficiency is the so-named super class AB am plifiers [69]. They are single-stage topologies combining adaptive biasing at the input di ferential pair and nonlinear current amplifiers to convey and additionally boost the di ferential pair current to the output. Super class AB amplifiers can potentially achieve ver large FoML, due to this double current boosting process, and can also achieve very larg FoMS if the adaptive biasing and nonlinear current amplifiers employed provide en hanced transconductance. Moreover, current utilization is very high, as the large dynam currents achieved are generated directly at the output transistors of the nonlinear curren amplifier, right at the output branch. Figure 8a shows the proposed circuit, which is based on a recycling folded cascod topology [70]. The same adaptive bias circuit used in Figure 6b, formed by the FVFs M1C M1D and M2C-M2D, is employed. In quiescent conditions, M1C-M2C have the same VGS Q a M1A, M1B, M2A and M2B, and, since they have also the same size, neglecting mismatch an channel length modulation, they set a quiescent current IB in M1A, M1B, M2A, and M2B. Whe a differential signal is applied, the largest (winning) input voltage level shifted by the VSG of M1C-M2C appears at the common source of M1A, M1B, M2A and M2B. Hence, currents i these transistors are not limited by IB, due to the large currents that can be provided b the FVFs. The differential current amplifier employed to transfer and scale the currents in M and M2B to the output is a nonlinear cascode current mirror formed by M3A, M3B, M4A, M M3C, M4C, M5 and M6. It employs local common-mode feedback [69] by transistors MR MR2 acting as tunable active resistors. When a large differential current appears in M1 The differential current amplifier employed to transfer and scale the currents in M 1B and M 2B to the output is a nonlinear cascode current mirror formed by M 3A , M 3B , M 4A , M 4B , M 3C , M 4C , M 5 and M 6 . It employs local common-mode feedback [69] by transistors M R1 -M R2 acting as tunable active resistors. When a large differential current appears in M 1B -M 2B , a large voltage drop appears in M R1 -M R2 , which creates a large current in either M 3A or M 4A , which reaches the output. Hence, this nonlinear current mirror provides an additional dynamic current boosting.

Proposed Super Class AB Amplifier
Current starving is implemented in Figure 8a by two DC current sources that subtract part of the DC input current to the NMOS current mirrors. For a fixed current mirror gain K, current starving allows for decreasing the quiescent current of the current mirror output, thus increasing the amplifier output resistance and DC gain [71]. However, here, current starving is used to increase K without increasing static power. The starving factor used is 0.5, so half of the bias current (I B /2) is subtracted. As a result, K can be doubled in Figure 8a for the same quiescent current consumption.
Adaptive biasing of cascode transistors M 5 , M 6 , M 7 and M 8 is provided using the QFG technique of Figure 4d to avoid M 3A , M 4A , M 9 and M 10 entering triode region for large dynamic currents (which would strongly degrade SR). The simple pseudo-resistor of Figure 2a is enough, in this case.

Circuit Analysis
Routine small-signal analysis of the circuit of Figure 8a leads to a transconductance with g mi and r oi as the small-signal transconductance and output resistance of transistor M i , respectively, and R DS as the resistance of triode transistors M R1 and M R2 , which is where β i = µC ox (W/L) i is the transconductance factor of transistor M i . The GBW is GBW = G m /(2πC L ), with G m defined in Equation (5) and C L as the load capacitor. The small-signal gain is G m ·R out , with R out = g m8 r o8 r o10 ||[g m6 r o6 (r o4A ||r o2A )] as the output resistance of the amplifier. Using the simple MOS square law, an approximate expression can be found for the SR: with A as the differential input signal amplitude. Note that SR is not limited by the bias current, as expected from a class AB amplifier. Practical values of SR are, however, lower, due to nonideal effects not considered in Equation (7). Regarding thermal noise and noting that g m1A = g m1B = g m1C = g m2A = g m2B = g m2C , g m3A = g m4A , g m3B = g m4B and g m9 = g m10 , the input-referred noise density is with k B as the Boltzmann's constant, T as the absolute temperature, g mI as the transconductance of the transistors implementing the I B /2 current sources and δ as a parameter that varies from 1/2 to 2/3 from weak inversion to strong inversion. Note that transistors in the output branch have little influence on the input-referred noise, due to the large gain, according to theoretical expectations.
Note, also, that decreasing bias voltage V RES increases R DS and, hence, increases gain, GBW and SR and reduces input-referred noise. Unfortunately, it also reduces phase margin, which can be approximated by where f pND ≈ −1/[2π(R DS ||r o2B )C X ] is the frequency of the lowest nondominant pole, and C X is the parasitic capacitance at the nodes where the gates of M 3A and M 4A are connected. Hence, a tradeoff between gain, GBW, SR, input-referred noise and stability exists for a given C L . Tuning V RES allows for optimally balancing these parameters and compensating for PVT variations.  Figure 8b, where the layout plot is also shown, since the surface of the die is opaque.

Measurement Results
Supply voltages were ±0.5 V and I B = 3 µA. Cascode bias voltages V CP and V CN were −0.34 V and 0.3 V, respectively, and V RES was set to 480 mV. The measurement setup used is shown in Figure 9. Test PCB TDS5052B DSO 33522A AWG N9320B Figure 9. Measurement setup. Figure 9. Measurement setup.
For transient response, the input signal was a 1 MHz 0.4 Vpp square wave, with a −0.2 V DC level generated by an Agilent 33522A arbitrary waveform generator, and the output was displayed in a Tektronix TDS5052B oscilloscope. Total load capacitance was 140 pF. Both the input and transient response are plotted in Figure 10. The measured SR values for the rising and falling edge were 5.7 V/µs and −7.1 V/µs, respectively. Figure 11 shows the measured total harmonic distortion (THD) using a 30 kHz input tone, whose amplitude varies from 100 mVpp to 350 mVpp. Note that THD is below 1% in all this range.
The frequency response was also measured ( Figure 12) using a Keysight N9320B spectrum analyzer. Since an off-chip buffer was employed to avoid loading the analyzer, total load capacitance was C L = 120 pF. The cutoff frequency of the proposed OTA was 4.48 MHz, which corresponds approximately to the GBW, because of the dominant pole design.

Discussion
A summary of the main performance parameters of the amplifier is shown in Table  1, including parameters from other reported amplifiers for comparison. Since the fabricated amplifier is in unity-gain closed loop, open-loop performance parameters (DC gain, Phase Margin PM, Common-Mode Rejection Ratio CMRR and Power Supply Rejection Ratio PSRR) were obtained from post-layout simulations using BSIM4 MOSFET models and the Spectre simulator available in Cadence IC6.1.

Discussion
A summary of the main performance parameters of the amplifier is shown in Table 1, including parameters from other reported amplifiers for comparison. Since the fabricated amplifier is in unity-gain closed loop, open-loop performance parameters (DC gain, Phase Margin PM, Common-Mode Rejection Ratio CMRR and Power Supply Rejection Ratio PSRR) were obtained from post-layout simulations using BSIM4 MOSFET models and the Spectre simulator available in Cadence IC6.1. Note that the proposed amplifier showed improved small-signal and large-signal performance just drawing 30 µA from the ±0.5 V power supply. A graphical comparison of FoM L and FoM S with different reported amplifiers is shown in Figure 13, where the advantages of the proposed approach are evidenced. Note the good balance between both figures of merit, as deduced from their average value (FoM AVG ) in Table 1. The main drawback of the proposed amplifier is the extra silicon area required for the capacitors C BAT , employed for dynamic cascode biasing, as can be seen in Figure 8b. figures of merit, as deduced from their average value (FoMAVG) in Table 1. The main drawback of the proposed amplifier is the extra silicon area required for the capacitors CBAT, employed for dynamic cascode biasing, as can be seen in Figure 8b.

Conclusions
A comprehensive description of different circuit techniques based on QFG transistors and their application to energy-efficient amplifiers has been presented. Moreover, a new, low-power CMOS amplifier, using adaptive local common-mode feedback with current starving, WTA tail current biasing and QFG transistors for adaptive cascode biasing, has

Conclusions
A comprehensive description of different circuit techniques based on QFG transistors and their application to energy-efficient amplifiers has been presented. Moreover, a new, low-power CMOS amplifier, using adaptive local common-mode feedback with current starving, WTA tail current biasing and QFG transistors for adaptive cascode biasing, has been proposed. Measurement results of the amplifier fabricated in a 130 nm process show very large SR and GBW, maintaining very low static power consumption. The amplifier can be applied in ultra-low-power switched capacitor systems and in general, when both large capacitive loads and low quiescent power are required.