Generalized Structures for Switched-Capacitor Multilevel Inverter Topology for Energy Storage System Application

: The apparent advantages of Multilevel Inverter (MLI) topologies in handling medium and high power with less loss in switching and lower harmonic distortion in an output voltage waveform makes it better than the conventional inverter. However, the MLI topologies utilize a large number of DC power supplies and power semiconductor devices. They also have a higher value of total standing voltage (TSV). Moreover, capacitor voltage balancing problems, self-voltage boosting inability, and complex control techniques require a relook and improvement in their structure. More recently, Switched-Capacitor Multilevel Inverter (SCMLI) topologies have been proposed to overcome the shortcomings of MLIs. In this paper, a generalized structure for a single-phase switched capacitor multilevel inverter (SCMLI) with self-voltage boosting and self-voltage balancing capability is proposed. A detailed analysis of a general structure of SCMLI is presented. The comparative analysis of the structures is carried out with recently reported topologies to demonstrate superiority. An optimized low-frequency modulation controls the output voltage waveform. The simulation and experimental results are included in the paper for single-unit symmetric (9-level voltage) and asymmetric (17-level voltage) conﬁgurations. ,


Introduction
Nowadays, the alteration of power from DC to AC is an important process and performs a vital task in modern power system network and industrial processes powered by electric drives [1]. DC to AC conversion is carried out by power electronics converters. Due to high harmonic losses in two-level inverters, multilevel inverters are used in order to have highly efficient power electronics and drive systems [2]. The main property of the Multilevel Inverter (MLI) is to generate an output voltage waveform resembling a staircase using several voltage sources at the input, which results in the low value of total harmonics distortion (THD) and minimal values of electromagnetic interference (EMI) and voltage stress across switches [3]. The three classical topologies of MLI are Cascaded H-bridge inverter (CHB), Flying Capacitor Clamped inverter (FC), and Neutral Point Clamped inverter (NPC) [4]. Due to easy control and unique characteristics, they are practically implemented as alteration technology in various applications ranging from small-to large-scale industries. In order to achieve higher voltage levels, a large number of devices are required, which enhances the size and cost of MLIs [5]. At higher voltage levels, NPC and FC show capacitor voltage unbalancing problems besides the requirement 1 in red. Therefore, there are 2n total basic units from which n basic units are connected to the left side of the modified H-bridge and the remaining n basic units are on the right side of the bridge.  The capacitors C1,1, C1,2, C1,3, …, C1,n−1, C1,n are charged to V through switches S2,1, S2,2, S2,3, …, S2,n−1, S2,n, respectively, and switches S1,1, S1,2, S1,3, …, S1,n−1, S1,n are used for discharging the capacitors. The capacitors C2,1, C2,2, C2,3, …, C2,n−1, C2,n are charged to (2n + 1)V through switches S4,1, S4,2, S4,3, …, S4,n−1, S4,n, respectively, and switches S3,1, S3,2, S3,3, …, S3,n−1, S3,n are used for discharging the capacitors.

Comparative Analysis of the Proposed GSMLI Topology
The proposed generalized structure was compared with other recent topologies. The performance of various parameters such as numbers of diodes (N diode ), switches (N sw ), capacitors (N cap ), drivers (N dri ), and TSV p.u. , and cost function per level (CF/N L ), are shown in Figure 2. It may be noted that all these topologies are designed to generate seventeen levels of output voltage. Cost function per level (CF/N L ) is defined as  Here, α represents the contribution of TSV in the cost function The comparisons are carried out among the levels of generalized structure of the proposed topology and other topologies. The comparison is conducted in terms of numbers of switches, drivers, capacitors, diodes, and TSV when all generated the same levels. From Figure 2a, it can be observed that the number of switches required in the generalized structure in both methods (first and second) is less than the number of switches required by other topologies for the same number of levels. It can also be seen from Figure 2a that the number of switches required in the second method generalized structure is less than the switches required by the first method of generalized structure. From Figure 2b,c, it is clear that the number of driver circuits and capacitors required in GSMLI in both methods (first and second) is less than the number of drivers and capacitors required by other topologies for the same number of levels. In [28], there is no capacitor, which is why it is not shown in Figure 2c.
From Figure 2d, it is clear that the TSV (in per unit) in GSMLI (second method) is less than the other topologies when all generated the same number of levels. TSV (in per unit) in the GSMLI (first method) is higher than the CHB and in [30] when all generated the same number of levels; however, it requires less switches, drivers, and capacitors compared to CHB and in [30].

Analysis of the Basic Unit of GSMLI
The generalized topology presented in this work was simulated and experimentally verified by considering one unit in symmetric and asymmetric mode. It has also been tested for TSV, and optimal capacitance was calculated in this section. The basic units act as a level generator that can produce two voltage levels from a solitary DC power supply. Figure 3 shows the conducting paths of the proposed topology for asymmetric configuration. Switches S 2 and S 4 and diodes D 1 and D 2 of the basic units are utilized for the charging purpose of capacitors C 1 and C 2 , respectively, while switches S 1 and S 3 are used for discharging capacitors C 1 and C 2 , respectively, in order to take the participation of the capacitor voltages into consideration in voltage level generation. The switches used in the modified H-Bridge are T 1 , T 2 , T 3 , T 4 , T 5 , and T 6 . Positive voltage levels are generated by utilizing switches T 1 , T 4 , and T 6 , whereas negative voltage levels are generated by utilizing switches T 2 , T 3 , and T 5 . Thus, the operation of switch pairs (T 1 , T 2 ), (T 3 , T 4 ), (T 5 , T 6 ), (T 7 , T 8 ), (S 1 , S 2 ), and (S 3 , S 4 ) are complementary. This topology is capable of generating This topology is self-balancing for capacitor voltage because charging and discharging take place in an alternate manner and, if there is any voltage drop in capacitors voltage due to discharging, then it is regained during charging. This topology can damp out the disparate voltage between the capacitor and power supply, due to which it acts as a practically effective power circuit.
The generalized topology presented in this work was simulated and exp verified by considering one unit in symmetric and asymmetric mode. It ha tested for TSV, and optimal capacitance was calculated in this section. The bas as a level generator that can produce two voltage levels from a solitary DC pow Figure 3 shows the conducting paths of the proposed topology for asymmetric tion. Switches S2 and S4 and diodes D1 and D2 of the basic units are utilized for th purpose of capacitors C1 and C2, respectively, while switches S1 and S3 are u charging capacitors C1 and C2, respectively, in order to take the participation o itor voltages into consideration in voltage level generation. The switches used ified H-Bridge are T1, T2, T3, T4, T5, and T6. Positive voltage levels are generated switches T1, T4, andT6, whereas negative voltage levels are generated by utilizin T2, T3, and T5. Thus, the operation of switch pairs (T1, T2), (T3, T4), (T5, T6), (T7, and (S3, S4) are complementary. This topology is capable of generating 0V, ± VC1), ±V2, ±(V1 + V2), ±(V1 + VC1 + V2), ±(V2 + VC2), ±(V1 + V2 + VC2), and ±(V1 VC2) voltage levels. This topology is self-balancing for capacitor voltage becau and discharging take place in an alternate manner and, if there is any volta capacitors voltage due to discharging, then it is regained during charging. Th can damp out the disparate voltage between the capacitor and power sup which it acts as a practically effective power circuit.

Operating States
The proposed topology can be utilized in asymmetric and symmetric con Table 2 illustrates the switching states of T1 to T6 and S1 to S4, the charging and d states of capacitors C1 and C2 in a fastidious switching state. "C" and "D" indic capacitor is charged and discharged, respectively. "-" indicates that there is n the states of the capacitors. "1" denotes the on state of switches, while "0" den state of switches.
When both DC voltage sources have the same magnitude (V1 = V2), then it in symmetric configuration and produces 9 levels in 0V, ±V1, ±(V1 + VC1), ± and ±(2V1 + VC1 + VC2) output voltage waveform, which can be seen from Ta  Table 2, it can be observed that more levels are generated when both voltage so different magnitudes of voltage, i.e., asymmetric configuration.
To generate the maximum available voltage levels, it must be operated in a configuration and the magnitude of DC voltage sources V1 and V2 must be s 1:3 ratio. When it is operated in asymmetric configuration (3V1 = V2), it produc (0V, ±V1, ±(V1 + VC1), ±3V1, ±4V1, ±(4V1 + VC1), ±(3V1 + VC2), ±(4V1 + VC2), a VC1 + VC2)) in output voltage waveform, as shown in Table 2.   Total standing voltage (TSV) is one of the most important parameters w ing different inverter topologies. TSV is defined as the sum of the maximum b age (stress) across the semiconductor switches and diodes when the output v possible levels is generated at the output.

Operating States
The proposed topology can be utilized in asymmetric and symmetric configurations. Table 2 illustrates the switching states of T 1 to T 6 and S 1 to S 4 , the charging and discharging states of capacitors C 1 and C 2 in a fastidious switching state. "C" and "D" indicate that the capacitor is charged and discharged, respectively. "-" indicates that there is no change in the states of the capacitors. "1" denotes the on state of switches, while "0" denotes the off state of switches.
When both DC voltage sources have the same magnitude (V 1 = V 2 ), then it is operated in symmetric configuration and produces 9 levels in 0V, ±V 1 , ±(V 1 + V C1 ), ±(2V 1 + V C1 ), and ±(2V 1 + V C1 + V C2 ) output voltage waveform, which can be seen from Table 2. From Table 2, it can be observed that more levels are generated when both voltage sources have different magnitudes of voltage, i.e., asymmetric configuration.
Total standing voltage (TSV) is one of the most important parameters while designing different inverter topologies. TSV is defined as the sum of the maximum blocked voltage (stress) across the semiconductor switches and diodes when the output voltage of all possible levels is generated at the output.
The maximum value of blocked voltage across each switch in symmetric configuration , andV D2 are the blocked voltages across switches T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , S 1 , S 2 , S 3 , and S 4 respectively.
TSV in per unit is defined as where V o,max is the maximum value of output voltage TSV p.u in symmetric configuration is given as The maximum value of the blocked voltage across each switch in asymmetric configuration (V 1 = V and V 2 = 3V) is given as Appl. Sci. 2021, 11, 1319 11 of 20 TSV p.u in asymmetric configuration is given as

Capacitance Selection
The optimal value of capacitances for both switched capacitors (C 1 and C 2 ) is calculated based on the longest discharge time (LDT) over a complete cycle of the fundamental output voltage. The maximum quantity of charges from switched capacitors is discharged during LDT. Figure 4 shows the output voltage of this proposed topology (asymmetric) along with the LDT for both switched capacitors. The LDT for C 2 is high compared to C 1 .
The value of optimal capacitance for switched capacitor C2 can be calculated as From Equations (4) and (5), The amount of discharge during LDT for switched capacitor C1 can be calculated as From Equations (2), (3), and (7), we get QC1 as From Equations (5) and (8), the optimal capacitance (C1opt) for switched capacitor C1 is given: where p is the maximum allowable output voltage ripple in percentage, RL is load resistance, and V is input source voltage. From Equations (6) and (9), it can be observed that the optimal value of capacitances depends on the ripple in voltage, load resistance, and operating frequency. The variation of the optimal capacitance C2opt with frequency (at RL = 100 Ω) for different values of voltage ripples are shown in Figure 5a. The variation in the The amount of discharge during LDT for switched capacitor C 2 can be calculated as For resistive load, the output current during LDT can be expressed as Due to the application of a fundamental frequency scheme, the time t 8 , t 7 , and t 6 can be given as From Equations (1)-(3), we get Q C2 as The value of optimal capacitance for switched capacitor C 2 can be calculated as From Equations (4) and (5), Appl. Sci. 2021, 11, 1319 12 of 20 The amount of discharge during LDT for switched capacitor C 1 can be calculated as From Equations (2), (3), and (7), we get Q C1 as From Equations (5) and (8), the optimal capacitance (C 1opt ) for switched capacitor C 1 is given: where p is the maximum allowable output voltage ripple in percentage, R L is load resistance, and V is input source voltage. From Equations (6) and (9), it can be observed that the optimal value of capacitances depends on the ripple in voltage, load resistance, and operating frequency. The variation of the optimal capacitance C 2opt with frequency (at R L = 100 Ω) for different values of voltage ripples are shown in Figure 5a. The variation in the optimal capacitances (C 1opt and C 2opt ) with load resistance for different values of voltage ripples is shown in Figure 5b,d, respectively. From Figure 5b,d, it is clear that, for a particular value of voltage ripple, the values of optimal capacitances (C 1opt and C 2opt ) decrease as the load resistance increases. where φ is the phase angle between the fundamental output voltage and output current From Equations (1), (3), and (10), we get QC2 as From Equations (5) and (11), From Equations (3), (7), and (10), we get QC1 as From Equations (5) and (13), we get the optimal value of capacitance C1opt: For plotting the graph between the optimal capacitance and phase angle for different values of voltage ripple, we take I0max = 4A and V = 20 volt. Figure 5c,e show the variation in optimal capacitances (C1opt and C2opt) with phase angle for different voltage ripples. From these figures, it is clear that, for a particular value of voltage ripple, the optimal capacitance decreases as the phase angle increases. For R-L load, the output current can be expressed as i 0 (t) = I 0max sin(ωt − ϕ) (10) where ϕ is the phase angle between the fundamental output voltage and output current. From Equations (1), (3), and (10), we get Q C2 as From Equations (5) and (11), From Equations (3), (7), and (10), we get Q C1 as From Equations (5) and (13), we get the optimal value of capacitance C 1opt : For plotting the graph between the optimal capacitance and phase angle for different values of voltage ripple, we take I 0max = 4A and V = 20 volt. Figure 5c,e show the variation in optimal capacitances (C 1opt and C 2opt ) with phase angle for different voltage ripples. From these figures, it is clear that, for a particular value of voltage ripple, the optimal capacitance decreases as the phase angle increases.

Modulation Scheme
Different modulation schemes are used for controlling the MLI output voltage. Apart from reducing THD, fundamental frequency switching schemes are also capable of minimizing the switching losses. Fundamental switching frequency schemes such as Selective Harmonic Elimination (SHE), nearest level control, and space vector control are preferred for high power applications. The main disadvantage of SHE is to solve the system of nonlinear trigonometric transcendental equations, which consume more computational time. Hence, the SHE technique is not concerned with real-time (closed-loop) applications. The nearest control techniques can eliminate this drawback of SHE. Nearest Level Control (NLC) can be classified as (1) the nearest space vector control and (2) nearest level control [26]. In this work, an optimized nearest level control is utilized for controlling the output voltage and different carrier signals are compared with a reference signal [26]. The level generation method and block scheme are shown in Figures 6 and 7, respectively, for the NLC.
Hence, the SHE technique is not concerned with real-time (closed-loop) applications. The nearest control techniques can eliminate this drawback of SHE. Nearest Level Control (NLC) can be classified as (1) the nearest space vector control and (2) nearest level control [26]. In this work, an optimized nearest level control is utilized for controlling the output voltage and different carrier signals are compared with a reference signal [26]. The level generation method and block scheme are shown in Figures 6 and 7, respectively, for the NLC. nearest control techniques can eliminate this drawback of SHE. Nearest Level Control (NLC) can be classified as (1) the nearest space vector control and (2) nearest level control [26]. In this work, an optimized nearest level control is utilized for controlling the output voltage and different carrier signals are compared with a reference signal [26]. The level generation method and block scheme are shown in Figures 6 and 7, respectively, for the NLC. The equation for output voltage is shown below: where m is the modulation index and is expressed as

Simulation and Hardware Realization of the Basic Unit of the Proposed GSMLI Topologies
To assert the feasibility of the topologies, a MATLAB ® /Simulink-based simulation was carried out. For the simulation of this topology in symmetric configuration, V 1 and V 2 were taken equal to 12 volts and the other parameters were taken according to Table 3. For simulation of the proposed topology in asymmetric configuration, V 1 and V 2 were taken equal to 12 and 36 volts, respectively, and the other parameters were taken according to Table 3. Table 3. Parameters used in the simulation of the symmetrical and asymmetrical configurations.

Parameters Attributes
Switches (T 1 to S 4 ) IGBT/Diode Switching frequency (f s ) 50 Hz Load (purely resistive) 100 Ω, Capacitors C 1 ,C 2 2200 µF, 4300 µF Figure 8 shows the output voltage waveform and load current for the symmetric configuration (9 levels) of the proposed topology under R load for M at unity. Figure 9a shows the output voltage and current for dynamic change in modulation index and Figure 9b shows the total harmonics distortion (THD) in output voltage for symmetric configuration. Figure 10 show the voltage across capacitor C 1 (2.5% ripple) and capacitor C 2 (2.5% ripple) under the symmetric configuration. Figure 11 shows the waveforms of load current and output voltage for the asymmetric configuration (17 levels) of this topology at M = 1.0 with a purely resistive load. From these figures, it is confirmed that the proposed topology has the capability to generate all positive and negative voltage levels. A gain factor of 40 was taken to multiply the load current in order to have its scale be the same as that of the output voltage. While Figure 12a shows the voltage and current during dynamic change in the load from resistive to resistive-inductive, Figure 12b shows the voltage and current for the asymmetric case for a varying modulation index. THD in output voltage is 9.06% and 4.63% under the symmetric (9 levels) and asymmetric (17 levels) configurations, respectively. Due to the resistive load, the current harmonic spectrum is the same as the load voltage. Figure 13 show the voltage across capacitor C 1 (2.5% ripple) and capacitor C 2 (2.5% ripple) under the asymmetric configuration.

Parameters
Attributes Switches (T1 to S4) IGBT/Diode Switching frequency (fs) 50 Hz Load (purely resistive) 100 Ω, Capacitors C1,C2 2200 µF, 4300 µF Figure 8 shows the output voltage waveform and load current for the symmetric configuration (9 levels) of the proposed topology under R load for M at unity. Figure 9a shows the output voltage and current for dynamic change in modulation index and Figure 9b shows the total harmonics distortion (THD) in output voltage for symmetric configuration. Figures 10 show the voltage across capacitor C1 (2.5% ripple) and capacitor C2 (2.5% ripple) under the symmetric configuration. Figure 11 shows the waveforms of load current and output voltage for the asymmetric configuration (17 levels) of this topology at M = 1.0 with a purely resistive load. From these figures, it is confirmed that the proposed topology has the capability to generate all positive and negative voltage levels. A gain factor of 40 was taken to multiply the load current in order to have its scale be the same as that of the output voltage. While Figure 12a shows the voltage and current during dynamic change in the load from resistive to resistive-inductive, Figure 12b shows the voltage and current for the asymmetric case for a varying modulation index. THD in output voltage is 9.06% and 4.63% under the symmetric (9 levels) and asymmetric (17 levels) configurations, respectively. Due to the resistive load, the current harmonic spectrum is the same as the load voltage. Figure 13 show the voltage across capacitor C1 (2.5% ripple) and capacitor C2 (2.5% ripple) under the asymmetric configuration.        . Output voltage and load current for asymmetric configuration. Figure 11. Output voltage and load current for asymmetric configuration.
A laboratory prototype was developed in order to verify the simulation results and performance of the proposed SCMLI topology. Figure 14 shows the setup of the laboratory prototype for the proposed topology. In this experimental work, an Insulated Gate Bipolar Transistor (IGBT) (FGA25N120AND) with rating 1200 V/25 A was utilized as the power electronic switch signals to the switches by interfacing with SIMULINK.
Diode BEC0141 with a rating of 10A was used as the power diodes, an electrolyte capacitor with a rating of 4700 µF/63V was utilized as the switched capacitors, and TMS320 F28335 (Texas Instruments) was used as a controller for the generation of the gating prototype and controller isolated by using the TLP 250 (TOSHIBA) optocoupler. A Digital Storage Oscilloscope (TPS2024B TEKTRONIX) was employed for the measurement of the waveforms of voltage and current. For the experimental results of the symmetric configuration, voltage sources V1 and V2 were taken equal to 12 volts each. This resulted in a 9-level staircase output voltage with a 48-volt peak value, as shown in Figure 15a. Figure 15a also shows the load current when a purely resistive load of 100 Ω was connected at the output. Figure 15b shows the waveform of output voltage and load current when the DC voltage sources were connected across capacitors C1 and C2 in the symmetric configuration. Figure 15c,d show the waveform of voltage across capacitors C1 and C2 and the waveform of the blocked voltage across switches S1 and T1, respectively, in the symmetric configuration. The peak values of voltage across capacitors C1 and C2 are 12 volts. The peak value of the blocked voltage across switches S1 and T1 are 12 and 24 volts, respectively, which verify the equations for maximum blocked voltage by switches. For the experimental results of asymmetric configuration, voltage sources V1 and V2 were taken 12 volts and 36 volts, respectively. This resulted in a 17-level staircase output voltage with a 96-volt peak value, as shown in Figure 15e under the no-load condition. Figure 15f shows the output voltage and load current waveform when a purely resistive load of 100 Ω was connected at the output. Figure 15g shows the waveform of output voltage (17 levels) and load current to observe the levels clearly. Figure 15h-j show the waveform of the voltage across capacitors C1 and C2, the waveform of blocked voltage across switches S1 and S3, and the waveform of blocked voltage across switches T1 and T3, respectively, in an asymmetric configuration. The peak values of voltage across capacitors C1 and C2 are 12 and 36 volts. The peak values of the blocked voltage across switches S1, S3, T1, and T3 are 12, 12, 24, and 72 volts, respectively, which verify the equations for maximum blocked voltage by switches. It is clear that the experimental results have a close agreement with the simulation results.      A laboratory prototype was developed in order to verify the simulation results and performance of the proposed SCMLI topology. Figure 14 shows the setup of the laboratory prototype for the proposed topology. In this experimental work, an Insulated Gate Bipolar Transistor (IGBT) (FGA25N120AND) with rating 1200 V/25 A was utilized as the power electronic switch signals to the switches by interfacing with SIMULINK. Diode BEC0141 with a rating of 10A was used as the power diodes, an electrolyte capacitor with a rating of 4700 µF/63V was utilized as the switched capacitors, and TMS320F28335 (Texas Instruments) was used as a controller for the generation of the gating prototype and controller isolated by using the TLP 250 (TOSHIBA) optocoupler. A Digital Storage Oscilloscope (TPS2024B TEKTRONIX) was employed for the measurement of the waveforms of voltage and current. For the experimental results of the symmetric configuration, voltage sources V1 and V2 were taken equal to 12 volts each. This resulted in a 9-level staircase output voltage with a 48-volt peak value, as shown in Figure  15a. Figure 15a also shows the load current when a purely resistive load of 100 Ω was connected at the output. Figure 15b shows the waveform of output voltage and load current when the DC voltage sources were connected across capacitors C1 and C2 in the symmetric configuration. Figure 15c,d show the waveform of voltage across capacitors C1 and C2 and the waveform of the blocked voltage across switches S1 and T1, respectively, in the symmetric configuration. The peak values of voltage across capacitors C1 and C2 are 12 volts. The peak value of the blocked voltage across switches S1 and T1 are 12 and 24 volts, respectively, which verify the equations for maximum blocked voltage by switches. For the experimental results of asymmetric configuration, voltage sources V1 and V2 were taken 12 volts and 36 volts, respectively. This resulted in a 17-level staircase output voltage with a 96-volt peak value, as shown in Figure 15e under the no-load condition. Figure  15f shows the output voltage and load current waveform when a purely resistive load of 100 Ω was connected at the output. Figure 15g shows the waveform of output voltage (17 levels) and load current to observe the levels clearly. Figure 15h-j show the waveform of the voltage across capacitors C1 and C2, the waveform of blocked voltage across switches S1 and S3, and the waveform of blocked voltage across switches T1 and T3, respectively, in an asymmetric configuration. The peak values of voltage across capacitors C1 and C2 are 12 and 36 volts. The peak values of the blocked voltage across switches S1, S3, T1, and T3 are 12, 12, 24, and 72 volts, respectively, which verify the equations for maximum blocked voltage by switches. It is clear that the experimental results have a close agreement with the simulation results.   Figure 15. Waveform of (a) output voltage (25V/div) and load current (1.5 A/div). (b) Output voltage (20 V/div) and load current (0.5 A/div) when the voltage supply of 12V was connected across both capacitors. (c) Voltage across capacitors C1 and C2 (12 V/div). (d) Blocked voltage across switches S1 and T1 (12 V/div) in symmetric configuration. Waveform of (e) output voltage (60 V/div) under the no-load condition. (f) Output voltage (20V/div) and load current (0.75 A/div). (g) Output voltage (20V/div) and load current (0.75 A/div) for showing one complete cycle (f). Voltage across capacitors C1 and C2 (25 V/div). (i) Blocked voltage across switches S1 and S3 (25 V/div). (j) Blocked voltage across switches T1 and T3 (24 V/div) in asymmetric configuration.

Conclusions
In this paper, a generalized structure for the MLI topology was presented. The generalized structures including various basic units and bidirectional switches, and a detailed analysis of this structure for two different methods depending on the selection of voltage sources are also presented. In the topology, capacitor voltages are self-balanced, due to Figure 15. Waveform of (a) output voltage (25 V/div) and load current (1.5 A/div). (b) Output voltage (20 V/div) and load current (0.5 A/div) when the voltage supply of 12 V was connected across both capacitors. (c) Voltage across capacitors C1 and C2 (12 V/div). (d) Blocked voltage across switches S1 and T1 (12 V/div) in symmetric configuration. Waveform of (e) output voltage (60 V/div) under the no-load condition. (f) Output voltage (20 V/div) and load current (0.75 A/div). (g) Output voltage (20 V/div) and load current (0.75 A/div) for showing one complete cycle (h). Voltage across capacitors C 1 and C 2 (25 V/div). (i) Blocked voltage across switches S1 and S3 (25 V/div). (j) Blocked voltage across switches T1 and T3 (24 V/div) in asymmetric configuration.

Conclusions
In this paper, a generalized structure for the MLI topology was presented. The generalized structures including various basic units and bidirectional switches, and a detailed analysis of this structure for two different methods depending on the selection of voltage sources are also presented. In the topology, capacitor voltages are self-balanced, due to which no voltage balancing algorithm is needed. The comparative study of the generalized structure was performed, and the results show superior performance under various performance parameters. The generalized structure needs less switches, capacitors, drivers, and TSV (in per unit) for a higher level of voltage output. Finally, to validate the performance, the simulation and experimental results were presented for symmetric (9-level voltage) and asymmetric (17-level voltage) configurations for a basic unit. The experimental results validate the performance obtained by simulation. The proposed modular structure is suitable for solar PV application. Moreover, the 9 levels can find application in electric vehicle driven applications. The number of DC power sources becomes higher for a higher level of operation. Future research should focus on the replacement of the DC power supplies with capacitors for a cost-effective solution for high power applications.