Two-Terminal Electronic Circuits with Controllable Linear NDR Region and Their Applications

: Negative differential resistance (NDR) is inherent in many electronic devices, in which, over a speciﬁc voltage range, the current decreases with increasing voltage. Semiconductor structures with NDR have several unique properties that stimulate the search for technological and circuitry solutions in developing new semiconductor devices and circuits experiencing NDR features. This study considers two-terminal NDR electronic circuits based on multiple-output current mirrors, such as cascode, Wilson, and improved Wilson, combined with a ﬁeld-effect transistor. The undoubted advantages of the proposed electronic circuits are the linearity of the current-voltage characteristics in the NDR region and the ability to regulate the value of negative resistance by changing the number of mirrored current sources. We derive equations for each proposed circuit to calculate the NDR region’s total current and differential resistance. We consider applications of NDR circuits for designing microwave single frequency oscillators and voltage-controlled oscillators. The problem of choosing the optimal oscillator topology is examined. We show that the designed oscillators based on NDR circuits with Wilson and improved Wilson multiple-output current mirrors have high efﬁciency and extremely low phase noise. For a single frequency oscillator consuming 33.9 mW, the phase noise is − 154.6 dBc/Hz at a 100 kHz offset from a 1.310 GHz carrier. The resulting ﬁgure of merit is − 221.6 dBc/Hz. The implemented oscillator prototype conﬁrms the theoretical achievements.


Introduction
Negative differential resistance is a property of nonlinear semiconductor devices or special electronic circuits. An increase in the voltage drop across them results in a decrease in the flowing current.
Electronic devices with NDR are widely used in electronic and radio engineering systems of the broadest use, not only as of the main elements of amplifying [1], oscillating [2,3], multiplexing [4], static-random-access-memory (SRAM) [5], and switching circuits [6]. Recently, very promising is the use of NDR devices in radar [7], communication [8] and info-communication [9] circuits, analog-to-digital converters [10], and neural network circuits [11] due to the significant simplification of many circuitry solutions. Other possible applications of NDR devices can be found in the comprehensive overview by Reference [12].
Generally, we can divide NDR devices into N and Λ current-voltage characteristics devices and S characteristics devices. Since the article's main content is N-type NDR devices, we will analyze previously published studies for electronic structures with N-and Λ-type characteristics.
FET (TFET) based on a BP/InSe heterostructure in contact with graphene electrodes and covered with an hBN layer. In TFET, the tunneling current and the NDR region strongly depend on electrostatic gating. Qiu et al. [24] considered a graphene-based NDR device based on intrinsic armchair-edged nanoribbons with uniform widths. The device provides a sharp current peak of 1.2 µA at bias 0.8 V and a PVCR of 2.7. Kheirabadi et al. [25] considered armchair graphene nanoribbons for creating the NDR effect, which could have applications in nanoelectronics and nanosensors. Yang and Hwu [26] analyzed the tunable NDR characteristics of metal-insulator-semiconductor-insulator-metal tunnel diodes structure where the PVCR can be over 100. The NDR voltage interval exceeds 1 V. Xiong et al. [27] reported a four-terminal NDR device made from a 2D BP/Al 2 O 3 /BP sandwich structure with the PVCR exceeding 100 at room temperature. Kim et al. [28] considered an m-NDR device based on a BP/(ReS 2 + HfS 2 ) type-III double-heterostructure and its application to a ternary latch circuit capable of storing three logic states. Liang et al. [29] proposed a Λ-type NDR circuit based on a particular connection of three nMOS transistors with the same length and different widths of the channel. Gan et al. [30] considered a MOSheterojunction bipolar transistor (HBT) N-type NDR circuit based on three n-channel MOS and one SiGe HBT device with two power supplies. At specific supply voltages, the NDR circuit provides the PVCR of about 8. Chung et al. [31] reported a three-terminal Si-based NDR device by epitaxially growing a resonant interband tunnel diode atop the emitter of a Si/SiGe HBT on a silicon substrate. The device provides an adjustable PVCR. Semenov [32] proposed a Λ-type NDR BJT-metal-oxide-semiconductor FET (MOSFET) circuit applied to periodic and chaotic mode oscillators. Gan et al. [33] considered a novel NDR circuit comprising nMOS transistors and HBT with application to inverter design based on 0.35 µm SiGe technology. Ulansky et al. [34] presented five electronic circuits of NDR VCOs based on a GaAs transistor and single-output BJT CM. Ulansky et al. [35] considered an NDR circuit comprising a FET and a simple BJT CM with multiple outputs that control the slope of the current-voltage curve by changing the number of CM outputs. Yang [36] investigated a resonant tunneling electronic circuit with reactance elements having high and multiple peak-to-valley current density ratios displayed in the NDR curve. Kadioglu [37] considered a monolayer structure based on vanadium phosphide with a current-voltage characteristic having the NDR region. Rathi et al. [38] observed an NDR region in the current-voltage curve in graphene oxide two-terminal device with precise control of carbon-oxygen ratio. The fabricated novel electronic device can find application in switches and oscillators. Sharma et al. [39] synthesized graphene oxide quantum dots based on graphene oxide, cysteine, and H 2 O 2 having N-type current-voltage characteristics with PVCR of 4.7. Shim et al. [40] demonstrated an NDR device on the base of a phosphorene/rhenium disulfide (BP/ReS 2 ) heterojunction. It has a high PVCR of 4.2 at room temperature. The peak and valley currents are 3 and 0.7 nA, respectively.
We can draw the following conclusions from the review of published studies: 1.
In most of the published studies, there is no possibility of controlling the PVCR. The PVCR control is available in the NDR devices considered in the studies [26,27,31,39], but the maximum current levels are in the nA and µA ranges. In the NDR circuit [17], the control of PVCR is possible in the mA range by changing the value of one of the resistors. Figure 1 shows a two-terminal electronic circuit with a controllable NDR region. The circuit comprises a voltage divider R c , R d , an n-channel FET T 0 , a current mirror with m (m = 0, 1, 2, . . . ) additional outputs (mirrored current sources), and a power supply V 1,2 .

Two-Terminal NDR Circuits
Appl. Sci. 2021, 11, 9815 4 of 33 Figure 1 shows a two-terminal electronic circuit with a controllable NDR region. The circuit comprises a voltage divider Rc, Rd, an n-channel FET T0, a current mirror with m (m = 0, 1, 2,…) additional outputs (mirrored current sources), and a power supply V1,2. The circuit of Figure 1 has N-type current-voltage characteristics between nodes 1 and 2, as shown in Figure 2. The slope of the NDR region in the current-voltage characteristics depends on the number (m) of the additional mirrored current sources I2. In Figure 2, the green curve corresponds to m = 0, the blue curve to m = 1, and the red curve to m = 2. As seen in Figure 2, the current-voltage characteristics have four regions. In the first (0, VX) and fourth (VZ, ∞) regions, the current I1 depends only on the voltage V1,2. In these regions, all transistors are off. In the second region (VX, VY), all transistors are on. Transistor T0 operates in the ohmic region, and current I1 increases. We should also note that the voltage VY does not depend on the value of m, i.e., VYi = VY, i = 0, 1,…, m. In the third region (VY, VZ), transistor T0 operates in the saturation region and current I1 decreases due to a decrease in the gate-source voltage. The current I1 consists of two currents in the NDR region: the current through resistor Rc and m +1 currents I2. The current through resistor Rc is due to power supply V1,2 and the drain-current ID of transistor T0. Thus, the current I1 is given by The circuit of Figure 1 has N-type current-voltage characteristics between nodes 1 and 2, as shown in Figure 2. The slope of the NDR region in the current-voltage characteristics depends on the number (m) of the additional mirrored current sources I 2 . In Figure 2, the green curve corresponds to m = 0, the blue curve to m = 1, and the red curve to m = 2. As seen in Figure 2, the current-voltage characteristics have four regions. In the first (0, V X ) and fourth (V Z , ∞) regions, the current I 1 depends only on the voltage V 1,2 . In these regions, all transistors are off. In the second region (V X , V Y ), all transistors are on. Transistor T 0 operates in the ohmic region, and current I 1 increases. We should also note that the voltage V Y does not depend on the value of m, i.e., V Yi = V Y , i = 0, 1, . . . , m. In the third region (V Y , V Z ), transistor T 0 operates in the saturation region and current I 1 decreases due to a decrease in the gate-source voltage. Figure 1 shows a two-terminal electronic circuit with a controllable NDR region. The circuit comprises a voltage divider Rc, Rd, an n-channel FET T0, a current mirror with m (m = 0, 1, 2,…) additional outputs (mirrored current sources), and a power supply V1,2. The circuit of Figure 1 has N-type current-voltage characteristics between nodes 1 and 2, as shown in Figure 2. The slope of the NDR region in the current-voltage characteristics depends on the number (m) of the additional mirrored current sources I2. In Figure 2, the green curve corresponds to m = 0, the blue curve to m = 1, and the red curve to m = 2. As seen in Figure 2, the current-voltage characteristics have four regions. In the first (0, VX) and fourth (VZ, ∞) regions, the current I1 depends only on the voltage V1,2. In these regions, all transistors are off. In the second region (VX, VY), all transistors are on. Transistor T0 operates in the ohmic region, and current I1 increases. We should also note that the voltage VY does not depend on the value of m, i.e., VYi = VY, i = 0, 1,…, m. In the third region (VY, VZ), transistor T0 operates in the saturation region and current I1 decreases due to a decrease in the gate-source voltage. The current I1 consists of two currents in the NDR region: the current through resistor Rc and m +1 currents I2. The current through resistor Rc is due to power supply V1,2 and the drain-current ID of transistor T0. Thus, the current I1 is given by The current I 1 consists of two currents in the NDR region: the current through resistor R c and m + 1 currents I 2 . The current through resistor R c is due to power supply V 1,2 and the drain-current I D of transistor T 0 . Thus, the current I 1 is given by

Two-Terminal NDR Circuits
Outside the region (V X , V Z ), the current I 1 is only due to the power supply voltage V 1,2 . Further, we assume the matching of all transistors in the multiple-output CMs. As is well-known [40], for large transistor dc gain h FE , the currents I 2 and I D are approximately identical. The magnitude of the difference in currents I 2 and I D depends on the selected CM. Figure 3 shows a two-terminal NDR circuit with the multiple-output cascode CM (MCCM). The following relation links currents I 2 and I D [41]: Further, we assume the matching of all transistors in the multiple-output CMs. As is well-known [40], for large transistor dc gain hFE, the currents I2 and ID are approximately identical. The magnitude of the difference in currents I2 and ID depends on the selected CM. Figure 3 shows a two-terminal NDR circuit with the multiple-output cascode CM (MCCM). The following relation links currents I2 and ID [41]: By substitution (2) to (1), we obtain the total current in the NDR region: The advantage of using cascode CM in the two-terminal NDR circuit is its high output resistance. The disadvantage is a mismatch between currents I2 and ID.  Figure 4 shows a two-terminal NDR circuit using MWCM. With finite Early voltage VA, the currents I2 and ID are related as follows [41]: where VEB3 is the emitter-base voltage of transistor T3. By substitution (2) to (1), we obtain the total current in the NDR region: The advantage of using cascode CM in the two-terminal NDR circuit is its high output resistance. The disadvantage is a mismatch between currents I 2 and I D . Figure 4 shows a two-terminal NDR circuit using MWCM. With finite Early voltage V A , the currents I 2 and I D are related as follows [41]: where V EB3 is the emitter-base voltage of transistor T 3 .
Substituting (4) to (1) gives the following equation for the total current in the NDR region: The advantage of using MWCM in the NDR circuit of Figure 1 is high output resistance and a slight mismatch between master branch current (I D ) and slave branch current (I 2 ). The disadvantage is the difference in collector-emitter voltages V EC1 and V EC2 , which is equal to voltage V EB3 . Appl. Sci. 2021, 11, x FOR PEER REVIEW 6 of 33 Substituting (4) to (1) gives the following equation for the total current in the NDR region: The advantage of using MWCM in the NDR circuit of Figure 1 is high output resistance and a slight mismatch between master branch current (ID) and slave branch current (I2). The disadvantage is the difference in collector-emitter voltages VEC1 and VEC2, which is equal to voltage VEB3. Figure 5 shows a two-terminal NDR circuit with MIWCM. The improved Wilson CM introduces a diode-connected transistor T4 equalizing the collector-emitter voltages of transistors T1 and T2. Therefore, Equation (4) is reduced to [41] Substituting (6) to (1), we obtain an equation for the total current in the NDR region: Analysis of (3), (5), and (7) shows that the total current I1 in the NDR region is a function of the drain current of transistor T0, which is an n-channel FET. For the existence of   Substituting (4) to (1) gives the following equation for the total current in the NDR region: The advantage of using MWCM in the NDR circuit of Figure 1 is high output resistance and a slight mismatch between master branch current (ID) and slave branch current (I2). The disadvantage is the difference in collector-emitter voltages VEC1 and VEC2, which is equal to voltage VEB3. Figure 5 shows a two-terminal NDR circuit with MIWCM. The improved Wilson CM introduces a diode-connected transistor T4 equalizing the collector-emitter voltages of transistors T1 and T2. Therefore, Equation (4) is reduced to [41] Substituting (6) to (1), we obtain an equation for the total current in the NDR region: Analysis of (3), (5), and (7) shows that the total current I1 in the NDR region is a function of the drain current of transistor T0, which is an n-channel FET. For the existence of Substituting (6) to (1), we obtain an equation for the total current in the NDR region: Analysis of (3), (5), and (7) shows that the total current I 1 in the NDR region is a function of the drain current of transistor T 0 , which is an n-channel FET. For the existence of the NDR region, the transistor T 0 must have a negative threshold voltage. Therefore, suitable types of transistors are JFET, depletion metal-oxide-semiconductor FET (DMOSFET), MESFET, HEMT, and PHEMT. As shown in Reference [35], the two-terminal NDR circuit with a multiple-output simple CM has an NDR effect when transistor T 0 is in saturation mode. In the circuits presented by Figures 3-5, transistor T 0 should also operate in the saturation mode in the NDR region. Thus, to calculate the current I 1 , it is necessary to model the current I D for the selected type of transistor T 0 .

Modeling the Drain Current of Transistor T 0
As we can see from (3), (5), and (7), to calculate the total current I 1 in the NDR region, we should know the drain current I D of the transistor T 0 . The modeling of current I D depends on the type of transistor T 0 .
If transistor T 0 is a JFET, the Shockley equation well represents the drain current in the saturation region: where I DSS is the drain current of transistor T 0 at zero bias, V P is the negative pinch-off voltage, and V GS is the gate-source voltage. The voltage between gate and source of transistor T 0 is negative and consists of two parts: the voltage due to voltage divider R c , R d : and the voltage drop across resistor R c because of the current through this resistor, i.e., Combining (9) and (10) gives Substituting (11) to (8) and providing some mathematical manipulations, we obtain the following quadratic equation for determining the value of the current I D : If transistor T 0 is a MESFET, we can model the current I D by one of the nonlinear large-signal models [42][43][44]. For example, the popular Curtice model in the saturation region is as follows [42]: where b is the transconductance, λ is the channel length modulation coefficient, α is the coefficient of the hyperbolic tangent function, V DS is the drain-source voltage, and V TH is the threshold voltage. The voltage V DS we find by applying Kirchhoff's voltage law to the circuit of Figure 1.
where V D is the voltage at the drain of transistor T 0 . Substituting V GS from (11) into (14), we obtain It is evident that, for all circuits in Figures 3-5, the voltage (V 1,2 − V D ) is equal to where V EB is the emitter-base voltage of BJT used in the current mirror. Substituting (11) and (15) into (13), we obtain the following nonlinear equation for determining the value of the current I D : Solving Equation (17), we can find the value of I D for the selected two-terminal NDR circuit. Then, by substitution of I D into (3), (5), or (7), we can calculate the total current I 1 .
The large-signal modeling of HEMT and PHEMT is quite similar to MESFET modeling [45].

Modeling the Negative Differential Resistance
We find the NDR at the operating point as follows: Let us determine R diff for the two-terminal NDR circuits shown in . Substituting current I 1 from (3), (5), and (7) into (18) and taking the first derivative of function I 1 concerning variable V 1,2 , we obtain the following equations for the NDR: for the two-terminal NDR circuit with an MCCM, for the two-terminal NDR circuit with an MWCM, (20) and, for the two-terminal NDR circuit with a MIWCM, The derivative dI D /dV 1,2 in (19)-(21) cannot be derived analytically. Therefore, we can replace this derivative with the ratio of ∆I D /∆V 1,2 in the vicinity of the operating point. Then, calculate the increment of current ∆I D by (12) for a JFET and by (17) for a MESFET, HEMT, or PHEMT. In the oscillator circuits of Figures 6-8, capacitors C 1 , C 2 , and inductor L establish a resonant tank circuit. Capacitor C a is a feedback element used to improve the start-up of the oscillator. Capacitor C b serves as a noise killer at the drain of transistor T 0 .

Negative Differential Resistance Oscillators
The two-terminal circuits shown in Figures 3-5 can be used for constructing singlefrequency NDR oscillators.

Negative Differential Resistance Oscillators
The two-terminal circuits shown in Figures 3-5 can be used for constructing singlefrequency NDR oscillators.

Negative Differential Resistance Oscillators
The two-terminal circuits shown in Figures 3-5 can be used for constructing singlefrequency NDR oscillators.     We show later that the NDR oscillator performance depends on the selected CM and the number of additional current sources I 2 .
The main characteristics of oscillators are frequency of operation, phase noise, harmonic distortions, and power consumption. Designers use several merit figures combining some or all of the key features to compare different oscillators [46,47].
The most common figure of merit (FOM) is given by [48] FOM where f of is the offset frequency from the carrier frequency f c , PN(f of ) is the oscillator phase noise at offset frequency f of , and P dis is the oscillator dissipation power. The second term allows us to compare oscillators operating at different frequencies. Thus, this criterion is invariant to the oscillator frequency. According to (22), the less FOM, the more efficient oscillator.
For self-excitation of the oscillator, it is necessary to compensate for the tank circuit's losses. Negative differential resistance of the oscillator's electronic circuit carries such compensation for the tank circuit losses. Therefore, the condition for self-excitation of the NDR oscillator has the following form [49]: where |R diff | is the absolute value of the NDR at the operating point calculated by (19)-(21), and R Q is the loaded tank circuit resistance at the resonance. The loaded tank circuit resistance at resonance is [50] (p. 905) where ρ is the characteristic impedance of the tank circuit, and Q l is the loaded quality factor of the tank circuit.

Negative Differential Resistance Voltage-Controlled Oscillators
Voltage-controlled oscillators are crucial elements of modern instrumentation, communication, navigation, and radar systems. We can classify VCOs as negative impedance (NI) and NDR oscillators. In the NI VCOs, the real part of the input impedance has a negative sign [51,52]. This negative resistance compensates for the losses in the tank circuit. In the NDR VCOs, a negative resistance induced into the tank circuit neutralizes the tank circuit losses; this resistance is inversely proportional to the absolute value of R diff [53].
The two-terminal circuits of

Simulation and Calculation of Current-Voltage Characteristics
Let us simulate the current-voltage characteristics for two-terminal NDR circuits presented in Figures 3-5 by Multisim 14.0. As transistor T0, we use MMBFU310LT1 and BFT92W as transistors in current mirrors. We select the following resistor values: Rc = 1 kΩ and Rd = 2 kΩ.

Simulation and Calculation of Current-Voltage Characteristics
Let us simulate the current-voltage characteristics for two-terminal NDR circuits presented in

Simulation and Calculation of Current-Voltage Characteristics
Let us simulate the current-voltage characteristics for two-terminal NDR circuits presented in Figures 3-5 by Multisim 14.0. As transistor T 0 , we use MMBFU310LT1 and BFT92W as transistors in current mirrors. We select the following resistor values: R c = 1 kΩ and R d = 2 kΩ. Figures 12-14 show the current-voltage characteristics for the two-terminal NDR circuits with different multiple-output CMs. Table 1 shows the values of voltages and currents at the breakpoints of the curves. Analysis of current-voltage characteristics in Figures 12-14 and data in Table 1 leads to the following conclusions: all two-terminal NDR circuits have the same voltages V X , V Y , and V Z and currents I X and I Z for any value of m, two-terminal NDR circuit with MCCM has the smallest value of current I Y for any value of m, two-terminal NDR circuit with MIWCM has the most considerable value of current I Y for any value of m, and two-terminal NDR circuits with MCCM, MWCM, and MIWCM have almost linear dependence of current on voltage in the NDR region.  Table 1 leads to the following conclusions: all two-terminal NDR circuits have the same voltages VX, VY, and VZ and currents IX and IZ for any value of m, two-terminal NDR circuit with MCCM has the smallest value of current IY for any value of m, two-terminal NDR circuit with MIWCM has the most considerable value of current IY for any value of m, and two-terminal NDR circuits with MCCM, MWCM, and MIWCM have almost linear dependence of current on voltage in the NDR region.    Table 1 leads to the following conclusions: all two-terminal NDR circuits have the same voltages VX, VY, and VZ and currents IX and IZ for any value of m, two-terminal NDR circuit with MCCM has the smallest value of current IY for any value of m, two-terminal NDR circuit with MIWCM has the most considerable value of current IY for any value of m, and two-terminal NDR circuits with MCCM, MWCM, and MIWCM have almost linear dependence of current on voltage in the NDR region.   Since current IZ is the same for all two-terminal NDR circuits, and current IY is different, the slope of the current-voltage characteristics in the NDR region is higher for the greater value of current IY. Therefore, we can order the absolute negative resistance values of various two-terminal NDR circuits according to the following inequality: , Since current I Z is the same for all two-terminal NDR circuits, and current I Y is different, the slope of the current-voltage characteristics in the NDR region is higher for the greater value of current I Y . Therefore, we can order the absolute negative resistance values of various two-terminal NDR circuits according to the following inequality: where R C di f f , R W di f f , and R IW di f f are, respectively, the absolute values of NDR in the two-terminal circuits with cascode, Wilson, and improved Wilson CM.
Thus, inequalities (23) and (25) indicate that the oscillator with multiple-output improved Wilson CM has the most considerable self-excitation ability. In addition, the oscillator with multiple-output cascode CM has the least self-excitation ability.
For comparison with the simulation results, we calculate the current I 1 using (3), (5), and (7) with the following data of transistors MMBFU310LT1 and BFT92W: I DSS = 50 mA, V P = -3.5 V, V A = 11 V, and V EB3 = 0.6 V. We use the same values of resistors R c and R d as in the simulation. Figures 15 and 16 show the calculated dependences of current-voltage characteristics in the NDR region for different two-terminal circuits. Tables 2 and 3 show the calculated currents I Y and I Z and the relative accuracy of the I Y current calculation ∆I Y %, where ∆I Y % is given by As shown in Table 3, the highest accuracy of current I Y calculation when m = 0 belongs to Equations (5) and (7) for the two-terminal NDR circuit with an MWCM and MIWCM. The highest accuracy of the current I Y calculation when m = 1, 2 has Equation (5) for the two-terminal NDR circuit with an MWCM. The worst accuracy of the current I Y calculation when m = 0, 1, 2 has Equation (3) for the two-terminal NDR circuit with an MCCM.
In general, we should note that the worst accuracy does not exceed 12.3%, which indicates a sufficient engineering accuracy for calculating the current I Y . A practically zero error exists in calculating the current I Z .
in the NDR region for different two-terminal circuits. Tables 2 and 3 show the calculated currents IY and IZ and the relative accuracy of the IY current calculation ΔIY %, where ΔIY % is given by    % is given by      Now, let us simulate the current-voltage characteristics for two-terminal NDR circuits presented in Figures 3-5 when transistor T 0 is a PHEMT. We select ATF34143 as transistor T 0 and MRFC521 as transistors in BJT CM and choose the following resistor values: R c = 300 Ω and R d = 4 kΩ. Figures 17-19 show the current-voltage characteristics for the PHEMT based twoterminal NDR circuits with different multiple-output CM. Table 4 shows the values of voltages and currents at the breakpoints of characteristics. From the analysis of Table 4, the same conclusions follow as from the study of Table 1. As in using JFET, the PHEMT based two-terminal circuits also have a linear current dependence on voltage in the NDR region. As shown in Table 3, the highest accuracy of current IY calculation when m = 0 belongs to Equations (5) and (7) for the two-terminal NDR circuit with an MWCM and MIWCM. The highest accuracy of the current IY calculation when m = 1, 2 has Equation (5) for the two-terminal NDR circuit with an MWCM. The worst accuracy of the current IY calculation when m = 0, 1, 2 has Equation (3) for the two-terminal NDR circuit with an MCCM.
In general, we should note that the worst accuracy does not exceed 12.3%, which indicates a sufficient engineering accuracy for calculating the current IY. A practically zero error exists in calculating the current IZ.
Now, let us simulate the current-voltage characteristics for two-terminal NDR circuits presented in Figures 3-5 when transistor T0 is a PHEMT. We select ATF34143 as transistor T0 and MRFC521 as transistors in BJT CM and choose the following resistor values: Rc = 300 Ω and Rd = 4 kΩ. Figures 17-19 show the current-voltage characteristics for the PHEMT based two-terminal NDR circuits with different multiple-output CM. Table 4 shows the values of voltages and currents at the breakpoints of characteristics. From the analysis of Table 4, the same conclusions follow as from the study of Table 1. As in using JFET, the PHEMT based twoterminal circuits also have a linear current dependence on voltage in the NDR region.     We also calculate the current I1 at voltages VX, VY, and VZ using Equations (3), (5) and (7) Tables 5 and 6 show the calculated currents IY and IZ and the relative accuracy of the IY current calculation ΔIY %. The conclusions concerning the accuracy of the current IY calculation for Table 6 are the same as those for Table 3.
We should note that the accuracy of calculating the current ID by Formula (17) is quite high. Indeed, for all two-terminal NDR circuits at VY = 2.8 V, the current ID(simulated) = 2.79 mA, and the current ID(calculated) = 2.67 mA. Therefore, ΔID % = -4.5 %, where ΔID % is the relative accuracy of calculating the current ID by formula

Type of NDR Circuit → Two-Terminal NDR Circuit with Multiple-Output
Parameter of I-V Characteristic ↓  We also calculate the current I 1 at voltages V X , V Y , and V Z using Equations (3), (5) and (7) Tables 5 and 6 show the calculated currents I Y and I Z and the relative accuracy of the I Y current calculation ∆I Y %. The conclusions concerning the accuracy of the current I Y calculation for Table 6 are the same as those for Table 3.

Improved Wilson Current Mirror
We should note that the accuracy of calculating the current I D by Formula (17) is quite high. Indeed, for all two-terminal NDR circuits at V Y = 2.8 V, the current I D (simulated) = 2.79 mA, and the current I D (calculated) = 2.67 mA. Therefore, ∆I D % = -4.5 %, where ∆I D % is the relative accuracy of calculating the current I D by formula

Simulation of Negative Differential Resistance
By inequality (23), the steepness of the current-voltage characteristics in the vicinity of the operating point significantly affects the self-excitation of an oscillator. The less the absolute value of the differential resistance, the greater is the probability of self-excitation of the oscillator. Table 7 shows the simulation results of the differential resistance at the operating point V 1,2 = 4 V for two-terminal NDR circuits shown in Figures 3-5 using the same input data as Table 4. As shown in Table 7, the smallest absolute value of NDR at the operating point has a two-terminal NDR circuit with an improved Wilson CM. The NDR circuit with a Wilson CM has a little greater absolute value of NDR. The circuit with a cascode CM has the most considerable absolute value of NDR for any m. Thus, the improved Wilson and Wilson CM oscillators have the best start-up conditions due to inequality (23).

Simulation of Oscillator Characteristics
Let us simulate the characteristics for oscillators presented in Figures 6-8 by ADS2020. As transistor T 0 , we use ATF34143 and MRFC521 as transistors in BJT CM. We select chip inductor 0604HQ-1N1XJR (1.15 nH), and C 1 = C 2 = 1 pF, R c = 300 Ω, R d = 4 kΩ, C b = 300 nF, and V 1,2 = 4 V for all oscillators. We selected the value of capacitance C a from the condition of minimizing the phase noise of each oscillator.
We use FOM (22) to compare oscillators shown in Figures 6-8. Table 8 shows the results of the oscillators' simulation under the assumption that load resistance (R L ) is infinite. As shown in Table 8, oscillators with MCCM, MWCM, and MIWCM have the best FOM value when m is 0, 2, and 1, respectively. Among all oscillators, the best FOM of −227.1 dBc/Hz has the one with MWCM when m = 2. For each value of m in Table 8, oscillators with MWCM and MIWCM have significantly better FOM than the oscillator with MCCM. For each value of m, the oscillator with MCCM has the highest oscillation frequency, the lowest power of dissipation, and the worst phase noise. Figure 20 shows the dependence of phase noise versus offset frequency for the oscillator with MWCM. As shown in Figure 20, the best value of phase noise of −159.9 dBc/Hz at an offset frequency of 100 kHz is the case when m = 2 and C a = 3 pF. Figure 21 shows the dependence of phase noise versus capacitance C b for the oscillator with multiple-output Wilson CM. We can see from Figure 21 that oscillator phase noise significantly depends on the value of C b . Indeed, when capacitance C b varies from 3 to 300 nF, phase noise decreases from −125.5 to −159.9 dBc/Hz. We can explain such a decrease in phase noise by reducing noise spectral density at the drain of transistor T 0 where capacitor C b is connected.  Let us now consider the case when a load RL is connected through the capacitive divider to an oscillator output, as shown in Figure 22   Let us now consider the case when a load RL is connected through the capacitive divider to an oscillator output, as shown in Figure 22  Let us now consider the case when a load R L is connected through the capacitive divider to an oscillator output, as shown in Figure 22. Assume that R L = 50 Ω and C CD1 = C CD2 = 0.5 pF for the oscillators with MIWCM (m = 0, 1, 2) and MWCM (m = 0). For the oscillators with MCCM (m = 0, 1, 2) and MWCM (m = 1, 2), we selected C CD1 = C CD2 = 0.25 pF.
Appl. Sci. 2021, 11, x FOR PEER REVIEW 20 of 33 Figure 22. A capacitive divider with load resistance RL at the oscillator output.
Using FOM (22), we compare oscillators shown in Figures 6-8 when RL = 50 Ω. Table  9 shows the results of the oscillators' simulation. As shown in Table 9, the best FOM values correspond to the same m sequence (0, 2, 1) as when RL = ∞ for oscillators with MCCM, Figure 22. A capacitive divider with load resistance R L at the oscillator output.
Using FOM (22), we compare oscillators shown in Figures 6-8 when R L = 50 Ω. Table 9 shows the results of the oscillators' simulation. As shown in Table 9, the best FOM values correspond to the same m sequence (0, 2, 1) as when R L = ∞ for oscillators with MCCM, MWCM, and MIWCM.  Table 10 shows the performance comparison of oscillators with MCCM, MWCM, and MIWCM for R L = ∞ and R L = 50 Ω.  As we can see in Table 10, the performance of each oscillator reduces when a 50 Ω load is connected to its output. The oscillator's performance with MICCM decreases to the greatest extent, and the oscillator's performance with MIWCM drops to the least. The absolute FOM value decreases by 4.9% and 0.8% in relative units, respectively, i.e., not critical.

Simulation of VCO Characteristics
Let us now simulate the characteristics for VCOs presented in Figures 9-11 by using the same transistors, resistor values of R c and R d , inductor type of L, and power supply voltage as in Section 7.3 when R L = ∞. We select varactors SMV1104-33. The tuning voltage V d is varied from 2 to 12 V for each VCO. Capacitance C b = 50 nF for VCOs with MCCM and C b = 300 nF for VCOs with MWCM and MIWCM.
As in Section 7.3, we select the value of capacitance C a from the condition of minimizing the phase noise of each VCO. Figures 23 and 24 show the dependence of phase noise versus offset frequency for VCOs with MIWCM at V d = 2 V and V d = 12 V. The best value of phase noise of −137.9 dBc/Hz at an offset frequency of 100 kHz and V d = 2 V has VCO with MIWCM when m = 2 (see Figure 23). The best value of phase noise of −152.5 dBc/Hz at an offset frequency of 100 kHz and V d = 12 V also has VCO with MIWCM but when m = 1 (see Figure 24). the same transistors, resistor values of Rc and Rd, inductor type of L, and power supply voltage as in Section 7.3 when RL = ∞. We select varactors SMV1104-33. The tuning voltag Vd is varied from 2 to 12 V for each VCO. Capacitance Cb = 50 nF for VCOs with MCCM and Cb = 300 nF for VCOs with MWCM and MIWCM.
As in Section 7.3, we select the value of capacitance Ca from the condition of minimiz ing the phase noise of each VCO. Figures 23 and 24 show the dependence of phase noise versus offset frequency fo VCOs with MIWCM at Vd = 2 V and Vd = 12 V. The best value of phase noise of −137. dBc/Hz at an offset frequency of 100 kHz and Vd = 2 V has VCO with MIWCM when m 2 (see Figure 23). The best value of phase noise of −152.5 dBc/Hz at an offset frequency o 100 kHz and Vd = 12 V also has VCO with MIWCM but when m = 1 (see Figure 24).
Interestingly, at Vd = 2 V, the phase noise improvement occurs in the sequence of m 0, 1, 2, i.e., the more mirrored currents, the lower the phase noise (see Figure 23). However at Vd = 12 V, the phase noise improvement occurs in m = 0, 2, 1, i.e., the highest phase nois occurs at m = 0, and the lowest at m = 1 (see Figure 24). The phase noise curve at m = occupies an intermediate position.   Table 11 shows the simulated characteristics of different VCOs when RL = ∞, where fmin and fmax are the minimum and maximum frequency of VCO operation. As shown in Table 11, the VCO with MCCM has the best performance when m = 0. The VCO with MWCM achieves the best performance when m = 2 and VCO with MIWCM-when m = 1 For each value of m in Table 11, VCO with MWCM and MIWCM have significantly lower (i.e., better) FOM than VCO with MCCM. The broadest tuning frequency range, Δf = 370 Interestingly, at V d = 2 V, the phase noise improvement occurs in the sequence of m = 0, 1, 2, i.e., the more mirrored currents, the lower the phase noise (see Figure 23). However, at V d = 12 V, the phase noise improvement occurs in m = 0, 2, 1, i.e., the highest phase noise occurs at m = 0, and the lowest at m = 1 (see Figure 24). The phase noise curve at m = 2 occupies an intermediate position. Table 11 shows the simulated characteristics of different VCOs when R L = ∞, where f min and f max are the minimum and maximum frequency of VCO operation. As shown in Table 11, the VCO with MCCM has the best performance when m = 0. The VCO with MWCM achieves the best performance when m = 2 and VCO with MIWCM-when m = 1. For each value of m in Table 11, VCO with MWCM and MIWCM have significantly lower (i.e., better) FOM than VCO with MCCM. The broadest tuning frequency range, ∆f = 370 MHz, has VCO with MCCM when m = 0. The lowest power consumption, P dis = 18.8 mW, also has VCO with MCCM when m = 0. Table 11. Simulated characteristics of different NDR VCOs when R L = ∞. We can explain such a decrease in phase noise by reducing noise spectral density at the drain of transistor T 0 . Table 12 shows the simulated characteristics of different VCOs when a 50 Ω load through a capacitive divider (see Figure 22) is connected to the output of VCOs shown in Figures 9-11.

As shown in
As in the case of R L = ∞ (see Table 11), for each value of m in Table 12, VCOs with MWCM and MIWCM have significantly lower FOM than VCO with MCCM. Figures 27 and 28 show the dependence of phase noise versus offset frequency for VCOs with MIWCM at V d = 2 V and V d = 12 V when R L = 50 Ω. The best value of phase noise of −139.0 dBc/Hz at an offset frequency of 100 kHz and V d = 2 V has VCO when m = 2 (see Figure 27). We select CCD1 = CCD2 = 0.5 pF for the VCOs with MWCM (m = 0, 1, 2), and MIWCM (m = 1, 2), and CCD1 = CCD2 = 0.25 pF for the VCOs with MCCM (m = 0, 1, 2) and MIWCM (m = 0).
As shown in Table 12, the VCO with MCCM has the best performance when m = 0 and Ca = 30 pF. The VCO with MWCM achieves the best performance when m = 1 and C = 20 pF, and the VCO with MIWCM-when m = 2 and Ca = 9 pF.    As shown in Table 12, the VCO with MCCM has the best performance when m = 0 and Ca = 30 pF. The VCO with MWCM achieves the best performance when m = 1 and C = 20 pF, and the VCO with MIWCM-when m = 2 and Ca = 9 pF.    As in the case of RL = ∞ (see Table 11), for each value of m in Table 12, VCOs wit MWCM and MIWCM have significantly lower FOM than VCO with MCCM. Figures 27 and 28 show the dependence of phase noise versus offset frequency fo VCOs with MIWCM at Vd = 2 V and Vd = 12 V when RL = 50 Ω. The best value of phas noise of −139.0 dBc/Hz at an offset frequency of 100 kHz and Vd = 2 V has VCO when m 2 (see Figure 27).  The best value of phase noise of −138.4 dBc/Hz at an offset frequency of 100 kHz and Vd = 12 V corresponds to m = 0 (see Figure 28). Table 13 compares the performance of VCOs with MCCM, MWCM, and MIWCM fo RL = ∞ and RL = 50 Ω.  As shown in Table 13, the highest (i.e., the worst) in-band value of the FOM insignif icantly increases when connecting a 50 Ω load to the VCO output. Indeed, the absolute FOM value decreases by 0.5 dBc/Hz for VCO with MICCM, by 1.6 dBc/Hz for VCO with MWCM, and by 1.1 dBc/Hz for VCO with MIWCM. However, the lowest (i.e., the best in-band FOM value changes more substantially, namely by 41.1 dBc/Hz for VCO with MCCM, by 4.3 dBc/Hz for VCO with MWCM, and by 16.9 dBc/Hz for VCO with MIWCM Since, when comparing the VCOs, the worst in-band FOM value is considered, we can conclude that this value changes insignificantly (maximum 0.7 %) when connecting a 50 Ω load to the VCO output.
Tables 12 and 13 show that the best VCO when RL = 50 is the VCO with MIWCM (m = 2) Table 14 compares the performance characteristics of the recently published and de veloped in this article VCOs and oscillators. We can draw the following conclusions from Table 14. The oscillator with MWCM (m = 2, RL = 50 Ω) designed in this study has the lowest phase noise (−154.6 dBc/Hz at 0.1 MHz offset) and the best FOM (−221.6 dBc/Hz among all oscillators. The latter is an indisputable advantage of the developed oscillato since CMOS oscillators have a much lower power consumption and usually have a signif icant advantage over GaN and GaAs oscillators in terms of the FOM value. The best value of phase noise of −138.4 dBc/Hz at an offset frequency of 100 kHz and V d = 12 V corresponds to m = 0 (see Figure 28). Table 13 compares the performance of VCOs with MCCM, MWCM, and MIWCM for R L = ∞ and R L = 50 Ω.  As shown in Table 13, the highest (i.e., the worst) in-band value of the FOM insignificantly increases when connecting a 50 Ω load to the VCO output. Indeed, the absolute FOM value decreases by 0.5 dBc/Hz for VCO with MICCM, by 1.6 dBc/Hz for VCO with MWCM, and by 1.1 dBc/Hz for VCO with MIWCM. However, the lowest (i.e., the best) in-band FOM value changes more substantially, namely by 41.1 dBc/Hz for VCO with MCCM, by 4.3 dBc/Hz for VCO with MWCM, and by 16.9 dBc/Hz for VCO with MIWCM. Since, when comparing the VCOs, the worst in-band FOM value is considered, we can conclude that this value changes insignificantly (maximum 0.7 %) when connecting a 50 Ω load to the VCO output. Tables 12 and 13 show that the best VCO when R L = 50 is the VCO with MIWCM (m = 2). Table 14 compares the performance characteristics of the recently published and developed in this article VCOs and oscillators. We can draw the following conclusions from Table 14. The oscillator with MWCM (m = 2, R L = 50 Ω) designed in this study has the lowest phase noise (−154.6 dBc/Hz at 0.1 MHz offset) and the best FOM (−221.6 dBc/Hz) among all oscillators. The latter is an indisputable advantage of the developed oscillator since CMOS oscillators have a much lower power consumption and usually have a significant advantage over GaN and GaAs oscillators in terms of the FOM value. The designed VCO with MIWCM (m = 2, R L = 50 Ω) also has very low phase noise (−139.0, −137.0 dBc/Hz at 0.1 MHz offset) and is one of the best FOM (−205.1, −203.9 dBc/Hz at 0.1 MHz offset) in the tuning range. Thus, we can successfully use the proposed two-terminal circuits with NDR for constructing highly efficient microwave oscillators and VCOs.

Experimental Results
We tested the oscillator circuit with MIWCM (see Figure 8) on a breadboard and printed circuit board (PCB) assembly. Table 15 shows part numbers and nominal values of the breadboard oscillator elements. In the oscillator circuit with MIWCM of Figure 8, the value of m is equal to 1. At the operating point, V 1,2 = 6 V and I 1 = 2.7 mA. Figure 29 shows the measured oscillator output spectrum at the fundamental frequency of 18.7 MHz with an output power of −14.8 dBm. We used a spectrum analyzer USB-SA44B (Battle Ground, WA, USA) and an Auburn P-20A RF probe (Auburn, WA, USA) with a 10:1 voltage ratio.      Figure 30 shows the PCB assembly of the oscillator with MIWCM (m =0). Table 16 indicates part numbers and nominal values of components assembled on PCB. We also used the USB-SA44B spectrum analyzer with Auburn P-20A RF probe to measure the oscillator output spectrum (see Figure 31) at V 1,2 = 9 V and RBW = 100 kHz. As shown in Figure 31, the oscillation frequency is 944.4 MHz, and the power level of the output signal is −40.2 dBm. In estimating the actual power level, we should consider that the attenuation provided by the P-20A RF probe is 20 dB, and an insertion loss of the buffer amplifier is 2.2 dB.

Conclusions
In this article, we have demonstrated new two-terminal NDR circuits based on bination of a field-effect transistor and multiple-output cascode, Wilson, and im Wilson BJT current mirrors. The proposed circuits allow controlling the slope of t rent-voltage characteristics in the NDR region by changing the number of mirror rents, thus setting the peak-to-valley current ratio to any desired value. We ha ducted modeling total current in the NDR region when the FET is a JFET and M HEMT, or PHEMT; the obtained current equations calculate the negative resistanc operating point. We considered possible applications of the proposed two-termin circuits as oscillators and VCOs. We found that the NDR circuit with multiple-out proved Wilson current mirror has the smallest absolute value of negative res which means that the NDR oscillator based on this circuit has the best conditions f excitation. We analyzed the effect of loading on the performance characteristics of cillators and VCOs. We found that a 50-ohm load reduces, in comparison to infini the performance of the oscillators and VCOs by a maximum of 4.9% and 0.7 %, tively. By simulation, we show that the microwave oscillator based on multiple improved Wilson current mirror has the lowest phase noise (−154.6 dBc/Hz at off kHz) and the best figure of merit (−221.6 dBc/Hz) compared to other considered

Conclusions
In this article, we have demonstrated new two-terminal NDR circuits based on a combination of a field-effect transistor and multiple-output cascode, Wilson, and improved Wilson BJT current mirrors. The proposed circuits allow controlling the slope of the currentvoltage characteristics in the NDR region by changing the number of mirrored currents, thus setting the peak-to-valley current ratio to any desired value. We have conducted modeling total current in the NDR region when the FET is a JFET and MESFET, HEMT, or PHEMT; the obtained current equations calculate the negative resistance at the operating point. We considered possible applications of the proposed two-terminal NDR circuits as oscillators and VCOs. We found that the NDR circuit with multiple-output improved Wilson current mirror has the smallest absolute value of negative resistance, which means that the NDR oscillator based on this circuit has the best conditions for self-excitation. We analyzed the effect of loading on the performance characteristics of the oscillators and VCOs. We found that a 50-ohm load reduces, in comparison to infinite load, the performance of the oscillators and VCOs by a maximum of 4.9% and 0.7 %, respectively. By simulation, we show that the microwave oscillator based on multiple-output improved Wilson current mirror has the lowest phase noise (−154.6 dBc/Hz at offset 100 kHz) and the best figure of merit (−221.6 dBc/Hz) compared to other considered oscillators. We also show that the VCO with multiple-output improved Wilson current mirror has the best FOM in the tuning range (−205.1, −203.9 dBc/Hz). Comparison of the developed oscillators and those previously published showed that the oscillators based on the proposed two-terminal NDR circuits are superior to the well-known GaN and GaAs HEMT oscillators by 10-20 dB with respect to the commonly used figure of merit. It is also interesting to note that the proposed oscillator circuits are higher in effectiveness than even CMOS oscillators, despite the much lower power consumption of the latter. This advantage is due to the low level of phase noise in the designed oscillators.
Our future work will focus on developing and studying two-terminal NDR circuits, in which the multiple-output current mirrors consist of MOS transistors. Acknowledgments: The authors express thanks to engineer E. Meshcheryakov for technical support.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations exist in the manuscript: Voltage between terminals 1 and 2 in NDR circuits V A Early voltage of a BJT in the current mirror V CE1 , V CE2 Collector-emitter voltages of transistors T 1 and T 2 in the multiple-output Wilson current mirror V D Drain voltage of transistor T 0 V DS Drain-source voltage of transistor T 0 V EB Emitter-base voltage V EB3 Emitter-base voltage of transistor T 3 in the multiple-output Wilson current mirror V GS Gate-source voltage of transistor T 0 V P Pinch-off voltage of JFET T 0 V TH Threshold voltage of transistor T 0 (MESFET, HEMT, or PHEMT) V X Voltage between terminals 1 and 2 at point X V Y Voltage between terminals 1 and 2 at point Y V Z Voltage between terminals 1 and 2 at point Z ∆I Y % Relative accuracy of calculating current I Y ∆I D % Relative accuracy of calculating current I D