Formal Chaos Existing Conditions on a Transmission Line Circuit with a Piecewise Linear Resistor

: By using one-dimensional (1-D) map methods, some lossless transmission line circuits with a short at one side terminal have been actively studied. Bifurcation results or chaotic states in the circuits have been reported. On the other hand, many weak or strong deﬁnitions such that a 1-D map is mathematically chaotic are still being studied. In such deﬁnitions, the deﬁnition of formal chaos is well known as being the most traditional and most deﬁnite. However, formal chaos existences have not been rigorously proven in such circuits. In this paper, a general lossless transmission circuit is considered ﬁrst with a dc bias voltage source in series with a load resistor at one side terminal and with a three-segment piecewise linear resistor at another side terminal. Secondly, the method for deriving a 1-D map describing the behavior of the circuit is summarized. Thirdly, to provide a basis of chaotic application for the 1-D map, the mathematical deﬁnition of formal chaos and the sufﬁcient conditions of the existence of formal chaos are discussed. Furthermore, by using Maple, formal chaos existences and bifurcation behavior of 1-D maps are presented. By using the Lyapunov exponent, the observability of formal chaos in such bifurcation processes is outlined. Finally, the principal results and the future works are summarized.


Introduction
Transmission line circuits, switched capacitor circuits, neuron model circuits, and constrained circuits are notable as the nonlinear circuits of which behavior may be described by one-dimensional (1-D) maps [1][2][3][4][5][6][7][8][9][10][11]. Furthermore, in [12], by using real imperfect integrated devices induced by unavoidable manufacturing imperfections that plausibly have so called hidden dynamics with parasitic effects and nonidealities, the possibility of designing imperfect electronic circuits generating megahertz chaotic oscillations, without the use of additional capacitors or inductors, has been explored and discussed.
By using one-dimensional (1-D) map methods, some lossless transmission line circuits with a short at one side terminal [5][6][7][8][9][10][11] (or, with a dc bias voltage source in series with a load resistor at one side terminal [7]) have been actively studied. On the other hand, many weak or strong definitions such that a 1-D map is mathematically chaotic are still being studied [13][14][15][16][17][18]. In this paper, we use the following definition that is well known as most traditional and most definite since Moser [19]. Definition 1. A 1-D discrete dynamical system or 1-D map ϕ on M is said to be chaotic if there exists an invariant subset Λ ⊂ M on which some iterates of ϕ is topologically conjugate to the shift dynamics (σ, Σ m ) with m symbols.
The shift dynamics (σ, Σ m ) with m symbols has the following properties [13,[15][16][17]: (1) There are countably many periodic points with different periods in Σ m . (2) The set of all periodic points in dense in Σ m . (3) σ is topologically transitive. Namely, there exists a point c ∈ Σ m where its orbit is dense in Σ m . (4) σ is topologically expansive. (5) Σ m is homeomorphic to a Cantor set. (6) The topological entropy of σ is h(σ) = log e m.
For a 1-D discrete dynamical system ϕ, it is well known that "ϕ has a homoclinic point" implies Definition 1, and they are often equivalent [15,20,21]. Definition 1 is not based on the theoretical measure but is based on the topological viewpoint, and it is called formal chaos or topological chaos, which may be not observable generally [13]. Thus, we call the chaos in Definition 1 formal chaos.
Binary sequences based on observable chaotic behavior produced by 1-D maps coming from the nonlinear circuits are reported and well known to have good statistical properties useful for applications relative to several digital communication systems [4,13]. However, the sufficient conditions for the existence of observable chaos are so strong that most 1-D maps coming from general nonlinear circuits cannot be rigorously proved to possess observable chaos. Indeed, for general 1-D maps such that the absolute slops of them are either greater or less than unity, it is very difficult to rigourously prove the existence of observable chaos, except for 1-D maps such as the logistic map family or 1-D piecewise linear maps such that all their absolute slopes of are greater than unity.
Once the existence of formal chaos is guaranteed, the degree of the observability of the chaos can be checked by the existence of maximal positive Lyapunov exponent [14] through computer simulations from the viewpoint of engineering. Hence, we pay attention to the sufficient condition that formal chaos in Definition 1 exists in a 1-D map.
In [5,6], a lossless transmission line circuit with a short at one side terminal and with a three-segment piecewise linear (3SPWL) resistor (so called Nagumo's 3SPWL resistor) at another side terminal is considered. The v − i characteristic of the (3SPWL) resistor is not only in point symmetry at the origin but also in all four quadrants of a (v, i) coordinate system. The method for deriving a 1-D map describing the dynamics of the circuit is discussed at the base of the incident and reflected waves. Some analytical results are obtained by using the 1-D map. In [8][9][10], for a lossless transmission line circuit with a short at one side terminal and with a three-segment piecewise linear resistor function at another side terminal, the conditions are provided for the existence of the explicit function form of the incident and reflected wave transformed from the three-segment piecewise linear resistor function, the existence of the 1-D map, and the existence of the invariant interval of the 1-D map. Furthermore, in [8][9][10][11], by using a 1-D map, analytical bifurcation results or chaotic states (except for formal chaos) are reported in terms of numerical simulation.
In this paper, from the above background, in Section 2, we consider a lossless transmission circuit with a dc bias voltage source in series with a load resistor at one side terminal and with a three-segment piecewise linear resistor at another side terminal. In Section 3, we summarize the method for deriving a 1-D map describing the behavior of the circuit. In Section 4, in order to provide a basis of chaotic application for the 1-D map (or the transmission circuit), we discuss the mathematical definition of formal chaos and the sufficient conditions of the existence of formal chaos for generating 1-D maps. In Section 5, using Maple [23], we present an example of formal chaos existence and several examples of bifurcation behavior of 1-D maps. Using the degree of observability of chaotic states in terms of Lyapunov exponent, we discuss the observability of formal chaos in such bifurcation processes. In the Conclusion section, we summarize the principal results and the future works. In particular, we mention the possibility of designing imperfect transmission lines with parasitic effects and nonidealities inside real integrated devices generating high frequency ranges and chaotic oscillations without the use of additional capacitors or inductors.

Lossless Transmission Circuit Equations with Terminal Conditions
Incorporating the works in [5][6][7][8][9][10], we consider a lossless transmission circuit with a dc bias voltage source in series with a load resistor at one side terminal and with a three-segment piecewise linear resistor at another side terminal such as (N) Nagumo's 3SPWL resistor in Figures 1 and 2 or (T) the present authors' Modeled Tunnel Diode (TD) 3SPWL resistor in Figures 3 and 4 in Figure 5. The circuit in Figure 5 can be represented by the circuit in Figure 6 with 3SPWL resistor (N) or (T) together with the side terminal conditions as follows. At one side terminal A of the circuit, we have the following: (i) a dc bias voltage source in series with 3SPWL resistor (N) or (T): E B0 = 0; and (ii) 3SPWL resistor (N) or (T): E B0 = 0. At another side terminal B of the circuit, we have the following: (3) a load resistor: E B = 0, R L = 0; (4) a dc bias voltage source: E B = 0, R L = 0; or (5) a dc bias voltage source in series with a load resistor: E B = 0, R L = 0. We focus on considering a lossless transmission line circuit with 3SPWL resistor (N) or (T), together with the above side terminal conditions in Figure 6.

Three-Segment Piecewise Linear Resistor
The three-segment Piecewise Linear (3SPWL) resistor i NR = F k (v NR ), (k = N, T) in Figure 5 is realized by the op amp based circuit (N) Nagumo's 3SPWL resistor in Figure 1 and  Figure 3 denotes the forward voltage drop of the ideal switching diode. In Figure 2 or Figure 4, the v-i characteristic of F k is always of the N type such that g 1 , g 2 , and g 3 are positive, negative, and positive slopes, respectively.
(N) Nagumo's 3SPWL Resistor F N : The slopes g i , i = 1, · · · , 3 and break points −E − p and E + p in Figure 2 are given as follows: on the condition that η > −1, is also freely set up by V + cc because, for any op amps, The slopes g i , i = 1, · · · , 3 and break points E d and E p in Figure 4 are given as follows: is also freely set up by V + cc because, for any op amps, E + s is generally in proportion to V + cc .

Transmission Line Circuit Equation
The relation of the voltage v and the current i in the line in Figure 6 becomes the following: ∂v ∂τ where Z = L C is the characteristic impedance of the line; s = 1 √ LC is the propagation velocity of waves in the line; T = 2l s , v = v C /V max , i = i L /I max , x = x l /2l, τ = t/T, L are the series of inductance per unit length of the line; C is the parallel capacitance per unit length of the line; l is line length; v C is the voltage in the line; i L is the current in the line; x l is the coordinate in the line; v is the non-dimensional voltage in the line; i is the non-dimensional current in the line; x is the non-dimensional coordinate in the line; and τ is non-dimensional time. Accordingly, by eliminating i (or v), we have the following.
The following Equations (3) and (4) provide the boundary conditions of Figure 6. Equations (3) and (4) also provide the boundary conditions of Figure 5 as follows. At one side terminal, we have the following: (i) a dc bias voltage source in series with 3SPWL resistor (N) or (T): ξ = 0 and (ii) 3SPWL resistor (N) or (T): ξ = 0. At another side terminal, we have the following: (1) short: E = 0, R = 0; (2) open: E = 0, R → ∞; (3) a load resistor: E = 0, R = 0; (4) a dc bias voltage source: E = 0, R = 0 ; or (5) a dc bias voltage source in series with a load resistor: i(τ, Here, Here, , and E B are the dc bias voltage sources; R L is the load resistor; and f k (v, ζ, η, ξ) is the non-dimensional current of 3SPWL resistor, (k = N, T).

Derivation of 1-D Map
Here, we discuss how to derive the 1-D map or the difference equation of which the dynamics completely describes the dynamics of Equations (2)-(6).
The 1-D wave equation of Equation (2) has the d'Alembert's solution, which is described as the following.
Equation (7) can be solved with regard to the scattering variables, that is,ψ and φ. Then, we have the following description.
The following Equations (9) and (10) provide the boundary conditions of Figure 6. Equations (9) and (10) also provide the boundary conditions of Figure 5 as follows.
which also holds when the following is the case: or we have the following: where Dχ ki is the slope of χ ki (ψ(τ − 1)), 1 ≤ i ≤ 3, and R is the set of real numbers.
Proof in Appendix A.
The other case is where R → ∞: Proof in Appendix A.
Proof in Appendix A.

Global Behavior of 1-D Map
Here, we provide Theorem 2 to guarantee that for any initial point, every orbit by the iteration of the 1-D map of ψ(τ) = h(ψ(τ − 1)) ultimately penetrates an invariant interval set.
, then the following is the case.
There exists an invariant interval

3.
For any ψ 0 ∈ (−∞, ∞), there exists jth iterate of h k such that h j k (ψ 0 ) ∈ I kψ , j(> 0) ∈ Z, where h j k denotes the jth iterate of h k , i.e., h j k is the j-fold composition of h k with itself. Z is the set of non negative integers.
Proof in Appendix A.

Formal Chaos Existing Conditions of 1-D Maps
As mentioned before, binary sequences based on observable chaotic behavior produced by 1-D maps are well known to have good statistical properties useful for applications relative to several digital communication systems [4,13]. However, the sufficient conditions for the existence of observable chaos are so strong that most 1-D maps cannot be rigorously proved to possess observable chaos. Furthermore, once the existence of formal chaos is guaranteed, the degree of the observability of the chaos can be checked by the existence of maximal positive Lyapunov exponent [14] through computer simulations from the viewpoint of engineering. Hence, we focus on the sufficient condition that formal chaos in Definition 1 exists in a 1-D map.

Formal Chaos Existing Conditions of a General 1-D Map
In this subsection, in order to verify formal chaos existence for 1-D map easily, we provide Theorem 3 to guarantee the formal chaos existence in Definition 1 in the case of m = 2. Although a similar 1-D map to the map in Theorem 3 appears in Devaney or Aoki's mathematical proof process for "ϕ has a homoclinic point" implying Definition 1 in [15,21], the existence of the similar 1-D map has not been considered as an easy-to-use sufficient condition implying Definition 1.
Therefore, the authors propose to adopt the existence of the similar 1-D map as the sufficient condition implying Definition 1 and to summarize this condition as Theorem 3. This theorem can be regarded as 1-D map version of Moser's theorems [14,19] for two dimensional maps. Theorem 3. Let I be a closed interval of real numbers. Let f be a continuous piecewise differentiable mapping from I to itself and D f be a derivative of f . A1 There exist I 0 and I 1 disjoint closed subintervals in I such that I 0 ∪ I 1 ⊂ f (I 0 ) and I 0 ∪ I 1 ⊂ f (I 1 ).
A2 |D f (x)| > 1 holds for any x in I 0 ∪ I 1 . If f satisfies A1 and A2, then the invariant set Λ = ∩ 0≤n≤∞ ( f ) n (I 0 ∪ I 1 ) ⊂ I exists, and the 1-D map f on Λ is topologically conjugate to the shift dynamics (σ, Σ 2 ) with 2 symbols. The one-dimensional map f on Λ is mathematically chaotic.
Proof in Appendix A.

Formal Chaos Existing Conditions of a 1-D Map Family
As mentioned precisely in the later subsections, for a lossless transmission circuit with a dc bias voltage source in series with a load resistor at one side terminal and with a three-segment piecewise linear resistor at another side terminal, the existence of a threesegment piecewise linear 1-D map describing the dynamics of the circuit, the existence of the invariant interval of the 1-D map, and the coordinate transformation from the invariant interval to the normalized interval I = [0, 1] are provided.
Therefore, in this subsection, we pay our attention to the normalized 1-D map on the normalized interval I after applying the coordinate transformation to the three-segment piecewise linear 1-D map. We discuss the formal chaos verification of the normalized threesegment piecewise linear 1-D map H on I such that the absolute slopes of the map are either greater or less than unity. In general such map H satisfies Theorem 3 under very narrow range-limited circuit parameters. Instead of H, focusing on H 2 of which the circuit parameters are expected to have the broader range implying that H 2 satisfies Theorem 3, we provide Theorem 5 to guarantee that the dynamics of H 2 on I is topologically conjugate with respect to the shift dynamics (σ, Σ 2 ) with two symbols. Since one tends to consider it as routine work for providing the sufficient inequality conditions of Theorem 5, once again we note that,in order to obtain the inequality conditions, one needs an elaborate symbolical manipulation technique.
We consider the normalized 1-D map as follows (see in Figure 7): where I = [0, 1] ⊂ R, x n , x n+1 ∈ I, and R is the set of real numbers.
and 0 < k 1 , k 2 , n 1 , n 2 < 1, then the following is the case: where DH i H j is the slope of H i (H j (x n )), 1 ≤ i, j ≤ 3.
Proof in Appendix A.
Proof in Appendix A.

Formal Chaos Existing Conditions of 1-D Maps of Lossless Transmission Circuits
Now, we discuss the method for verifying formal chaos in the dynamics of the 1-D map of ψ(τ) = h k (ψ(τ − 1)), (k = N, T) rigorously. In the following, we assume that the conditions of Theorem 2 are satisfied. Then, ψ(τ) = h k (ψ(τ − 1)) has a unique unstable fixed point ψ * k ∈ I ψk and an invariant interval I ψk such that h(I ψk ) ⊂ I ψk , and for any ψ 0 ∈ (−∞, ∞), there exists jth iterate of h k such that h j k (ψ 0 ) ∈ I ψk , j(> 0) ∈ Z. Thus, eventually all we have to consider are the dynamics of ψ(τ) = h k (ψ(τ − 1)) on the invariant interval of I ψk . To this end, we consider the following coordinate transformation and maps. Using Equations (26) and (27), we provide Theorem 4. By further using Theorem 3, we provide Theorem 5 in order to guarantee that the dynamics of h 2 k on an invariant subset ⊂ I ψk is topologically conjugate to the shift dynamics (σ, Σ 2 ) with two symbols.

Formal Chaos Existence and Bifurcation Behavior of 1-D Maps by Using Maple
In this section, we pay our attention to the 1-D maps derived from the transmission line circuits with TD 3SPWL Resistor F T at another side terminal because the characteristics of TD 3SPWL Resistor F T is more general than the characteristics of Nagumo's 3SPWL resistor F N . Then, we present an example of formal chaos existence and several examples of bifurcation behavior of 1-D maps. Using the degree of observability of chaotic states in terms of Lyapunov exponent, we show the observability of formal chaos in such bifurcation processes.

An Example of Formal Chaos Existence
In this subsection, using Maple, we present an example of the existence of formal chaos. Under the condition such that V max = 10 Invariant set Λ = ∩ 0≤n≤∞ (H 2 ) n (I 0 ∪ I 1 ) ⊂ I exists, and H 2 on Λ is topologically conjugate to the shift dynamics (σ, Σ 2 ) with two symbols. H 2 on Λ is mathematically chaotic.
In the following, we show f (v, ζ, η), H(Ψ), and H 2 (Ψ) and illustrate the v-i characteristic of f (v, ζ, η) and the graphs of H(Ψ) and H 2 (Ψ) in Figures 8 and 9, respectively. Further graphical iterative paths of H 2 (Ψ) and voltage map by Corollary 2 and iterative time series data of the voltage map at iterative time n are illustrated in Figures 10-12, respectively. The conditions of these graphical iterations are as follows: the initial point of these iterations is x 0 = 52,828 227,953 ⊂ I 0 , and with the use of Maple 8, the graphical iterations in these figures are illustrated by 2000 iterations such that the iterations from first until 1000 are not used in the total 3000 iterations. In addition, the real parameters of the conditions above are reasonable because E d = 3 , and R L = 525 4 [Ω]. The real transmission line circuit with three-segment piecewise linear resistor can be implemented.

Several Examples of Bifurcation Behavior of 1-D Maps
In this subsection, by using Maple 8, we present various bifurcation behavior (including the found formal chaos) of 1-D voltage maps of Equation (18) with maximal Lyapunov exponent. The degree of observability of chaotic states is given by Lyapunov exponent µ(v 0 ) of Equation (28) for any initial point v 0 [14].
Here, codimension one bifurcation diagrams with one of the bifurcation parameters: ζ, η, ξ, or E, and representative iterative paths are summarized as follows. With one of the following bifurcation parameters from (1) bifurcation parameter ζ until (4) bifurcation parameter E, the codimension one bifurcation diagrams including the found formal chaos togethar with the Lyapunov exponents, are illustrated in Figures 13-16  Representative iterative paths in bifurcation diagrams of Figures 13-16 are illustrated in Figures 17-20, respectively. Graphical iterations in these figures are illustrated by 60 iterations such that the iterations from first until 40 are not used in the total 100 iterations. Since the voltage maps are composite maps consisting of incident waves or reflected waves, etc., it takes too much computation time to obtain bifurcation diagrams with Lyapunov exponents in Figures 13-16. Therefore, the number of iterations for the voltage maps is intentionally reduced.

1.
We have described an implicit 1-D map of the incident and reflected waves that is derived from a lossless transmission line circuit with a dc bias voltage source in series with a load resistor at one side terminal and with a three-segment piecewise linear resistor at another side terminal.

3.
We have provided Theorem 3 such as an easy-to-use sufficient condition implying formal chaos existence in Definition 1.

4.
We have provided Theorem 2 to guarantee that for any initial point, every orbit by the iteration of the 1-D map ultimately penetrates in an invariant interval.

5.
We have provided Theorems 2 and 5 to guarantee that the dynamics of the second iterate map of the 1-D map on an invariant subset of the invariant interval has formal chaos.
We have obtained the codimension of one type of four various bifurcation diagrams including the found formal chaos, with one of the bifurcation parameters: ζ, η, ξ, or E.
From each bifurcation diagram with the Lyapunov exponent, the obsavability of the found formal chaos is considered to be rather high. 8.
As with the case of [12] such that the hidden dynamics of the circuit based on the integrated device has been unveiled on the basis of an analogy with the well-known Colpitts oscillator with the chaotic oscillations, we think that the hidden dynamics of imperfect transmission lines with parasitic effects and nonidealities inside real integrated devices can be unveiled on the basis of an analogy with the transmission line circuit of Equations (2)-(6) with formal chaos and that the parameters of the hidden dynamics can also be estimated by synchronizing a transmission line circuit with the chaotic oscillations acquired from the experimental circuit. 9.
We will report bifurcation processes with each of bifurcation parameters, Z or R, because nonlinear phenomena such as intermittency of chaos or blue sky bifurcation are observed in simulations. 10. We will establish a method to find the bifurcation parameter ranges such that formal chaos exists for applications relative to several digital communication systems. Institutional Review Board Statement: Not Applicable.

Informed Consent Statement: Not Applicable.
Data Availability Statement: Data is contained within the article.

Conflicts of Interest:
The authors declare no conflict of interest.

Appendix A. Proofs of Theorems and Corollaries
Proof of Theorem 1. Each of the proof for the case k = N, or T, is given as follows.

Proof of Theorem 2.
Under the conditions that Theorem 2 holds, the following is the case.
In a similar manner as the above, for all x such as . Therefore, for all x such as x > ψ T2 , the following is the case.
In the case of k = N: It is easy to check the following properties: (1) ψ N * > 0 holds because r − ζ > 0 and r − Rζ > 0. (2) 2r(r−Rζ) . Therefore, for all x such as x < ψ N1 , the following is the case.
In the similar way above, for all x such as Therefore, for all x such as x > ψ N2 , the following is the case.
Item 1 is proved.
Next, under the conditions that Theorem 2 holds, the following is the case.
In the case of k = T, it is easy to check the following properties.
The shift map simply "forgets" the first entry in a sequence, and shifts all other entries one place to the left. Clearly, σ is a two-to-one map of Σ 2 , as s 0 may be either 0 or 1. Moreover, in the metric defined above, σ is a continuous map.
Next to prove the item 2, it is sufficient that H 2 is considered as the map f in Theorem 3. Under the item 1 condition, H 2 is satisfied with the condition of Theorem 3. The item 2 is also proved. The proof is now complete.