Active Clamp Boost Converter with Blanking Time Tuning Considered

: An active clamp boost converter with blanking time auto-tuned is presented herein, and this is implemented by an additional auxiliary switch, an additional resonant inductor, and an additional active clamp capacitor as compared with the conventional boost converter. In this structure, both the main and auxiliary switches have zero voltage switching (ZVS) turn-on as well as the output diode has zero current switching (ZCS) turn-off, causing the overall efﬁciency of the converter to be upgraded. Moreover, as the active clamp circuit is adopted, the voltage spike on the main switch can be suppressed to some extent whereas, because of this structure, although the input inductor is designed in the continuous conduction mode (CCM), the output diode can operate with ZCS turn-off, leading to the resonant inductor operating in the discontinuous conduction mode (DCM), hence there is no reverse recovery current during the turn-off period of the output diode. Furthermore, unlike the existing soft switching circuits, the auto-tuning technique based on a given look-up table is added to adjust the cut-off time point of the auxiliary switch to reduce the current ﬂowing through the output diode, so that the overall efﬁciency is upgraded further. In this paper, basic operating principles, mathematic deductions, potential designs, and some experimental results are given. To sum up, the novelty of this paper is ZCS turn-off of the output diode, DCM operation of the resonant inductor, and auto-tuning of cut-off time point of the auxiliary switch. In addition, the efﬁciency of the proposed converter can be up to 96.9%.


Introduction
How to obtain a high-power density power supply is becoming more and more attractive in the world. By increasing the switching frequency, the size of magnetic devices and capacitors can be reduced so that high-power density requirements can be achieved. However, for the hard switching to be considered, the higher the switching frequency, the greater the switching loss and the more difficult the heat process. In addition, the switching loss under hard switching is proportional to the switching frequency. Consequently, the problem in high switching frequency is becoming more and more serious, thereby causing resonant and soft-switching converters to develop to reduce the switching loss.
The conventional resonant converter is based on the inductor connected in series with the main switch or the capacitor connected in parallel with the main switch so as to form a resonant loop. As the voltage on or current in the switch is dropped to zero, the switch is switched to achieve zero voltage switching (ZVS) turn-on of the switch or zero current switching (ZCS) turn-off of the switch. Basically, this method can reduce the crossover area of voltage and current of the switch, thereby decreasing the switching loss. However, large voltage and current spikes increase the voltage and current stresses of switches as well as increase the conduction losses. Furthermore, in order to render the output voltage controlled at a desired value, the switching frequency is varied because the resonant time is fixed, causing the design of the filter to be difficult.
As the conventional resonant converter has the demerits mentioned above, the softswitching converter is presented. The ZVS/ZCS pulse-width-modulation (PWM) converter [1][2][3] has put an auxiliary switch to the resonant loop of the resonant converter to make the resonant time point adjustable, thereby leading to fixed frequency control and making the design of the filter easy. However, the conduction loss is large because the resonant voltage on and current in the circuit elements are large. The operating principle of the ZVT/ZCT converter is that prior to turn-on of the main switch, the auxiliary switch is conducted, and hence the transient resonance occurs. As the voltage on or current in the main switch resonates to zero, the main switch is turned on to achieve ZVT turn-on or ZCT turn-off. As the auxiliary switch in the off-state, no resonance happens, leading to effectively reducing the voltage or current stress as well as conduction loss. In the literature [4,5], although the main switches have ZVS turn-on, the auxiliary switches still operate under hard switching. In the literature [6][7][8], although the main and auxiliary switches have ZVS turn-on, many components lead to an increase in cost. The operating behavior of the ZVZCT converter [9][10][11] is that the auxiliary switch has two transient resonances over one cycle so that the main switch has ZVT turn-on and ZCT turn-off. Indeed, this converter can reduce switching and conduction losses, and no additional voltage and current stresses on components. However, such a converter has complexity in control and a relatively large part count, leading to an increase in cost. Furthermore, as the ZVS or ZVT turn-on is relatively suitable for the metal-oxide-semiconductor field-effect transistor (MOSFET) switch [10], there are many studies on the MOSFET switch with ZVS or ZVT turn-on.
In addition, based on the above-mentioned, the ZVS pulse width modulation (PWM) converter, the ZVT converter, and the ZVZCT converter have individual disadvantages. Accordingly, the active clamp technique is developed, which is composed of an auxiliary switch in series with a capacitor. The work of [12] applies the synchronous rectifier to the ZVS active clamp forward converter to reduce the conduction loss. Another paper [13] applies the soft-switched synchronous rectifier to the ZVS active clamp forward converter to reduce the conduction loss as well as the switching loss. A further paper [14] applies the two-switch active clamp to a forward converter for high input voltage applications. The work of [15] applies the phase-shift control to the dual active clamp forward converter to reduce the conduction loss. The work of [16] utilizes the combination of active clamp and passive clamp to improve the light-load efficiency. A further paper [17] applies the secondary-side resonance scheme to the active clamp flyback converter to shape the primary-side current waveform, and hence to reduce the primary-side root-mean-square (RMS) value. Another paper [18] employs the primary-side digital control to regulate the active lamp flyback converter. The work of [19] applies the bidirectional concept to the ZVT active clamp boost converter. The work of [20] applies a coupled inductor to the ZVS active clamp boost converter. In the work of [21], the improved ZVS topology is applied to the active clamp buck converter. Although the converters shown in [19][20][21] have ZVS or ZVT turn-on of the main switches, the number of components used is large, leading to an increase in cost as well as difficulty in circuit analysis. In addition, in CCM, there is no ZCS turn-off of the output diode, leading to a problem in reverse recovery current created from the output diode, which operates during the turn-off period.
Based on the aforementioned, in this paper, one traditional boost converter along with one auxiliary circuit is presented. This auxiliary circuit is composed of one auxiliary switch, one resonant inductor, and one active clamp capacitor, so that the main switch and the auxiliary switch are turned on with ZVS and the output diode is turned off with ZCS, thereby resulting in upgrading the overall efficiency. Furthermore, the proposed active clamp has a function of voltage clamp, thereby leading to reducing the voltage spike on the main switch to some extent, whereas this structure can also cause the output diode to have ZCS turn-off, thereby removing the reverse recovery current. Above all, the proposed auto-tuning technique of the second blanking time is applied to the proposed circuit to upgrade the overall efficiency further. By the way, the potential application of the proposed soft switching converter is for high-power light-emitting diode (LED) lighting fed by the direct current (DC) voltage to improve the overall efficiency [22]. Figure 1 displays the proposed active clamp boost converter, which is constructed by one conventional boost converter combined with one auxiliary circuit. The former is built up by one input inductor L in and one main switch S 1 , along with one body diode D s1 , one parasitic capacitor C s1 , one output diode D o , and one output capacitor C o . The latter is constructed by one auxiliary switch S 2 along with one body diode D s2 , one parasitic capacitor C s2 , one resonant inductor L r , and one active clamp capacitor C c . The load is represented by one output resistor R. In addition, Figure 2 displays the equivalent circuit of the circuit shown in Figure 1, based on the assumption that the values of C o and C c are large enough to be regarded as ideal voltage sources, whereas the value of L in is large enough to be viewed as an ideal current source.   respectively; (v) v ds1 and i ds2 are the voltage on and current in S 2 , respectively; and (vi) all the elements are ideal except that switches have individual body diodes and parasitic capacitors. There are nine stages in the converter operating shown in Figure 3, where t on is the turn-on time of v gs1 , which is equal to DT s with a switching period of T s and a duty cycle of D, whereas t off is the turn-off time of v gs1 , which is equal to (1−D)T s .

Proposed Converter
As illustrated in Figures 3 and 4, S 1 is ON but S 2 is OFF. During this stage, L in is magnetized by V in . At the same time, v ds2 is clamped at V c . Once S 1 is cut off, the operation moves to stage 2.
As illustrated in Figures 3 and 5, S 1 is cut off and S 2 is still OFF. During this state, C s1 is abruptly charged to V c . As V c = v ds1 + v ds2 , C s2 is abruptly discharged to zero. At the same time, L r is magnetized and the energy at input terminal is transferred to the output terminal via D o . Once the energy stored in C s2 is entirely exhausted, the operation proceeds to stage 3.  According to Figure 5b, three stage equations can be obtained as By assuming that two switches are identical, C s1 = C s2 = C s . Moreover, the initial values of this stage are i Lr (t 1 ) = 0, v ds1 (t 1 ) = 0 and v ds2 (t 1 ) = V c . By taking the Laplace transform of Equation (1), the following equations can be attained to be By taking the inverse Laplace transform of Equation (2), the following equations can be attained to be where can be close to the following equations: cos According to Equation (6) and v ds (t 2 ) = 0, the corresponding time elapsed T 2 is As illustrated in Figures 3 and 6, S 1 and S 2 are both still OFF. In the previous stage, v ds1 (t 2 ) = V c and v ds2 (t 2 ) = 0. During this stage, i Lr is smaller than I in . Hence, D S2 is conducted, making v ds1 still clamped at V c . At the same time, the voltage across L r is V c − V o , causing i Lr to increase linearly. As soon as S 2 is conducted, the operation goes to stage 4. According to Figure 6b, one stage equation can be obtained as As the initial value of this stage is i Lr (t 2 ) = I Lr2 , solving Equation (8) yields Since i Lr (t 3 ) = I Lr3 , the corresponding time elapsed T 3 is Stage 4: (t 3 ≤ t ≤ t 4 ) As illustrated in Figures 3 and 7, S 1 is still OFF, but S 2 is conducted. In the previous stage, v ds2 (t 3 ) = 0. Therefore, S 2 is conducted at t 3 with ZVS. As I in is still smaller than i Lr , the voltage across L r is still V c − V o , causing L r to still be linearly magnetized. Once i Lr = I in , the operation proceeds to stage 5.
One stage equation can be obtained as shown in Figure 7b.
As the initial value of this stage is i Lr (t 3 ) = I Lr3 , solving Equation (11) yields Because i Lr (t 4 ) = I in , the corresponding time elapsed T 4 is Stage 5: (t 4 ≤ t ≤ t 5 ) As illustrated in Figures 3 and 8, S 1 is still OFF, but S 2 is still ON. Hence, the voltage across S 1 is clamped at V c . During this stage, i Lr is larger than I in , changing i ds2 to the positive direction. At the same time, the voltage across L r is still V c − V o , causing L r to still be linearly magnetized. As soon as S 2 is cut off, the operation goes to stage 6. One stage equation can be obtained as shown in Figure 8b.
As the initial value of this stage is i Lr (t 4 ) = I in , solving Equation (14) yields Because i Lr (t 5 ) = I Lr5 , the corresponding time elapsed T 5 is As illustrated in Figures 3 and 9, S 1 is still OFF and S 2 is cut off. During this stage, i Lr is still large than I in , hence C s2 is abruptly charged to V c and C s1 is abruptly discharged to zero. At the same time, L r begins to be demagnetized. The moment C s1 is discharged to zero, this stage comes to an end and the next stage begins. Three stage equations can be obtained as shown in Figure 9b.
By assuming two switches are identical, C s1 = C s2 = C s . Further, the initial values of this stage are i Lr (t 5 ) = I Lr5 , v ds1 (t 5 ) = V c and v ds2 (t 5 ) = 0. Based on Equation (4) and by taking the Laplace transform of Equation (17), the following equations can be attained: By taking the inverse Laplace transform, the following equations can be attained: According to Equations (5) and (19), the equation of v ds2 (t) can be simplified to According to Equation (20) and v ds2 (t 6 ) = V c , the corresponding time elapsed T 6 is As illustrated in Figures 3 and 10, S 1 and S 2 are still OFF, In the previous stage, v ds1 is equal to zero, whereas v ds2 is equal to V c . During this stage, i Lr is still larger than I in , making D s1 conducted, hence v ds2 still clamped at V c . At the same time, the voltage across L r is − V o , causing L r to be linearly demagnetized. As soon as S 1 is conducted, this stage comes to an end and the next stage begins.
As the initial value of this stage is i Lr (t 6 ) = I Lr6 , solving Equation (22) yields Because i Lr (t 7 ) = I Lr7 , the corresponding time elapsed T 7 is Stage 8: (t 7 ≤ t ≤ t 8 ) As illustrated in Figures 3 and 11, S 1 is conducted and S 2 is still OFF. In the previous stage, D s1 is conducted so S 1 is switched on with ZVS at t 7 . As i Lr is still larger than I in , the voltage across L r is still −V o , causing L r to be still linearly demagnetized. As i Lr = I in , this stage ends and the next stage starts. According to Figure 11b, one stage equation can be obtained as As the initial value of this stage is i Lr (t 7 ) = I Lr7 , solving Equation (25) yields Because i Lr (t 8 ) = I in , the corresponding time elapsed T 8 is Stage 9: (t 8 ≤ t ≤ t 0 + T s ) As illustrated in Figures 3 and 12, S 1 is still ON but S 2 is still OFF. Hence, v ds2 is clamped at V c . During this stage, i Lr is smaller than I in , changing i ds1 to the positive direction. At the same time, the voltage across L r is −V o , causing L r to still be linearly demagnetized. From Figure 3, it can be seen that, as i Lr = 0, the output diode D o is cut off before the turn-off time point of v gs1 , meaning that D o has ZCS turn-off. Once i Lr = 0, this stage ends with the next cycle repeated.
According to Figure 12b, one stage equation can be obtained as As the initial value of this stage is i Lr (t 8 ) = I in , solving Equation (28) yields Because i Lr (t 0 + T s ) = 0, the corresponding time elapsed T 9 is If T 8 plus T 9 , which is about T 9 , is smaller than t on , i.e., DT s , the resonant inductor L r works in DCM, meaning that there is no reverse recovery current during the turn-off period of D o . Because v gs1 and v gs2 have two blanking times between them per cycle, if T 9 is larger than t on , then at the instant when S 1 is cut off, but S 2 is still OFF, i Lr will flow through D s1 . Once S 2 is turned on, a large reverse recovery current will flow through S 2 owing to a reverse voltage of V c across D s1 . Accordingly, S 2 may be destroyed as a result of this current spike or S 1 is turned on again, causing shoot-through between S 1 and S 2 . Table 1 is used to summarize soft switching types in the proposed converter.

Voltage Gain
By applying the voltage-second balance to L in , we can obtain By rearranging Equation (31), we can obtain where By applying the voltage-second balance to L r , we can obtain By rearranging Equation (34), we can obtain Substituting Equation (35) into Equation (32) yields It can be seen from Equation (35) that the active clamp voltage V c is larger than the output voltage V o , whereas it can also be seen from Equation (37) that this voltage gain is smaller than that of the conventional boost converter in CCM. Table 2 shows the system specifications, whereas Table 3 shows the component specifications.

Design of Input Capacitance C o
As for output capacitor design, Equation (38) is used on condition that the maximum output voltage ripple ∆v o,max is equal to 0.1% of the output voltage V o , the value of R is 17.6 Ω, T s is 10 µs, D = 0.43, and V o = 42 V. After some calculations, the value of C o is larger than 244 µF. Eventually, a 470 µF capacitor is chosen, because the value of the electrolytic capacitor will be decreased if the switching frequency is increased.

Design of Input Inductance L in
Because the converter operates in the CCM for any load, the minimum value of L in , called L in,min , can be represented by where R max = 176 Ω, D = 0.43, and T s = 10 µs. Based on Equation (39), L in,min = 123 µH after some calculations and, eventually, the value of L in is chosen to be 150 µH by considering the inductance reduction owing to the temperature and load. After this, a T175-18 core, manufactured by Micrometals, Inc. (Anaheim, CA, USA) is utilized, which has an inductance coefficient A L1 of 82 nH/N 2 , and hence the number of turns, called N in , is Eventually, based on Equation (40), the value of N in is chosen to be 43.

Design of Resonant Capacitance C s
According to stage 2 in Section 2 with C s1 = C s2 = C s , from Equation (7), we can obtain the following: From Equation (32), we can get the relationship between V in and V c , with α being positive and smaller than 1, as shown in Equation (42): During stage 2, v ds1 rises from zero to V c and v ds2 falls from V c to zero. Based on the IRF540 datasheet and its characteristic curves of rising time t r and falling time t f versus drain current I ds , we can know that the value of T 2 is about 0.02 µs. Hence, from Equations (41) and (42), we can attain the inequation of the resonance capacitance C s to be C s < 4.21 × 0.02 µs 42 × 2 = 1nF (43) As the resonant capacitance C s is equal to the parasitic capacitance of the power switch, two IRF540 MOSFETs with typical output capacitance of 125 pF are chosen for S 1 and S 2 to meet the requirements of Equation (43).

Design of Resonant Inductance L r
After the resonant capacitance C s is determined, the design of the resonant inductance L r will follow. As the resonant radian frequency ω 1 is desired not to affect the operation behavior of the converter, the value of ω 1 ten times larger than the value of the switching radian frequency ω s , namely, ω 1 > 2π × 10 6 rad/ sec. Therefore, based on Equations (43) and (44), the inequality of L r can be obtained to be Accordingly, the value of L r is chosen to be 10 µH. After this, a T175-18 core, manufactured by ARNOLD Co., is adopted, which has an inductance coefficient A L1 of 75 nH/N 2 , and hence the number of turns, called N r , is Finally, based on Equation (45), the value of N r is chosen to be 11.

Design of Active Clamp Capacitor C c
Regarding the design of the active clamp capacitor C c , it can be designed based on the required voltage ripple ∆v c . From stages 2, 3, 4, 5, and 6 and Figure 3, it can be seen that C c has the behavior of slight charge and discharge. Therefore, the product of C c and ∆v c can be expressed as where T 5 and T 6 are the times elapsed for stages 5 and 6, respectively. Because individual switch parasitic capacitors in stages 2 and 6 have charge and discharge, the corresponding times elapsed are so short. Therefore, if two switches are identical, then Accordingly, based on Equation (16), T 5 plus T 6 can be represented by In order to find the value of C c , the currents i ds2,max and I Lr5 should be figured out first. From stage 5 and Figure 8, the value of i ds1,max can be obtained to be From Equation (49), the value of I Lr5 should be figured out first, via stages 2 and 6 in Section 2.2.1. Based on Equations (7), (21) and (47), the following equation can be obtained to be 1 Rearranging Equation (50) yields Finally, substituting Equation (51) into Equation (49) yields As I in = I o,rated /(1-D), I in can be obtained to be 4.165A from Table 2, if the voltage ripple ∆v c has 5% of V c , then, substituting Equations (48), (51), and (52) into Equation (46), the value of C c can be expressed to be To solve the value of C c , the value of V c should be figured out first. From Figure 3, the following equation can be obtained: Sequentially, from stage 2 in Section 2.2.1, the following equation can be obtained: From Section 2.2.1, it can be seen that i ds1 (t 2 ) = 0 can be found and i Lr (t 2 ) ∼ = 0.22 A can be found based on Equation (3) and T 2 ∼ = 0.02 µs. Substituting i ds1 (t 2 ) = 0 and i Lr (t 2 ) ∼ = 0.22 In addition, from stages 3 to 5, the voltage across L r is V c − V o , thereby causing L r to be linearly magnetized with i Lr (t) = I in + i ds2 (t), hence i ds2 (t) has the same slope from stages 3 to 5. Accordingly, based on the ampere-second balance, the following equation can be obtained: From Equations (33) and (47), the following equation can be obtained: Based on Equations (48), (54), (57), and (58), the following equation can be obtained: Based on Table 2 Solving Equation (63) yields C s ∼ = 1.33 µF. Eventually, the value of C s is selected as 2.2 µF.

Digital Control Flow Chart
As shown in Figure 13a, there are five modules in the digital control strategy, including output voltage sampling, named V_sample; input current sampling, named I_sample; lookup table; digital controller; and digital pulse width modulation generator, named DPWM.

System Operation
In Figure 13a, the output voltage and the input current are sensed by the V_sample module and the I_sample module, respectively. The sensed output voltage is sent to the digital controller and then to the DPWM generator to create a suitable gate driving signal for the switch S 1 , so as to keep the output voltage constant at a desired value. The sensed current is sent to the look-up table to generate a suitable gate driving signal for the switch S 2 , so that the cut-off time point of the auxiliary switch S 2 can be determined.

Auto Tuning of the Last Blanking Time of S 2
From Section 2, we can see that as the auxiliary switch S 2 is cut off, the resonant inductor L r begins to be demagnetized, and the demagnetization path will pass through D o , leading to the power dissipation in D o . Accordingly, cutting off S 2 early reduces the required time flowing through D o , hence the power dissipation in D o will be decreased, increasing the overall efficiency. Therefore, a lookup table is built up with the relationship between the cut-off time point of S 2 and load current I o . However, it is noted that, as for the auto tuning of the cut-off time point for S 2 , the resonant current i Lr should be larger than the input current I in before the main switch S 1 is switched on so as to make sure that S 1 is switched on with ZVS. In the following, how to construct this lookup table is mentioned below.
Step 1 Under an open-loop test with ten points from light to rated load, the maximum efficiency for each sensed input current is obtained by manually tuning the cut-off time point of the auxiliary switch S 2 . This sensed input current is digitalized and then used to generate one interval value in a look-up table.
Step 2 For each point, the corresponding cut-off time point of S 2 under the maximum efficiency is recorded.
Step 3 A lookup table with cut-off time point of S 2 versus interval value created from the input current is established as shown in Figure 13b. After this, as an actual input current is sensed and digitalized; this value will be stored in the register REG and then compared with interval values in the lookup-up table to obtain the required cut-off time point of S 2 , called L_T. The corresponding gate driving signal for S 2 is obtained as illustrated in Figure  14. Accordingly, the proposed converter will do a good performance on efficiency under different input current levels. It is noted that the hysteresis band is applied to the exchange of two cut-off time points to avoid oscillation. It is noted that the proposed auto-tuning technique is used in the steady state. First, the input current I in is sampled at a time point within the turn-on time t on of v gs1 . After this, based on the lookup table, the corresponding cut-off time point of v gs2 for the auxiliary switch S 2 will be determined, which will be used in the next cycle of v gs2 . As to v gs1 for the main switch S 1 , it is almost not changed because the duty cycle of v gs1 is generated from the controller, hence the system stability is almost not affected.

Results and Discussion
At a rated load, Figure 15 shows the gate driving signals for S 1 and S 2 , called v gs1 and v gs2 , respectively. Figure 16 shows the gate driving signal for S 1 , called v gs1 ; the voltage on S 1 , called v ds1 ; and the current in S 1 , called i ds1 . Figure 17 shows the gate driving signal for S 2 , called v gs2 ; the voltage on S 2 , called v ds2 ; and the current in S 2 , called i ds2 . Figure 18 shows the voltage on C c , called v c , and the current in L r , called i Lr . Figure 19 shows the voltage on D o , called v Do , and the current in L r , called i Lr . Figure 20 shows the efficiency comparison.      From Figure 15, it can be seen that v gs1 and v gs2 are complementary to each other. From Figure 16, before S 1 is turned on, i ds1 flows in the opposite direction, causing C s1 to be discharged to zero, making D s1 forward biased. At this moment, S 1 is switched on with ZVS. From Figure 17, before S 2 is turned on, i ds2 flows in the opposite direction, causing C s2 to be discharged to zero, making D s2 forward biased. At this moment, S 2 is switched on with ZVS. From Figure 18, it can be seen that v c is almost kept constant at about 60 V, close to Equation (62). In addition, according to Equation (30), the ideal value of T 9 can be figured out to be From Equation (64), the ideal value of T 9 is smaller than the ideal value of t on of v gs1 , i.e., 4.3 µs. Moreover, from Figure 18, the calculated value of T 9 is 1.36 µs, which is located between 1 µs and 4.3 µs. Therefore, we can confirm that the output diode has ZCS turn-off.
In the following, an efficiency test bench will be described as shown in Figure 19. First of all, the input current I in is attained by measuring the voltage on one current-sensing resistor according to one digital meter. Afterwards, the input voltage V in is also attained by another digital meter. Therefore, the input power can be attained. As to the output power, the output current I o is read from one electronic load and the output voltage V o is also attained by the other digital meter. Thus, the output power can be attained. Eventually, the required efficiency can be attained. In Figure 20, there are three cases used for efficiency comparison. Case 1 is under soft switching with auto tuning of the turn-off time point of the auxiliary switch. Case 2 is only under soft switching without auto tuning of the turn-off time point of the auxiliary switch. Case 3 is only under the hard switching without auto tuning of the turn-off time point of the auxiliary switch. Therefore, at 10% load, all three have the same the second blanking time, leading to the efficiencies for cases 1 and 2 being the same. As the load is increased, only the second blanking time in case 1 is changed. From Figure 20, it can be seen that the proposed soft switching with auto tuning of the cut-off time point of the auxiliary switch has the best performance in efficiency among them.

Conclusions and Future Work
The traditional boost converter, having an active clamp circuit along with the resonant inductor, is presented herein. Both the main switch and the auxiliary switch can be turned on with ZVS and the output diode can be turned off with ZCS. In addition, as the active clamp circuit is utilized, the voltage spike on the main switch can be suppressed to some extent, whereas because this structure, although the input inductor is designed in CCM, the output diode can operate with ZCS turn-off, leading to the resonant inductor operating in DCM, hence there is no reverse recovery current during the turn-off period of the output diode. Unlike the existing soft switching circuits, in order to improve the overall efficiency further, one look-up table is employed to adjust the cut-off time point of the auxiliary switch so that the current flowing through the output diode is reduced. By doing so, the maximum efficiency is 96.9%. In this paper, the cut-off time point of the auxiliary switch is adjusted only in the steady state. In the future, adjusting the cut-off time point for the auxiliary switch in the transient will be studied. In addition, the MOSFETs and Schottky diode used are all Si-based. For high switching frequency applications, SiC-or GaN-based semiconductors can be more attractive than Si-based ones. This will also be studied.

Data Availability Statement:
No new data were created or analyzed in this study. Data sharing is not applicable to this article.

Conflicts of Interest:
The authors declare no conflict of interest. β T 8 plus T 9 divided by T s t 0 to t 0 + T s Time points used in Figure 3 T 2 to T 9

Abbreviations
Elapsed times for operating stages I Lr2 to I Lr7 Currents in Lr for time points in Figure 3 i ds2,max Maximum current flowing through S 2 N in Number of turns for L in N r Number of turns for L r A L1 Inductor coefficient for L in A L2 Inductor coefficient for L r L in,min Minimum input inductance ∆Q c Net charge in C c