Power Sharing Control in a Grid-Tied DC Microgrid: Controller Hardware in the Loop Validation

: This article presents the development of a low-cost control hardware in the loop platform for the validation and analysis of controllers used for the management of power sharing between the main grid and a DC microgrid. The platform is made up of two parts: a main grid interconnection system emulator (MGISE) and a controller under test (CUT). The MGISE operates on a 260 V DC bus and includes a 1000 W photovoltaic array, a DC variable load and a single H full bridge converter (HFBC). The CUT includes a phase locked loop and a main cascade control structure composed of two PI controllers. Both the MGISE and the CUT were embedded on an NI myRIO-1900 development board and programmed using LabVIEW virtual instrumentation software. These devices communicate with each other using analog signals representing the AC side current, the DC side voltage, and the HFBC control signal. The MGISE operates with an integration time of 6 µ s and its performance is validated by comparing it with a simulation in PSIM. The integration time of the MGISE, the development boards used, as well as its programming environment, and the results obtained from the comparison with PSIM simulation, show that the proposed platform is useful for the validation of controllers for power sharing, with a simple implementation process compared to other hardware description methods and with a low-cost platform.


Introduction
In recent years, CO 2 emissions have increased significantly, and this has caused an increase in the average temperature of the planet and a threat to the health and well-being of humanity. This situation has raised awareness regarding the effects of global warming produced by CO 2 emissions, motivating research that evaluates the effect of energy consumption on climate change. Compared with fossil fuels, renewable energies (RE) facilitate a significant reduction in CO 2 emissions and consequently, the effects of climate change are reduced [1]. In response to this, electrical systems around the world have begun a transition following three trends known as the "three D's": Decentralization, Decarbonization and Democratization. Although the factors and details that guide the "three D's" may differ from place to place, microgrids (µGs) have emerged as a flexible architecture for the deployment of distributed energy sources, including renewable generation (such as photovoltaic cells, small wind turbines, and mini hydro), which satisfy a wide range of needs [2].
According to their mode of operation, µGs can be categorized into isolated µGs (i-µGs) and grid-tied µGs (gt-µGs); i-µGs are mainly used in remote applications where power supply through the MG is not feasible, while gt-µGs operate both in islands and interconnected with the main grid (MG) [3]. The interconnection between the DC µGs and the MG is achieved using power electronic converters (PECs), so correct operation of the DC µG depends largely on the adequate control of these converters [4]. Typically, the µG control is made through a hierarchical scheme, including three levels: for locally measured power exchange, for voltage or frequency regulation and for optimal and economical global µG operation [5]. This hierarchical structure allows multiple controllers' interoperability as well as several coupled elements through PECs such as those used in the µG and MG power exchange [6].
The main function of this type of converter is the power sharing between the AC side and the DC side [7]. Therefore, this active and reactive power sharing plays an essential role in control algorithms of the interconnection converters [8]. Various studies have been published on power sharing control algorithms, and some of these are described below. In [9], a Linear Quadratic Regulator-Based Current Control is proposed for the management of power sharing between the AC and DC buses of a hybrid µG. Study [10] proposes a predictive voltage model and a power control method to manage power sharing between a µG and the MG. In [11], a nonlinear coordinated control strategy for parallel bidirectional power converters for a hybrid AC/DC µG is proposed. In this topology, two bidirectional converters are used; one of them oversees transferring power between the AC side and the DC side. In [12], a droop control strategy is proposed for the control of a bidirectional AC/DC converter used for an electric airplane. Finally, study [13] discusses control techniques for current-controlled and voltage-controlled bidirectional converters in a hybrid AC/DC µG.
In contrast, increasing advances in computer systems and the need to create different types of prototypes that simulate the behavior of physical systems in real time have led to the use of complex, sophisticated and expensive simulation tools. However, traditional simulation systems have the disadvantage of not recreating the actual operating conditions of physical systems. One option to solve this problem is to use the Hardware in the Loop (HIL) real-time simulation (RTS) technique, which reduces the gap between simulation and real conditions [14]. The development of physical systems on HIL platforms is carried out in various areas: For example, [15] proposes a novel HIL simulation configuration using the dSPACE SCALEXIO board with the aim of verifying the validity of an active control strategy of a conventional railway vehicle with a rigid axle set of wheels; this RTS has an integration time (IT) of 10 µs. Conversely, [16] describes the details of an HIL platform (HILP) that uses the dSPACE RCP board for the implementation of an electromechanical system of an aircraft that allows evaluation of landing gear performance. Furthermore, in [17], the development of an HILP with an IT of between 1 and 2 ms is presented to perform analysis of the behavior of cyber-physical energy systems using the RT-LAB and OPNET software.
Several HIL commercial development platforms have been presented. These platforms offer HIL pre-configurated system libraries in their programmatic environments, as well as specific HIL-focused hardware that features a communication layer. Nonetheless, these platforms are generally high cost, making them inaccessible for some researchers. In the search for the development of low-cost HIL platforms, [18] proposes a flexible platform for the simulation of embedded control strategies; in the validation stage of their proposal, they present two case studies: the first is an automotive application and the second a space application. In this proposal, an FPGA is not used because complex languages for description of hardware are required to make good use of resources from the devices. Instead, a computer with a DAQ-6703 data acquisition system was used as an interface; this HILP has a 200 µs IT. In this same manner, [19] proposes a low-cost HILP, with an IT of between 1 and 1.5 µs, for the simulation of electrical machines and their controllers. The implementation of the system is carried out on the Texas Instruments DSP TMS28379D board using C language; in this research, results were compared with commercial PSIM models. When working with platforms where the designer must embed their proposals, it is necessary to choose appropriate methods for the design and implementation of HILPs. In [20], two methods are proposed for the implementation of HILPs; these methods seek to compare a system with the optimal resolution to have a performance comparable to the real system, and a second conservative method for resolution of the variables using the FPGA Xilinx XST0 development board (DB). An HILP was developed to validate these methods with an IT of 10 ns.
Working with HILPs presents a low-cost option that allows developers to test new prototypes by performing reliable experiments in a short time. One of the areas where HILPs are being used for the validation of various proposals is in power electronics, specifically in elements that make up the DC µGs. In [21], an experimental platform for wind turbines based on HIL was presented for the study of control structures. In [22], the MATLAB/XSG environment was used for the mathematical modeling of the aerodynamic and mechanical aspects of a real wind turbine. The Xilinx FPGA Virtex 5 LX50 T DB with an IT of 50 µs was used, and rapid prototyping using MATLAB/Xilinx System Generation was performed.
Among the investigations carried out on DC µGs, there are applications that focus on the PECs that comprise them. In [23], an HIL simulation with an IT of 50 µs was used to validate the proposal of a resonance mitigation controller used in series with a source voltage controller in a dual active bridge converter. To implement the system, an OPAL-RT simulator was used. A similar emulator was used in [24] to implement a DC µG and test its proposed power management system; this application was developed with an IT of 1 ms. In [25], a modular development for the control of PECs was presented using a P-HIL platform, with an IT of between 9.44 and 15.72 µs, based on a Xilinx Zynq-7000 development system. In [26], an HILP to test control algorithms was presented; this research focused on an energy administration technique. Furthermore, in [27], the design of an HILP, with a 100 µs IT, of a multilevel converter that includes a control system test scheme based on the FPGA OP5607, was presented. Investigations in converters may include other aspects in addition to their electrical characteristics; for example, in [28], an electrothermal model of an interleaved boost converter was developed using an FPGA. The HILP was designed using a graphical programming environment in LabVIEW, embedding the system in the NI-7975R FlexRIO DB with an IT of 25 ns.
For the design and implementation of HILPs to emulate DC µGs, various DBs have been used. In [29], the Typhoon 602+ platform was used to emulate the behavior of a DC µG with an IT of 1 µs, while for the TMS32028335DSPC, Spartan 6XC6SLX16FPGA DBs were used to control the different converters, which operate with a modulation frequency of 10 kHz. These implementations were carried out to analyze the effect of the drivers on the transitions of the DC µG converters. In [30], the same platform to emulate a DC µG was used; this time, the objective was to measure the effectiveness of the proposed Adaptive Droop Control; the control systems are embedded in a Texas Instruments DSP DB. In contrast, in [31], a robust control strategy was presented to solve the stability problems caused by constant power loads in a DC µG. To demonstrate the operation of the proposed controller, a simulation in MATLAB was compared with experimental results using an HILP implemented on the DSP (TMS320F28035) DB. National Instruments platforms have also been used. In [32], a DC µG HILP was developed to validate the behavior of a DC bus voltage control system; in this design, the NI-PXIe-1078 DB was programmed with LabVIEW software. In [33], an HILP of a DC µG using an RT-LAB and NI cRIO-9030 emulator was implemented; with this platform, the behavior of the system controllers, as well as their stability, were tested. In [34], an HILP was proposed, with an IT of 20 µs, as a new method to develop and test control algorithms and operation strategies in DC µGs; this proposal uses RT-LAB (OP5600) for the implementation of the components of DC µG and an NI cRIO-9025 DB for the control and administration of the DC µG. In [35], the stability of the converters connected in parallel in a DC µG is analyzed; for this, an HILP was developed with the RT-LAB software and an AD7606 data acquisition board. In [36], an OPAL-RT device was used to emulate the behavior of a DC µG, presenting the advantage of considering delays and errors; these considerations allow the characteristics of the fuzzy controller proposed in this research to be strengthened.
An HIL simulation is considered control hardware in the loop (C-HIL) when the power elements of a system are emulated in real time, while its controller, or part of it, is embedded in an external hardware device [37]. This technique allows experimentation with real controllers under a wide range of operating conditions without the risk of damaging real components [38] and has been used to validate controllers in PECs. In [39], work was carried out with an i-µG, a C-HIL with an IT less than 1 µs to validate the controllers applied to a photovoltaic system, and a storage system using batteries. In [40], a C-HIL platform to validate the control strategies applied to a multifunctional converter was developed. In this platform, the controller was emulated in a dSPACE with a 6 µs IT. In [41], the C-HIL technique to validate different control strategies applied to a universal PQ compensator for low-voltage distribution networks was used. The HILP used had an IT of 15,625 µs.
This article proposes the development of a C-HIL platform for the analysis of controllers aimed at managing the power sharing between a DC µG, with a photovoltaic array (PA) as the main source of energy, and the MG, considered as first-level controllers in the µG's hierarchical control structure. The proposed platform consists of two elements: a real-time emulator that reproduces the behavior of the main grid interconnection system (MGISE) and a controller under test (CUT) to validate the platform. The emulator includes a PA with a maximum power of 1000 W, a bidirectional AC/DC converter based on the H full bridge converter (HFBC) topology, and a load on the DC side; also this emulates the MG. The emulator operates with a 6 µs IT. It has three analog outputs that represent the DC side voltage, the AC side current and the voltage signal of the MG; it also has an analog input that represents the control signal of the HFBC. The CUT, on the other hand, has two main parts: a phase-locked loop (PLL) type Park-PLL and a main control structure that includes two loops nested with PI controllers.
The proposed HILP allows for cascaded PI controller validation. This controller is simple and is effective for energy transfer management while having low computational costs during implementation. The results obtained with the proposed implemented C-HIL technique platform demonstrate its usefulness and that this platform could be an option for researchers, such as [7][8][9][10][11][12][13], to validate their controllers before an experimental prototype implementation. The HILP offers advantages during the validation process, in comparison with a software simulation, because of a test feature that allows the real time behavior of real hardware implemented controllers to be observed, obtaining the same results that would have been obtained with a real system and permitting observation of environmental variable changes as well, such as the behavior of the MG. In order to guarantee real time execution of the HILP, the hardware device's IT is the most important variable to take into account. The proposed HILP has an IT of 10 µs; this time is enough to emulate real time continuous signals. In comparison with dedicated HIL platforms, the proposed HIL features low-cost hardware. It has a self-owned, high-level description environment, which facilitates and expedites platform development, and, in comparison with solutions such as those presented in [22], a tripartite software to embed the developed systems in the hardware is not required. All of these advantages together offer a useful and versatile HILP, built for power sharing controller analysis in µGs applications, with features such as low cost and benefits comparable to those of the commercial platforms.
The article is divided into five sections. Section 1 comprises the introduction. Section 2 presents a description, modeling and design of the elements that make up the main grid interconnection system (MGIS); the elements included in this section are HFBC, a PA and the controller proposed to validate the C-HIL platform. Section 3 describes the implementation of the systems in the NI myRIO-1900 (myRIO) DB and the conformation of the C-HIL platform interconnecting the emulator in real time that reproduces the behavior of the HFBC and the controller. Section 4 shows the results obtained with the C-HIL platform for a series of open loop and closed loop experiments, with the HFBC operating as a rectifier and inverter. The results obtained in this section are compared with results obtained through software simulations in MATLAB and PSIM. Finally, Section 5 presents the discussion and conclusions related to the advantages that our proposal presents over some similar proposals reported in the literature.

MGIS: Description, Modeling, and Design
The topology used for the implementation of the MGIS shown in Figure 1 includes a single-phase HFBC made up of a power stage; switches Q 1 , Q 2 , Q 3 and Q 4 ; a capacitor C; and an inductor L that has an associated resistance r. This topology is typical for the interconnection of distributed generation systems and µGs with the MG [42]. Additionally, the proposed topology includes a PA in the DC side, which represents the main source of energy that feeds the DC load, R. When the energy generated in the PA is greater than that consumed by the DC load, the rest of the energy is transferred to the MG. In the event that the energy generated by the PA is not enough to satisfy the demand of the DC load, the necessary energy is extracted from the MG. i pv represents the electric current supplied by the PA; i R is the current of the DC load R; i c is the current in the capacitor C; v dc is the DC bus voltage, which, in turn, represents the DC side voltage of the HFBC; i dc is the DC side current of the HFBC; v ab is the AC side voltage of the HFBC; i a is the AC side power of the HFBC, which, in turn, corresponds to the electric current of inductor L; and v g , which corresponds to the voltage of the MG. The proposal is based on the design of a platform to evaluate the controller's operation used in power sharing between a µG and the MG in a stage prior to its implementation in the field, eliminating the risk of damage to the real device. An isolation transformer is not contemplated in the proposed topology; however, it is recommended to include it in its physical implementation.

Photovoltaic Array Description and Modelling
For PA modeling, a Keysight E4360A photovoltaic panels emulator was used as a reference. As mentioned in [43][44][45][46][47][48], the device is used to substitute a real PA, presenting identical behavior. The emulator reproduces the characteristic current-voltage photovoltaic curve, based on parameters such as the open-circuit voltage V oc ; the voltage and current in the maximum power point V mpp and I mpp , respectively; and the short-circuit current I sc [49], while adding two extra variables (R s and N), which are dependent on the four previously mentioned parameters. Equation (1) defines the relationship of the PA current I p and its voltage V p .
The terms V p0 I p and R p are calculated according to Equations (2) and (3).
In contrast, Equations (2) and (3) depend on the variables R s , a and N, which are a function of the input parameters (V oc , V mpp , I sc and I mpp ), calculated with Equations (4)- (6).

H Full Bridge Converter Description and Modeling
In order to propose the HFBC model, a sinusoidal type u modulating function is initially defined as described by Equation (7).
where m is the amplitude of the modulator, α is its phase angle with respect to the MG voltage, ω is its angular frequency defined as ω = 2πf and f defines the operating frequency of the HFBC, which is equal to the frequency of the MG. To generate the switching function of the power switches Q 1 , Q 2 , Q 3 and Q 4 , the sinusoidal pulse width modulation (SPWM) unipolar technique type was used [50]. The HFBC power circuit and the schematic SPWM modulator are shown in Figure 2. Once the switching strategy has been defined, a simplified HFBC circuit is generated by replacing the two power switches on each branch with a single pole double throw (SPDT) switch. With this simplification, the power circuit of Figure 2 is reduced to the form shown in Figure 3, where Q 1 − Q 2 are replaced by SW 1 and Q 3 − Q 4 by SW 2. From the simplified representation of the power circuit shown in Figure 3, the dependence between the voltages and currents of the AC side and the DC side is obtained. Table 1 shows the possible combinations of the switching functions of the SPDT switches, and the values obtained for v ab and i dc in terms of v dc and i a . The variables q 1 and q 2 are the switching functions of SW 1 and SW 2 , respectively, and the variable q is defined as q = (q 1 − q 2 ). Table 1. Definition of the switching functions.
The switching function q is equivalent to the sum of the modulating signal, u, and several high frequency components, due to the presence of the triangular signal in the modulator, which are neglected because the frequency of the triangular signal is much higher than the frequency of the modulating signal, so that q = u [51]. From this equivalency and Table 1, expressions for v ab and i dc are obtained in terms of v dc and i a , as shown in Equations (8) and (9). v ab = uv dc (8) With Equations (8) and (9), a new simplification of the power stage of the scheme presented in Figure 1 is generated, replacing the switches with dependent current and voltage sources, obtaining the simplified scheme of the MGIS as illustrated in Figure 4. By applying Kirchhoff's voltage law (KVL) in the loop that includes the inductor L, the expression presented in Equation (10) is obtained. Subsequently, when using Kirchhoff's current law (KCL) on the node that includes the capacitor C, the expression of Equation (11) is generated.

H Full Bridge Converter Design
The HFBC design requires the dimension of the passive elements. These are evaluated for maximum values of active power P, and reactive Q. To achieve the maximum symmetric compensation of active and reactive power to the DC bus voltage, a value twice the magnitude of the voltage for the MG V g is given. Additionally, when the highest amount of power is shared, the amplitude of v ab is equal to v dc ; this implies, according to Equations (7) and (8), that m = 1. Applying these considerations, the coupling inductor is calculated with Equation (12) [52].
where P max is the maximum active power; α 1 is calculated with Equation (13), where Q max is the maximum reactive power.
In contrast, the capacitor in the DC side is calculated with Equation (14), where ∆v dc is the ripple of the DC side voltage [52].

Open Loop Main Grid Interconnection System Response
To validate the behavior of the MGIS, its responses were evaluated in open loop for the two operation modes: rectifier and inverter. To calculate the amplitude and phase of the modulating signal that determines the desired operating state, the AC loop presented in the diagram in Figure 4 is considered. For this validation, a value of zero was established for reactive power. This condition is desirable since it implies the state of operation with greater efficiency. Under this consideration, the HBFC AC side voltage is in phase with the AC side current so that its magnitude, V ab , is determined with Equation (15) as a function of the instantaneous active power that is shared, P, and the magnitude of the AC side current, I a .
With this condition, when applying the KVL to the AC loop in Figure 4, Equations (16) and (17) are obtained for the rectifier and inverter modes of operation, correspondingly. Two equations are generated from this loop, since, in the rectifier mode, the HFBC transfers energy from the MG and uses it in the DC side while, in the inverter mode, the energy generated by the PA that is not consumed in the DC load is injected into the MG. With this change in the direction of the energy flow, the direction of the AC side current changes, so the inductor voltage, (r + jωL)I a , changes sign.
In Equations (16) and (17), the variables V g , V ab and I a represent the phasors of the MG voltage, the AC side voltage and the AC side current, respectively. From these equations, the phasor diagrams shown in Figure 5 were generated.
is the magnitude of the inductor voltage phasor. From these phasor diagrams, the phase angle of the modulator, α, is obtained by calculating its tangent with the triangle ABC, as shown in Equation (18).
Nevertheless, to obtain the value of α, it is necessary to know the value of I a . The magnitude of the sides AD and DB of triangle ABD depend on I a , while AB = V g is known. Thus, when applying the law of cosines to triangle ABD, with respect to angle γ, Equation (19), which depends on I a , is generated.
By solving Equation (21), the value of I a is obtained where the value of α is determined with Equations (15) and (18). The angle γ, on which Equation (21) depends, is a function of the operation mode and is calculated from triangle BCD in Figure 5, as shown in Equation (22).
Finally, the magnitude of the modulator is determined from Equations (7) and (8), as shown in Equation (23).

Controller Description
The control scheme proposed to validate the work as a C-HIL platform is made up of two sections: (1) a PLL, which generates a sinusoidal signal in phase with the MG (θ = ωt) and (2) the control structure, composed of two nested loops with PI controllers, whose output is the modulating signal u. The diagram of the implemented controller is shown in Figure 6. The PLL block of the controller in Figure 6 is type Park-PLL, which is based on the Park's transformation and is characterized by being robust, having a relatively fast transient response and a high rejection of disturbances [53]. The Park-PLL diagram is presented in Figure 7. In this structure,θ is the approximation of the phase angle of the MG. The signals v g r and v g i are, respectively, the voltage of the MG and a signal that corresponds to this same voltage, with a phase shift of π 2 rad; this phase shift was generated using a quarter cycle delay. These signals constitute the rotating frame of reference of Park's transformation and are defined by Equations (24) and (25).
where θ = ωt is the phase angle of the MG voltage. In contrast, the signal v q is defined from the Park transformation [54], as shown in Equation (26).
The reference v q * = 0 implies that sin θ −θ = 0 for this to be true, and the difference between the angles must be zero and, therefore,θ =θ when the system stabilizes.

HIL Implementation
Two myRIOs were used for the implementation of MGISE and CUT. Devices such as field programmable gate arrays (FPGAs) and digital signal processors are common in the development of real time emulators using generic low-cost hardware [55], and the myRIO integrates both technologies in a single board with a 40 MHz clock [56]. These platforms have differential high-impedance analog inputs, which allows them to be interconnected while maintaining an optimized common mode rejection ratio (CMRR) in balanced circuits. In addition, the parallel processing of the FPGA allows the rapid resolution of multiple equations simultaneously with integration periods in the order of tens of microseconds. Ref. [57] uses a Xilinx Virtex 7 FPGA-based platform to validate the management system in a µG by an HIL simulation and generates simulation steps between 200 ns and 2 µs. In [58], a platform to emulate a photovoltaic system was implemented using a myRIO; this platform operates at a 1 ms integration time. Ref. [59] uses cRIO, FPGAs and a processor to emulate a µG with simulation steps of around 5 µs. Another advantage of this system is that its programming can be carried out using a high-level graphic language; this results in the development of applications more easily and quickly compared to other techniques [60]. The hardware description of the emulator proposed in this study was carried out using LabVIEW virtual instrumentation software. To achieve high performance, high throughput blocks with fixed point data types were used; these types of operation and data have a direct impact on the performance of the application, as well as on the use of hardware resources [61]. The proposed HILP implementation process is presented in this section. It is comprised of a real time emulator that reproduces the HFBC behavior, the controller, and their interconnection.

C-HIL Platform
The C-HIL platform proposed in this study is composed of two parts: the MGISE and the CUT. The MGISE emulates the behavior of the MG and the topology presented in Figure 1. For its implementation in hardware, this emulator was divided into two sections: the first is responsible for emulating the behavior of the PA (PAE) and the second emulates the HFBC (HFBCE). Similarly, the CUT implementation was divided into two blocks: the PLL and the main control structure. The configuration of the proposed platform is presented in Figure 8. The MGISE and CUT were implemented independently on one myRIO each. These two boards communicate with each other through analog signals; the signals v g , v dc and i a , which represent the MG voltage, the DC side voltage and the AC side current, are sent from the MGISE board to the CUT board and this, in turn, feeds back to the MGISE with the control signal u. With this configuration, it is possible to validate different structures and algorithms for the CUT. The controller described in this study was implemented to test the structure and validity of the developed platform, but it does not imply that it is the only controller that can be analyzed with the developed platform. The implementation of each of the parts that make up the C-HIL platform is described in the following sections.

Photovoltaic Array Emulator Implementation
To implement the PA model presented in Equation (1), a one-dimensional LookUp Table (LUT-1D) was used. This technique is used in studies such as [62][63][64] for HIL implementations. The model of Equation (1) was solved in MATLAB's Simulink generating 1024 equidistant values, between 0 and V oc , for V p . The block diagram implemented for this purpose is shown in Figure 9. The values obtained for I p were divided by I sc , scaled and rounded, so that integers obtained were between 0 and 65,535, representing current values between 0 and I sc . These values were then saved on a datasheet and assigned to the LUT-1D. For the implementation of the PAE, the voltage V p was scaled with a factor k 1 = 1023 V oc by means of a multiplication block. The output of this block was configured with a data type without a fractional part so that integer values between 0 and 1023 were obtained that represent the address of the LUT-1D. The output range of the LUT-1D is [0, 65535]; this range of values is scaled with a factor k 2 = I sc 65535 by means of a multiplication block so that current values between 0 and I sc were obtained at the output. Figure 10 shows the PAE implementation diagram.

H Full Bridge Converter Emulator Implementation
To embed the HFBC, the discrete model shown in Equations (27) and (28) was generated from Equations (10) and (11), where T is the period of the hardware device. Figure 11 shows the utilized schematic diagram for the implementation of the discrete model of the HFBC; this embedded system (ES) will act as the HFBCE. The frequency of the MG, f, was established at 60 Hz and its amplitude at 180 V; a value of 0.4 Ω was assigned to the resistance r, associated with the inductor; and a maximum active power level of 1200 W was defined. With these specifications and applying the calculations described in Section 2.3, L and C values of 4.1 mH and 4576 µF were defined, respectively. This ES has the panel current I p , the MG voltage v g and the modulating signal u as inputs and as outputs of the DC side voltage v dc and the AC side current i a . Figure 11. Implementation of the discrete H full bridge converter model.

Main Grid Interconnection System Emulator Implementation
For the implementation of MGISE, the ES presented in Figure 12 was developed. It integrates the ESs of the PAE and the HFBCE. The MGISE ES includes an analog input that represents the modulator signal u and two analog outputs that represent the variables v dc and i a . These input and output signals from the MGISE were used to interconnect with the CUT. The u signal takes values between −10 and 10 V, which, for this ES, represent values between −1 and 1. The i a signal, with voltage values between −10 and 10 V, represents a range between −256 and 256 A. Additionally, the v dc signal, with values between 0 and 5 V, represents a range between 0 and 512 V for the ES. In addition, the MGISE ES includes two local variables that act as inputs; assigned as v g and u, these two variables are the MG voltage and the modulating signal used for open loop tests. Additionally, the Boolean variables "Panel" and "Loop" determine the connection or disconnection of the panel and the operation of the MGISE in open loop and closed loop, correspondingly. The MGISE is performed with an integration time of 6 µs; this time is the result of an iterative process in which, initially, an integration period and a data weight are defined (to represent the constants dependent on the period). Later, the time of the actual implementation of a cycle is measured and compared with the selected period; then, the period is reduced, the weight of the data is redefined and the real time is measured again. At a certain point, a reduction in time period implies an implementation of real time greater than the one proposed, so that there is a minimum period for which the real and defined times coincide [61]. This process was carried out for each of the ES presented in this section. Constants k 3 to k 5 were used to normalize analog signals.

Open Loop
For the validation of the behavior of the MGISE in open loop, an ES was implemented that generates a modulating signal with variable amplitude m and phase angle ϕ. The amplitude and phase shift angle of the modulating signal are set by controls in this ES. In contrast, the MG voltage, v g , is an emulated signal in the same while loop; in addition, this signal was connected to an analog signal that was compared with the signal generated with the PLL to verify its correct operation. The ES implemented for the emulation of these signals is shown in Figure 13. Constants k 6 to k 8 were used to normalize the analog signals. Figure 13. Embedded system to emulate v g and u signals.

Main Grid Interconnection System Emulator Real Time Processor
The ES of Sections 3.5 and 3.6 were implemented in the FPGA of a myRIO and this, in turn, was managed from the real time processor (RTP) of the myRIO. In the RTP, the variable 1 − T RC of the discrete model of Equation (28) is defined. Additionally, through its control panel, the operator interacts with the MGISE. In this control panel, the operator has controls to define the variables R, of the HFBC model, "Panel" and "Loop", described in Section 3.4, as well as the amplitude and phase angle of the modulation signal for open loop tests. In addition, indicators were employed to display the voltage on the DC side and the integration period of the FPGA.

Controller
To validate the MGISE as a platform for the development of the experimental stage on real controllers following the C-HIL technique, the controller described in Section 2.5 was embedded in a myRIO.
An essential element in the implementation of the controller is the action of the PI controller; this is because the structure of the control used has three of these controllers: one for the PLL and two for the main control structure. The discrete model of the PI controller defines the control action u(k) in terms of the error e(k), and the proportional, k p , and integral, k i , gains, as shown in Equation (29) [65]. Figure 14 shows the ES block diagram to implement the model of Equation (29). The scheme presented in Figure 14 shows the PI controller of the PLL of Figure 7; however, similar diagrams were used for the inner loop and outer loop controllers of the control structure. Another element that composes the PLL is the Park transformation. The programing employed to calculate the v q component such as in Equation (26) is presented in Figure 15. The last block that composes the PLL is the integrator. For this element, if x(k) is the result of the integration and dx(k) is the variable which will be integrated, the model was proposed as shown in Equation (30). Additionally, the angle at the output of the integrator only takes values between 0 and 2. These values are interpreted in the sin(x) and cos(x) functional block of the structure shown in Figure 15, as if they took values between 0 and 2π. Figure 16 shows the schematic diagram to implement the integrator; in this diagram, the value of T = 16.6 µs. The block named "Select" is responsible for limiting the x(k) output value between 0 and 2.
x(k) = x(k − 1) + dx(k − 1)T (30) Figure 16. Block diagram for implement the PLL integrator. Figure 17 shows the implementation of the control structure. The presented controller in Figure 6 was implemented by using two loops. The first loop has a 16.65 µs execution time, allowing the loop to execute approximately 100 times for each MG period signal. In this loop, a PLL was implemented, joining Figure 14 to Figure 16 structures, the inner PI controller, the multiplication u 1 * sin θ and the summing junction 2 (defined in Figure 6). This loop has analog input and output signals. The input signals represent the MG voltage and the AC side current and are received from the MGISE. The output signals are the control signal u, sent to the MGISE, and the value of sin θ ; this signal is used to validate the PLL, comparing it with the MG voltage signal. The second loop includes an input (defined by the user in the PC) to define the DC side voltage reference (v dc * ), the summing junction 1, the PI outer controller and the gain −2 V g (defined in Figure 6); its input is the voltage v dc . This while loop has an execution time of 66.6 µs. Constants k 9 to k 13 were used to normalize the analog signals.

Results
In order to validate the reliability of the MGISE, as well as its application and efficiency in the design of a C-HIL platform to analyze controllers that manage the power sharing between the MG and the PA, a set of experiments were carried out. The results of the responses from MGISE and the closed loop system were compared with simulations in PSIM and MATLAB. In Section 2.2, it is established that the HFBC operates with an SPWM modulating signal generated from a high-frequency surround system-that is, the real system is a commutated system; however, the MGISE was implemented by embedding the averaged model of the HFBC. When comparing the results obtained in the experimental stage with the results of the simulation in MATLAB, the software solution of the averaged model is compared, without restrictions on the type and weight of the data and with a continuous solution, with its hardware implementation, which is inherently restricted regarding the type and weight of the data and with a discreet solution. Thus, comparison of the MGISE with MATLAB only offers a measure of the fidelity between the embedded discrete system and a continuous system. Comparison of the results with the PSIM simulation has the purpose of contrasting the results obtained with the implementation of the C-HIL platform and results as close as possible to reality. In the PSIM, the system was simulated using an SPWM modulator signal, similar to how it would be carried out in a real setting (experimental prototype).

Photovoltaic Array
To analyze the different states of power sharing of the MGISE, a PA was used with a maximum power of 1000 W, a V oc of 445 V, a V mp of 360 V, an I sc of 3 A and an I mp of 2.78 A. The PAE's fidelity was verified by comparing the V-I characteristic curve obtained with the direct model of Equation (1) solved in MATLAB with the V-I characteristic curve obtained with the implementation of the LUT-1D, as presented in Figure 10. Figure 18 shows this comparison: the red line corresponds to the characteristic curve V-I generated with the continuous model, while the green line is the characteristic curve generated by the PAE.

Open Loop Rectifier
For validation of the MGISE, an open loop experiment was performed operating in the rectifier mode. In this operating mode, it is assumed that the PA does not generate power, so the HFBC draws power from the MG to supply the DC load. In this experiment, a level of active power extracted from the MG, P, of 1200 W with a unity power factor was defined. The power consumed by the DC load depends on the voltage v dc and the resistance value of R. The value of the DC bus voltage was stablished at 360 V, while the value of R was set at 110 Ω. With these values and applying the calculations described in Section 2.4, the modulation signal was defined with an amplitude of 0.48105 and a phase angle of −6.8346 • . The frequency of the triangular signal f c , in the case of the simulation in PSIM, was set at 9.6 kHz. Figure 19 shows the comparison between the results obtained from the simulations in MATLAB and PSIM, in addition to the results generated with the MGISE for the AC side current. The yellow line represents the response obtained in PSIM, the red line represents the results obtained in MATLAB, and finally, the green line represents the results generated with the MGISE. For this response, mean absolute errors of −0.26 A in regard to MATLAB and −0.27 A regarding PSIM were obtained. In contrast, Figure 20 shows the comparison between the results obtained in the simulation and the results obtained with the MGISE for the v dc signal in the same experiment. For this variable, mean absolute errors of −1.47 V regarding MATLAB and −3.75 V regarding the PSIM were obtained.

Open Loop Inverter
In this operation mode, the PA feeds the DC load with a DC voltage defined by the steady state response and the remaining energy is injected in the MG. With the aim of keeping the energy demanded by the DC load lower than the energy generated by the PA, the bus voltage was calculated at 360 V with a DC load of 2579 Ω. Under these conditions, the PA generates 1000 W, while the DC load consumes 50 W; the remaining 950 W are injected to the MG with a unit power factor. For this, the modulation signal was defined with an amplitude of 0.50953 and a phase angle of 5.103 • . In Figure 21, the response of the AC current is presented, while, in Figure 22, the results obtained for the voltage v dc in the same experiment are presented. The yellow line represents the data obtained on PSIM; the red line-the results obtained in MATLAB; and the green line-the results generated with the MGISE. In this experiment, mean absolute errors of −0.07 and −0.06 A for i a were obtained with respect to MATLAB and PSIM. For the variable v dc , mean absolute errors of −4.92 V and −3.13 V were obtained with respect to MATLAB and PSIM.

PLL
To validate the results of the emulator with the PLL described in Section 2.5, the signal representing the MG voltage generated in the ES, shown in Figure 13, was compared with the signal sin θ generated for the calculation of the Park transformation shown in Figure 15. In this comparison presented in Figure 23, the MG voltage is shown in red and the sin θ signal of the Park transformation is shown in green.

Closed Loop Rectifier
To verify the behavior of the C-HIL platform operating in rectifier mode as presented in Figure 8, a DC load of 110 Ω was selected with a reference of 360 V on the DC bus. Figure 24 shows the results obtained for the AC side current in the closed loop with the MGISE operating in rectifier mode, while, in Figure 25, the behavior of voltage v dc is shown. Finally, Figure 26 illustrates the results obtained for the active and reactive powers in this experiment. In Figures 24 and 25, the red line represents the response obtained in PSIM and the green line illustrates the results generated with the MGISE. In this experiment, regarding the PSIM, mean absolute errors of 0.3 A, −0.67 V, −10.79 W and −45.32 VAR were obtained for the variables i a , v dc , P and Q, correspondingly. In contrast, for the DC side voltage, an average value was obtained in steady state of 360 V. In Figure 26, the red line shows the results obtained for the active power in the PSIM simulation, the yellow line shows the reactive power obtained in PSIM, the green line shows the active power generated by the MGISE and the blue line shows the reactive power generated by MGISE. The values of these signals were calculated using a Park transformation. The negative value of the active power indicates that the energy was transferred from the AC side to the DC side. Figure 24 shows the spectral analysis of the high-frequency current components. The components with the highest magnitude are as follows: • Fundamental frequency ( f ): 60  The other components present an amplitude below 0.5% of the fundamental peak value.

Closed Loop Inverter
In a similar way to the closed loop rectifier experiment, an experiment was carried out with the MGISE operating in inverter mode. For this experiment, the reference value of the DC bus voltage was 360 V, and the value of the DC load was 2579 Ω. Figure 27 shows the results obtained in this experiment for the AC side current, while, in Figure 28, the response obtained for the voltage v dc is presented. Figure 29 shows the behavior of active power, while Figure 30 shows the results of reactive power. The values of this signal were obtained by means of the Park transformation. The positive value of these signals indicates that energy is transferred from the DC side to the AC side. In these figures, the lines in red represent the results obtained in PSIM and the lines in green the results generated by the MGISE. In this experiment, with respect to PSIM, mean absolute errors of −0.05 A, −0.81 V, 3.46 W and 115.89 VAR were obtained for the variables i a , v dc , P and Q, correspondingly. In contrast, for the DC side voltage, an average value was obtained in steady state of 359.92 V. Finally, Table 2 shows a summary of the mean absolute errors obtained for these responses.
Similar to the rectifier mode, the response of the spectral analysis of the current highfrequency components is shown in Figure 27. The components with the largest amplitude are as follows: • Fundamental component ( The other components present an amplitude below 0.64% of the fundamental frequency peak value.

Conclusions
Analysis of the MGISE response shows that the developed platform satisfactorily reproduces the behavior of the real system. This is verified by comparing the responses of the MGISE with the simulations. In the case of the variable i a , in open loop, mean absolute errors of between −0.27 and −0.06 A were obtained. These errors represent a variation of between 0.58% and 1.94% with respect to the maximum and minimum values of this variable in the stable state, ranging from ± 10.28 A to ± 13.93 A, for the inverter and rectifier modes, respectively. Similarly, the errors obtained for the variable v dc , in open loop, represent a variation of between 0.41% and 1.38% with respect to the average values that this variable reaches in stable state. In the case of closed loop experiments, the variable i a presents variations between 0.44% and 1.96%, the variable v dc presents variations between 0.19% and 0.22% and the variable P-between 0.4% and 0.88%; the average value of the variable Q in steady state oscillates the value of 0, so a relative error value was not calculated for it.
Given that the variation observed in the open loop is small, with a maximum error of 1.94%, it is concluded that the MGISE reproduces the behavior of the real system with acceptable fidelity. Conversely, even though the responses in closed loop differ to a greater extent compared to the responses in open loop, it is worth mentioning that the controller implemented in PSIM is a continuous controller, while the controller implemented for C-HIL platform validation is a discrete controller. Another important aspect is that in PSIM, both the controller and the MGIS operate simultaneously and synchronously, in the same simulation, so the PLL in PSIM will inherently present better results than in the embedded system. These two differences between the simulated controller in PSIM and the embedded controller influence the observed difference in the response of the controlled system. The HILP execution time is a feature to take into consideration in the difference between systems. A C-HIL simulation presents, generally, a time delay between acquisition and HILP signal generation, due to the hardware's propagation time. This time affects the total harmonic distortion, as discussed in [41]; nonetheless, the spectral analysis presented in the results section shows that the implemented platform integration time does not affect this variable significantly. In conclusion, the proposed platform demonstrates its usefulness in the validation of controllers for the management of power sharing between the MG and a DC µG.
The IT of the proposed platform is 6 µs; in the studies presented in Section 1, the ITs range between 10 ns and 2 ms, being more common order times of µs. Of the 16 ITs presented, 12 are in the range of 1 to 200 µs. In this respect, the proposed platform presents an IT similar to those reported in the literature, being even lower than those reported in [15][16][17][18][22][23][24][25]27,34,41]. Of these studies, [17,23,24,27,34] use technologies destined for the development of HIL applications; they have their own programming environments, with functional blocks that represent the total dynamics of some elements and dedicated hardware. Therefore, the platform proposed in this study offers an IT similar to, and even less than, the ITs generated with dedicated platforms but at a lower cost. In [39][40][41], C-HIL platforms similar to the proposal are presented. In comparison with [41], the IT obtained in this work is smaller. The discussed works in [39][40][41] use a higher cost hardware in comparison with the DB used for the development of the HILP depicted in this paper. Conversely, the results obtained in [39][40][41] are valid even if they are not compared with a simulation or a real system, supporting the proposed viability for controller validation because of the comparison against a simulation, with satisfactory results.
With the proposed structure for the C-HIL platform and the methodology described for its implementation, it is possible to validate different controllers and algorithms under multiple operating conditions. With the proposed platform, it is possible, for example, to modify the characteristic V-I curve of the PA, to vary the frequency and amplitude of the MG and to modify the value of the DC load. With the MGISE of the independently embedded controller and a communication interface through analog signals between them, a change in the nature of the controller does not affect the constitution of the MGISE. Additionally, through the MGISE front panel, the user can modify the load on the DC side, select whether or not there is power generation in the PA, select between open loop and closed loop operation modes, as well as define the modulation signal for operations in open loop. Finally, the programming environment that was used makes it possible to reproduce and modify the proposed platform easily and quickly compared to the use of hardware description languages.