A Potentiostat Readout Circuit with a Low-Noise and Mismatch-Tolerant Current Mirror Using Chopper Stabilization and Dynamic Element Matching for Electrochemical Sensors

: This paper presents a potentiostat readout circuit with low-noise and mismatch-tolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. Current-mode electrochemical sensors are widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian inﬂuenza virus (AIV). Low-noise and mismatch-tolerant characteristics are essential for sensing applications that require high reliability and high sensitivity. To achieve these characteristics, a proposed potentiostat readout circuit is implemented using the chopper stabilization scheme and the DEM technique. The proposed potentiostat readout circuit consists of a chopper-stabilized programmable gain transimpedance ampliﬁer (TIA), gain-boosted cascode current mirror, and a control ampliﬁer (CA). The chopper scheme, which is implemented in the TIA and CA, can reduce low frequency noise components, such as 1/f noise, and can obtain low-noise levels. The mismatch offsets of the cascode current mirror can be reduced by the DEM operation. The proposed current-mirror-based potentiostat readout circuit is designed using a standard 0.18 µ m CMOS process and can measure the sensor current from 350 nA to 2.8 µ A. The input-referred noise integrated from 0.1 Hz to 1 kHz is 21.7 pA RMS , and the power consumption was 287.9 µ W with a 1.8 V power supply.


Introduction
Current-mode electrochemical sensors have been widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian influenza virus (AIV) [1][2][3]. The early diagnosis of highly pathogenic viruses such as H5N1 AIV is significant for preventing their rapid spread. A currentmode sensing technique using an aptamer-based field-effect transistor with an extended gate was previously introduced to detect AIV [3]. In addition, blood glucose sensing based on the electrochemical current-mode sensors with a potentiostat biasing circuit was reported in [1,2].
A general sensing mechanism with a three-electrode potentiostat electrochemical current-mode sensor is shown in Figure 1a [4]. For electrochemical current-mode sensors for blood glucose sensing, the level of diabetes can be detected by sensing the current generated through various potential differences according to the change in the concentration of glucose [4,5].
Glucose or virus concentrations are generally measured using an amperometric electrochemical sensor. A three-electrode structure with a potentiostat consisting of a working electrode (WE), reference electrode (RE), and counter electrode (CE) can measure the current generated by the electrochemical reaction [6,7]. When we assume a very small voltage drop across the current meter, the voltage difference between the WE and RE can be kept Glucose or virus concentrations are generally measured using an amperometric electrochemical sensor. A three-electrode structure with a potentiostat consisting of a working electrode (WE), reference electrode (RE), and counter electrode (CE) can measure the current generated by the electrochemical reaction [6,7]. When we assume a very small voltage drop across the current meter, the voltage difference between the WE and RE can be kept constant by the feedback error amplifier [8]. The current generated by the electrochemical reaction flows from the CE to the WE, and this current is measured by the current meter. Therefore, the potentiostat sensor converts the solution concentration into a current. This characteristic of the sensor is suitable for bio-sensing applications such as blood glucose and virus analyses [9][10][11]. The conventional circuit of the current mirror based potentiostat readout circuit is shown in Figure 1b. The M0 and the control amplifier (CA) generate a feedback loop, and the VREF between WE and RE, which is VDD-VDAC, is stabilized. The current from the electrochemical sensor, ISEN, is copied by the current mirror, M1 and M2. In this architecture, however, the mismatch between the current mirror transistors due to the process variations and channel-length modulation deteriorates the sensing accuracy. Moreover, the 1/f noise components generated in M1 and M2 act as the main noise contributors. Therefore, designing a current mirror with low-noise [12,13] and mismatch-tolerant characteristics is critical [14,15].
In this study, a potentiostat sensing circuit with a low-noise and mismatch-tolerant current mirror is proposed. The chopper stabilization scheme and dynamic element matching (DEM) technique are integrated to reduce the low-frequency noise and mismatch in the current mirror. The gain-boosted cascode scheme is also applied to the current mirror to reduce the mismatch between the drain-source voltages (VDS) of the current mirror. The mirrored electrochemical current is converted to the output voltage by a lownoise chopper-stabilized transimpedance amplifier (TIA).
In previous studies [16,17], a different chopper frequency and DEM frequency are used, and this may introduce performance degradation due to the intermodulation distortion (IMD) between the chopper and DEM frequencies [18]. The low DEM frequency also requires the lower cut-off frequency of LPF, which consumes a large circuit area.
Because the square waveform has odd-harmonics, if the DEM clock and the chopper clock are operated at different frequencies, the interaction between these harmonics can generate IMD, which can degrade the signal quality. The conventional circuit of the current mirror based potentiostat readout circuit is shown in Figure 1b. The M 0 and the control amplifier (CA) generate a feedback loop, and the V REF between WE and RE, which is V DD -V DAC , is stabilized. The current from the electrochemical sensor, I SEN , is copied by the current mirror, M 1 and M 2 . In this architecture, however, the mismatch between the current mirror transistors due to the process variations and channel-length modulation deteriorates the sensing accuracy. Moreover, the 1/f noise components generated in M 1 and M 2 act as the main noise contributors. Therefore, designing a current mirror with low-noise [12,13] and mismatch-tolerant characteristics is critical [14,15].
In this study, a potentiostat sensing circuit with a low-noise and mismatch-tolerant current mirror is proposed. The chopper stabilization scheme and dynamic element matching (DEM) technique are integrated to reduce the low-frequency noise and mismatch in the current mirror. The gain-boosted cascode scheme is also applied to the current mirror to reduce the mismatch between the drain-source voltages (V DS ) of the current mirror. The mirrored electrochemical current is converted to the output voltage by a low-noise chopper-stabilized transimpedance amplifier (TIA).
In previous studies [16,17], a different chopper frequency and DEM frequency are used, and this may introduce performance degradation due to the intermodulation distortion (IMD) between the chopper and DEM frequencies [18]. The low DEM frequency also requires the lower cut-off frequency of LPF, which consumes a large circuit area.
Because the square waveform has odd-harmonics, if the DEM clock and the chopper clock are operated at different frequencies, the interaction between these harmonics can generate IMD, which can degrade the signal quality.
As a result, the proposed readout circuit used the same frequency for the chopper and the DEM, therefore minimizing the IMD between the chopper and DEM. Moreover, the relatively higher operating frequency of the chopper and the DEM can relax the area consumption of the LPF.
The remainder of the paper is organized as follows. Section 2 presents the circuit implementation of the proposed current-mirror-based potentiostat readout circuit. Section 3 presents the simulation results of the proposed readout circuit. Finally, Section 4 concludes the paper with a performance summary and comparison.

Proposed Current-Mirror-Based Potentiostat Readout Circuit
A block diagram of the proposed potentiostat readout circuit is shown in Figure 2. The proposed circuit consists of potentiostat biasing, current mirror, and TIA stages. In the potentiostat biasing stage, the voltage potential between the WE and RE is maintained by the feedback loop. In the current mirror stage, the current from the CE is copied by the low-noise and mismatch-tolerant current mirror. In the TIA stage, the current from the current mirror stage is converted to a voltage signal. This voltage signal can be converted to a digital code using an analog-to-digital converter (ADC).
As a result, the proposed readout circuit used the same frequency for the chopper and the DEM, therefore minimizing the IMD between the chopper and DEM. Moreover, the relatively higher operating frequency of the chopper and the DEM can relax the area consumption of the LPF.
The remainder of the paper is organized as follows. Section 2 presents the circuit implementation of the proposed current-mirror-based potentiostat readout circuit. Section 3 presents the simulation results of the proposed readout circuit. Finally, Section 4 concludes the paper with a performance summary and comparison.

Proposed Current-Mirror-Based Potentiostat Readout Circuit
A block diagram of the proposed potentiostat readout circuit is shown in Figure 2. The proposed circuit consists of potentiostat biasing, current mirror, and TIA stages. In the potentiostat biasing stage, the voltage potential between the WE and RE is maintained by the feedback loop. In the current mirror stage, the current from the CE is copied by the low-noise and mismatch-tolerant current mirror. In the TIA stage, the current from the current mirror stage is converted to a voltage signal. This voltage signal can be converted to a digital code using an analog-to-digital converter (ADC). The top architecture of the proposed current-mirror-based potentiostat readout circuit is shown in Figure 3. The input stage of the readout circuit consists of a sensor and CA. The CA generates a feedback loop with an M5. It maintains a constant VREF between RE and WE. The VREF is calculated as The current from the CE is mirrored by the gain-boosted cascode current mirror stage. The mirrored current is converted to the voltage through the TIA stage. Here, the transimpedance gain is programmable to adjust the gain. The low-pass filter (LPF) filters out the unwanted high-frequency components, and also acts as an antialiasing filter before a 12-bit successive approximation register (SAR) ADC. The internal operating parameters, including the clock timing, transimpedance gain, VB1 voltage, and chopper frequency are programmable, through a serial peripheral interface (SPI). (1) Appl. Sci. 2021, 11, x FOR PEER REVIEW 4 of 12 The architecture of the proposed current mirror is shown in Figure 4a. The current input, IIN, is mirrored to the output current, IOUT. To increase the output resistance of the current mirror and to reduce the number of errors due to the channel-length modulation, a gain-boosted cascode scheme is adopted. The W/L ratio between Ma and Mb determines the current ratio between IIN and IOUT. Thus, the mismatch derived from the process variation between Ma and Mb directly affects the accuracy of the current mirror. The IIN is converted to the gate voltage by the diode-connection between the drain of Mc and the gate of Ma, and the gate voltage is converted to the IOUT by the transconductance of Mb; thus, the flicker noises from Ma and Mb largely contribute to the overall noise. In addition, the flicker noise from the gain-boosting amplifier acts as the main noise contributor. In this The current from the CE is mirrored by the gain-boosted cascode current mirror stage. The mirrored current is converted to the voltage through the TIA stage. Here, the transimpedance gain is programmable to adjust the gain. The low-pass filter (LPF) filters out the unwanted high-frequency components, and also acts as an antialiasing filter before a 12-bit successive approximation register (SAR) ADC. The internal operating parameters, including the clock timing, transimpedance gain, V B1 voltage, and chopper frequency are programmable, through a serial peripheral interface (SPI).
The architecture of the proposed current mirror is shown in Figure 4a. The current input, I IN , is mirrored to the output current, I OUT . To increase the output resistance of the current mirror and to reduce the number of errors due to the channel-length modulation, a gain-boosted cascode scheme is adopted. The W/L ratio between M a and M b determines the current ratio between I IN and I OUT . Thus, the mismatch derived from the process variation between M a and M b directly affects the accuracy of the current mirror. The I IN is converted to the gate voltage by the diode-connection between the drain of M c and the gate of M a , and the gate voltage is converted to the I OUT by the transconductance of M b ; thus, the flicker noises from M a and M b largely contribute to the overall noise. In addition, the flicker noise from the gain-boosting amplifier acts as the main noise contributor. In this design, these mismatches and low-frequency noise components can be cancelled by the four-phase combinations of the chopper and DEM.    In Figure 4b, the current mirror is operated in four phases as a combination of three switching signals, CLK 1, CLK 2, and CLK S. The connections between the mirror transistors and amplifier are altered periodically as P 1 , P 2 , P 3 , and P 4 . The mismatches between the elements can be averaged out. In this current mirror, the chopper operation and dynamic element matching operation are merged into four phases. The low-frequency noise of the current mirror and amplifier are up-modulated by the chopper operation. The mismatch between the transistors in the current mirror and the amplifier is averaged, and thus a highly accurate current mirror operation with low noise is achieved.
The circuit configuration of the proposed current mirror as the phases of the combined chopper and DEM operations are illustrated in Figure 5. At the point of the connection around M 3 , in Phase 1, the source of M 3 is connected to the drain of M 2 , and the gate of M 3 is connected to the negative output of the amplifier. In Phase 2, the source of M 3 remains connected to the drain of M 2 ; however, the gate of M 3 is connected to the positive output of the amplifier. In Phase 3, the source of M 3 is connected to the drain of M 1 , and the gate of the M 3 is connected to the positive output of the amplifier. In Phase 4, the source of M 3 is connected to the drain of M 1 , and the gate of M 3 is connected to the negative output of the amplifier. Using these four-phase combinations of the chopper and DEM techniques, the mismatches and the low-frequency noise components can be averaged out.   Figure 6 shows the single-ended chopper operational amplifiers used in the implementation of the CA and the TIA. The amplifier adopts complementary input stages of the PMOS and NMOS differential pairs for the rail-to-rail input common-mode range. The intermediate stage is implemented using a folded-cascode topology with class-AB biasing, and the output stage is implemented in class-AB. The choppers in front of both the input stage and common-gate stages are implemented, as shown in Figure 6. The individual switch in the chopper is implemented using the CMOS transmission gate, and the chopping frequency of this circuit is 125 kHz having non-overlapping clock. Non-overlapping clock have 10 ns duration.
The chopper amplifier modulates the input signal to the high chopping frequency band to avoid the low-frequency flicker noise. The modulated signal is amplified and de-    Figure 7 shows the fully differential amplifier used for gain boosting of the current mirror. A general two-stage folded-cascode Miller-compensated topology with common mode feedback (CMFB) is adopted. In this gain-boosted current mirror, because the input common mode level is low (approximately 100-200 mV), and the PMOS input stage is exploited, two source followers are added to the CMFB circuit to reduce the resistive load- The chopper amplifier modulates the input signal to the high chopping frequency band to avoid the low-frequency flicker noise. The modulated signal is amplified and demodulated to the baseband using an output chopper. Here, the offset and the low-frequency noise are up-modulated by the output chopper, and is attenuated by the following LPF. Thus, a thermal-noise-limited signal-to-noise ratio (SNR) can be achieved using the chopper operation. Figure 7 shows the fully differential amplifier used for gain boosting of the current mirror. A general two-stage folded-cascode Miller-compensated topology with common mode feedback (CMFB) is adopted. In this gain-boosted current mirror, because the input common mode level is low (approximately 100-200 mV), and the PMOS input stage is exploited, two source followers are added to the CMFB circuit to reduce the resistive loading for common mode detection.  Figure 7 shows the fully differential amplifier used for gain boosting of the current mirror. A general two-stage folded-cascode Miller-compensated topology with common mode feedback (CMFB) is adopted. In this gain-boosted current mirror, because the input common mode level is low (approximately 100-200 mV), and the PMOS input stage is exploited, two source followers are added to the CMFB circuit to reduce the resistive loading for common mode detection. Figure 7. Schematic of the fully-differential amplifier.

Results and Discussions
A three-port electrochemical sensor was modeled using a voltage controlled resistor, as shown in Figure 8 [19][20][21]. The resistance between the RE and CE is modeled as a constant resistor at 10 kΩ. The typical voltage difference between the WE and RE was set to be 700 mV. In this circuit, the WE was forced by the VDD supply (1.8 V). The RE is typically indirectly biased to 1.1 V by the virtual short between the feedback amplifier input nodes. The current change due to the electrochemical reaction is modeled using a voltage- Figure 7. Schematic of the fully-differential amplifier.

Results and Discussions
A three-port electrochemical sensor was modeled using a voltage controlled resistor, as shown in Figure 8 [19][20][21]. The resistance between the RE and CE is modeled as a constant resistor at 10 kΩ. The typical voltage difference between the WE and RE was set to be 700 mV. In this circuit, the WE was forced by the VDD supply (1.8 V). The RE is typically indirectly biased to 1.1 V by the virtual short between the feedback amplifier input nodes. The current change due to the electrochemical reaction is modeled using a voltage-controlled resistor, which varies from 250 to 2250 kΩ, and is implemented using Verilog-A. Since the chip is under fabricate, post layout simulation was performed using parasitic extraction (PEX).
Appl. Sci. 2021, 11, x FOR PEER REVIEW 7 of 12 controlled resistor, which varies from 250 to 2250 kΩ, and is implemented using Verilog-A. Since the chip is under fabricate, post layout simulation was performed using parasitic extraction (PEX).  Figure 9 shows the layout of the circuit. The circuit was implemented using a 0.18um CMOS process with an active area of 1.073 mm 2 . The overall current consumption was 287.9 μW.  Figure 9 shows the layout of the circuit. The circuit was implemented using a 0.18-um CMOS process with an active area of 1.073 mm 2 . The overall current consumption was 287.9 µW.  Figure 8. Configuration of the equivalent sensor model using a voltage-controlled resistor. Figure 9 shows the layout of the circuit. The circuit was implemented using a 0.18um CMOS process with an active area of 1.073 mm 2 . The overall current consumption was 287.9 μW.  Figure 10a shows the input-output characteristics of the proposed current mirror between the input current (ISEN.IN) and output current (ISEN.OUT). The maximum error from 0 to 4.5 μA for the input current is 1.129%FSO (full scale output). Figure 10b shows the transimpedance of the TIA was simulated to be 300 kΩ with a maximum nonlinearity of 0.793% in the current range of 3.83 μA.     Figure 9 shows the layout of the circuit. The circuit was implemented using a 0.18um CMOS process with an active area of 1.073 mm 2 . The overall current consumption was 287.9 μW.  Figure 10a shows the input-output characteristics of the proposed current mirror between the input current (ISEN.IN) and output current (ISEN.OUT). The maximum error from 0 to 4.5 μA for the input current is 1.129%FSO (full scale output). Figure 10b shows the transimpedance of the TIA was simulated to be 300 kΩ with a maximum nonlinearity of 0.793% in the current range of 3.83 μA.   Figure 10b shows the transimpedance of the TIA was simulated to be 300 kΩ with a maximum nonlinearity of 0.793% in the current range of 3.83 µA. Figure 11 shows the transient simulation results of the proposed potentiostat readout circuit. The resistance between the WE and RE varied from 250 to 2250 kΩ, and the V BIAS was set to 500 mV. The transimpedance of the TIA was set to 300 kΩ and feedback capacitance of 10 pF. Because the output current is inversely proportional to the sinusoidal input resistance change of the electrochemical sensor, the red line (I SEN ) and blue line (V OUT ) have the waveform shapes of 1/[1 + sin (x)].
Appl. Sci. 2021, 11, x FOR PEER REVIEW 8 of 12 Figure 11 shows the transient simulation results of the proposed potentiostat readout circuit. The resistance between the WE and RE varied from 250 to 2250 kΩ, and the VBIAS was set to 500 mV. The transimpedance of the TIA was set to 300 kΩ and feedback capacitance of 10 pF. Because the output current is inversely proportional to the sinusoidal input resistance change of the electrochemical sensor, the red line (ISEN) and blue line (VOUT) have the waveform shapes of 1/[1+sin (x)].      The input referred noise simulation results are shown in Figure 13. The input referred current noise at 1 Hz is reduced from 13.2775 pA/ √ Hz to 936 fA/ √ Hz by the chopper operation. The input-referred noise density and the integrated input-referred noise from 0.1 Hz to 1 kHz are 21.7 pA RMS , respectively.
Appl. Sci. 2021, 11, x FOR PEER REVIEW 9 of 12 The input referred noise simulation results are shown in Figure 13. The input referred current noise at 1 Hz is reduced from 13.2775 pA/√Hz to 936 fA/√Hz by the chopper operation. The input-referred noise density and the integrated input-referred noise from 0.1 Hz to 1 kHz are 21.7 pARMS, respectively.  Table 1 shows noise contributors of readout circuit. When the chopper is disabled, the flicker noise components in the current mirror, M1,2, form about 72% of the total noise. When the chopper is enabled, the main contributors are changed to the thermal noise of M1,2.

Transistor
Noise Source Total Noise Total Noise Figure 13. Input-referred noise simulation results of the readout circuit. Table 1 shows noise contributors of readout circuit. When the chopper is disabled, the flicker noise components in the current mirror, M 1,2 , form about 72% of the total noise. When the chopper is enabled, the main contributors are changed to the thermal noise of M 1,2 .  Figure 14 show the Monte-Carlo simulation results with N = 200. The input current, V BIAS and R f , were fixed to 1 µA, 500 mV, and 300 kΩ, respectively. The desired nominal output of the TIA was 800 mV. In the simulation, the standard deviation of the TIA output was reduced from 2.49 to 0.12 mV by the DEM operation in Figure 14d.   As shown in Figure 14b,c, the standard deviation of the TIA output was 0.75 to 0.68 mV. The different chopper frequency and DEM frequency were used, and this may introduce performance degradation due to the IDM between the chopper and DEM frequencies. In Figure 14d, the same frequency for the chopper and the DEM is used, thus IMD between the chopper and DEM can be minimized. Table 2 summarizes the performances of the proposed potentiostat readout circuit with those of previous studies [4,16,17,[22][23][24]. The simulation results of this circuit achieve the wide input range, low noise, and mismatch-tolerant characteristics.

Conclusions
This paper proposes a potentiostat readout circuit with a low-noise and mismatchtolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. The potentiostat electrochemical current-mode sensors convert potential differences into current signals according to the concentration of the solution, and the readout circuit converts current signals into voltage signals.
The proposed potentiostat readout circuit consists of a potentiostat biasing stage using CA, a gain-boosted cascode current mirror, TIA, I/V reference, SPI, oscillator, and a timing generator. In order to detect small changes in current, the proposed readout circuit with mismatch-tolerant and low-noise characteristics is essential. For this purpose, a chopper was adopted for the input and output stages of the CA, current mirror, and TIA. The DEM technique was applied to make it mismatch-tolerant. Thus, the clock generator for chopping, along with the DEM and an SPI for communication to the digital circuits, were integrated into a single chip.
The proposed readout circuit was under fabricate by implementing a 0.18-µm CMOS process with an active area of 1.073 mm 2 . It consumed 287.9 µW of power at a 1.8 V supply voltage. The input-referred current noise was reduced to 936 fA/ √ Hz at 1 Hz, and the input-referred noise from 0.1 Hz to 1 kHz was 21.7 pA RMS . The input current range was in the range of 100 nA to 3.83 µA (maximum nonlinearity < 1%). The standard deviation of the TIA output was reduced from 2.49 mV to 0.12 mV by the DEM operation. These results suggest that the readout circuit proposed in this paper is suitable as an electrochemical sensor using a potentiostat.