Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

: Accurate circuit simulation reﬂecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based ﬂexible electronics. In particular, appropriate modeling of threshold voltage ( V T ) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al 2 O 3 gate insulator on a polyethylene terephthalate (PET) substrate. Speciﬁcally, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of ﬂexible IGZO circuits. Future studies with various operating conditions, such as different duty, voltage, and toggle numbers, will bring more accurate predictions of the ﬂexible IGZO circuit operation. Author Contributions: Conceptualization, J.-H.K., Y.S., D.-W.P. and D.H.K.; methodology, J.-H.K., Y.S.; validation, J.-H.K., Y.S., J.T.J., S.P., D.K., J.P., M.H. and C.K.; writing—original draft preparation, J.-H.K., Y.S., D.-W.P. and D.H.K.; writing—review and editing, J.-H.K., Y.S., D.-W.P. and D.H.K.; supervision, D.-W.P. and D.H.K.; project administration, D.-W.P. and D.H.K.; funding acquisition, M.H., C.K., D.-W.P. and D.H.K. All authors have read and agreed to the published version of the manuscript.


Introduction
Recently, amorphous indium gallium zinc oxide (a-IGZO) has drawn much attention as an active channel material for thin-film transistors (TFTs) because of its relatively high mobility, low off-current, high I on /I off ratio, and low-temperature process [1][2][3][4][5]. In particular, IGZO TFTs can be fabricated on a flexible substrate, such as polyethylene terephthalate (PET) and polyimide (PI), through a low-temperature process, and they have been applied to rollable and foldable electronics [6][7][8]. However, the inherent performance degradation caused by bending conditions and bias stress is problematic in flexible IGZO systems. Therefore, a systemic study about the effect of mechanical and electrical stress on long-term reliability should be performed at both device and circuit levels. It is necessary to predict the circuit operation in alternating current (AC) driving conditions through simulations that reflect analysis results. Until now, there has been much research on direct current (DC) stress [9][10][11][12][13][14][15][16][17], even though most circuits are driven in AC conditions. Hence, it is very important to analyze the instability characteristics of IGZO devices and circuits in various AC conditions so that compact modeling can be drawn for the reliability-aware SPICE (Simulation Program with Integrated Circuit Emphasis) simulation.
Generally, a positive gate bias stress (+V G ) on IGZO TFTs results in a positive shift of threshold voltage (V T ). This is due to electron-trapping inside the gate insulator and on the interface trap. However, when the gate insulator is aluminum oxide (Al 2 O 3 ) deposited 2 of 10 by atomic layer deposition (ALD) at low temperatures, in addition to electron-trapping that generates positive ∆V T , there is also a hydrogen migration mechanism that generates negative ∆V T [18][19][20][21][22][23]. Cho et al. investigated the static and dynamic bias stress-induced charge trapping and de-trapping in IGZO TFTs [18]. On et al. examined the impact of channel length on the performance of IGZO TFTs with self-aligned structures [19]. Although these studies investigated the mechanism of V T shift in various conditions, the studies were performed at the transistor level, which has a limitation in circuit-level AC simulation.
In this paper, we analyzed the performance of IGZO TFTs and inverters based on the aforementioned degradation mechanisms, while mechanical stress (bending) and electrical stress (AC stress) were applied simultaneously. The NMOS-only inverters were fabricated on a flexible PET substrate consisting of a low-temperature processed a-IGZO and an ALD Al 2 O 3 gate insulator. The electrical stress and recovery on the driver and load transistor of the inverters were analyzed under AC bias conditions. Multiple bending tests were also performed for the mechanical stress test. Parameters such as τ(V), β, and ∆V T0 (V) were obtained by applying the stretched exponential function (SEF) to the instability characteristics that appeared in each stress condition [24,25]. These parameters were loaded into HSPICE so that the simulation could reflect the ∆V T in real-time, while AC bias was applied. This work can be a useful approach for a reliability-aware simulation of flexible IGZO circuits, enabling a circuit operation prediction based on compact modeling.

Fabrication and Measurement
In this study, a-IGZO was processed on a flexible PET substrate by taking advantage of its low-temperature process. The 3-dimensional (3D) structure and circuit diagram of the NMOS-only inverter are shown in Figure 1a,b. Copper (Cu) gate metal with a thickness of 20 nm was deposited using an electron-beam (e-beam) evaporator. The 40 nm Al 2 O 3 gate insulator was deposited using an ALD system at 80 • C. In detail, an ALD Al 2 O 3 film was formed using Al(CH 3 ) 3 (trimethylaluminum; TMA) and H 2 O. Generally, a positive gate bias stress (+VG) on IGZO TFTs results in a positive shift of threshold voltage (Vt). This is due to electron-trapping inside the gate insulator and on the interface trap. However, when the gate insulator is aluminum oxide (Al2O3) deposited by atomic layer deposition (ALD) at low temperatures, in addition to electron-trapping that generates positive ΔVT, there is also a hydrogen migration mechanism that generates negative ΔVT [18,19,20,21,22,23]. Cho et al. investigated the static and dynamic bias stressinduced charge trapping and de-trapping in IGZO TFTs [18]. On et al. examined the impact of channel length on the performance of IGZO TFTs with self-aligned structures [19]. Although these studies investigated the mechanism of Vt shift in various conditions, the studies were performed at the transistor level, which has a limitation in circuit-level AC simulation.
In this paper, we analyzed the performance of IGZO TFTs and inverters based on the aforementioned degradation mechanisms, while mechanical stress (bending) and electrical stress (AC stress) were applied simultaneously. The NMOS-only inverters were fabricated on a flexible PET substrate consisting of a low-temperature processed a-IGZO and an ALD Al2O3 gate insulator. The electrical stress and recovery on the driver and load transistor of the inverters were analyzed under AC bias conditions. Multiple bending tests were also performed for the mechanical stress test. Parameters such as τ(V), β, and ΔVT0(V) were obtained by applying the stretched exponential function (SEF) to the instability characteristics that appeared in each stress condition [24,25]. These parameters were loaded into HSPICE so that the simulation could reflect the ΔVT in real-time, while AC bias was applied. This work can be a useful approach for a reliability-aware simulation of flexible IGZO circuits, enabling a circuit operation prediction based on compact modeling.

Fabrication and Measurement
In this study, a-IGZO was processed on a flexible PET substrate by taking advantage of its low-temperature process. The 3-dimensional (3D) structure and circuit diagram of the NMOS-only inverter are shown in Figure 1a,b. Copper (Cu) gate metal with a thickness of 20 nm was deposited using an electron-beam (e-beam) evaporator. The 40 nm Al2O3 gate insulator was deposited using an ALD system at 80 °C. In detail, an ALD Al2O3 film was formed using Al(CH3)3 (trimethylaluminum; TMA) and H2O.  Thereafter, a target with the ratio of In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 mol% was radio frequency (RF) sputtered to form a 35 nm IGZO channel under the condition of Ar:O 2 = 3:0.1 sccm. Source and drain electrodes (40 nm Cu) were also deposited using an e-beam evaporator. The gate insulator was wet-etched using buffer oxide etchant (BOE) for metal interconnection, followed by a metallization performed with 60 nm Cu to connect the inverter circuit. A top view of the fabricated device for which inverter manufacturing has been completed is shown in Figure 1c.
The mechanical stress to the IGZO inverters was applied with a bending radius of 10 mm, and the electrical stress was tested by applying DC/AC stress to V GS and V DS using Keithley 4200. The schematics of the bending test, bending tool, and bending measurement of the fabricated flexible device are shown in Figure 1d. It should be noted that some local surfaces with small dimensions might experience negligible bending stress.

Analysis Process
The analysis process for the inverter simulation is shown in Figure 2. The load and driving transistors will be under electrical stress depending on the driving condition of the device. The two types of electrical stress that can be applied to each transistor (Figure 2a) are current stress (CS) and positive bias stress (PBS). The electrical stress will affect V T , and the V T change will result in the voltage transfer curve (VTC) of the inverter. In general, when the gate insulator is composed of SiO 2 , the cause of the positive V T shift due to the PBS condition can be explained by electron trapping (Figure 2b,c) [24][25][26][27]. However, when Al 2 O 3 is deposited by low-temperature ALD, the AlO-H bonding tends to have weak bonding that can lead to a negative V T shift. This is known as a hydrogen migration phenomenon as a result of the movement of H + ions (Figure 2b,c) [18][19][20][21][22][23]. The movement of electrons and hydrogens when the positive voltage is applied to the gate electrode is represented in Figure 2b.
The mechanical stress to the IGZO inverters was applied with a bending radius of 10 mm, and the electrical stress was tested by applying DC/AC stress to VGS and VDS using Keithley 4200. The schematics of the bending test, bending tool, and bending measurement of the fabricated flexible device are shown in Figure 1d. It should be noted that some local surfaces with small dimensions might experience negligible bending stress.

Analysis Process
The analysis process for the inverter simulation is shown in Figure 2. The load and driving transistors will be under electrical stress depending on the driving condition of the device. The two types of electrical stress that can be applied to each transistor ( Figure  2a) are current stress (CS) and positive bias stress (PBS). The electrical stress will affect VT, and the VT change will result in the voltage transfer curve (VTC) of the inverter. In general, when the gate insulator is composed of SiO2, the cause of the positive VT shift due to the PBS condition can be explained by electron trapping (Figure 2b,c) [24,25,26,27]. However, when Al2O3 is deposited by low-temperature ALD, the AlO-H bonding tends to have weak bonding that can lead to a negative VT shift. This is known as a hydrogen migration phenomenon as a result of the movement of H + ions (Figure 2b,c) [18,19,20,21,22,23]. The movement of electrons and hydrogens when the positive voltage is applied to the gate electrode is represented in Figure 2b.
In this experiment, the effects of electrical stress were measured and analyzed in accordance with the physical states of flat and bending conditions. The results showed that negative and positive shifts of VT were mixed because of the aforementioned electron trapping and hydrogen migration phenomena. In particular, in the case of AC driving, where the stress/recovery situation is repeated, the parameters ΔVT and τ were extracted using the SEF Equation (1). The compact model was mounted on HSPICE, and the load/driver transistors for AC simulation and its consistency were verified for the change of VT, as shown in Figure 2d. In this experiment, the effects of electrical stress were measured and analyzed in accordance with the physical states of flat and bending conditions. The results showed that negative and positive shifts of V T were mixed because of the aforementioned electron trapping and hydrogen migration phenomena. In particular, in the case of AC driving, where the stress/recovery situation is repeated, the parameters ∆V T and τ were extracted using the SEF Equation (1). The compact model was mounted on HSPICE, and the load/driver transistors for AC simulation and its consistency were verified for the change of V T , as shown in Figure 2d.

SPICE Compatible Compact Modeling
To analyze the reliability of the inverter operation, compact modeling of the load/driver transistors during the DC and AC bias should be studied. From the inverter schematic in Figure 2a, it is known that the CS condition dominates for the load transistor in which V GS and V DS are simultaneously applied, while the PBS condition dominates for the driver transistor. To implement experimentally the CS/PBS stress and recovery conditions, the change of the transfer curve was observed for up to 1800 s in each case. The width (W) and length (L) of the load transistor were designed as W/L = 5/50 µm and of the driver transistor were designed as W/L = 50/5 µm. Additionally, different V GS and V DS bias conditions ranging from 4 V to 8 V were applied to see the change of device characteristics in accordance with the applied voltage. The transfer curve change over time when 4 V and 7 V of V GS and V DS were applied (i.e., CS condition) to the load transistor in a flat state is shown in Figure 3a,b, respectively. The threshold voltage shift (∆V T ) depending on the stress and recovery time is summarized in Figure 3c. Meanwhile, the transfer curve changes and the summarized ∆V T when the load transistor was in a bending condition are shown in Figure 3d-f. AC inverter simulation based on a compact model of ΔVT in load and driver transistors.

SPICE Compatible Compact Modeling
To analyze the reliability of the inverter operation, compact modeling of the load/driver transistors during the DC and AC bias should be studied. From the inverter schematic in Figure 2a, it is known that the CS condition dominates for the load transistor in which VGS and VDS are simultaneously applied, while the PBS condition dominates for the driver transistor. To implement experimentally the CS/PBS stress and recovery conditions, the change of the transfer curve was observed for up to 1800 s in each case. The width (W) and length (L) of the load transistor were designed as W/L = 5/50 μm and of the driver transistor were designed as W/L = 50/5 μm. Additionally, different VGS and VDS bias conditions ranging from 4 V to 8 V were applied to see the change of device characteristics in accordance with the applied voltage. The transfer curve change over time when 4 V and 7 V of VGS and VDS were applied (i.e., CS condition) to the load transistor in a flat state is shown in Figure 3a,b, respectively. The threshold voltage shift (ΔVT) depending on the stress and recovery time is summarized in Figure 3c. Meanwhile, the transfer curve changes and the summarized ΔVT when the load transistor was in a bending condition are shown in Figure 3d-f. From the measurement results, it can be seen that a positive ∆V T and a negative ∆V T were mixed under stress and recovery conditions, and the trend changed for various voltages. In general, when electron trapping occurs in the gate insulator, a positive ∆V T occurs because more gate bias is required for the same channel charge, and the opposite phenomenon occurs when de-trapping takes place. As mentioned above and in other studies [18][19][20][21][22][23], the hydrogen migration takes place opposite to the electron trapping by H + Appl. Sci. 2021, 11, 4838 5 of 10 cations, which results in a negative ∆V T for the hydrogen migration and a positive ∆V T for the recovery of hydrogen migration. For the flat load transistors, as shown in Figure 3c, the largest positive ∆V T was observed in low-voltage stress, which is attributed to the dominant electron trapping. In the recovery condition, the total amount of charge contributed by the recovery of hydrogen migration is dominant, which results in a positive ∆V T . The measurement results in the bending condition were similar, as shown in Figure 3d-f. The larger ∆V T range is attributed to the increased oxygen vacancy during the tensile stress along the channel direction, which can increase the hydrogen migration [28,29].
The ∆V T over time for the driver transistors in the PBS stress/recovery conditions is shown in Figure 4. The biggest difference from the result of the load transistor in Figure 3 is that, because there is no drain bias, electrons and hydrogens move only with gate bias. This could enhance the effect of V GS bias throughout the entire channel region. The driver transistors in the flat state are shown in Figure 4a-c, while those for the bending condition are shown in Figure 4d-f. Overall, the negative ∆V T component increased, which is attributed to the larger hydrogen migration effect caused by greater charge movement throughout the channel.
From the measurement results, it can be seen that a positive ΔVT and a negative ΔVT were mixed under stress and recovery conditions, and the trend changed for various voltages. In general, when electron trapping occurs in the gate insulator, a positive ΔVT occurs because more gate bias is required for the same channel charge, and the opposite phenomenon occurs when de-trapping takes place. As mentioned above and in other studies [18,19,20,21,22,23], the hydrogen migration takes place opposite to the electron trapping by H + cations, which results in a negative ΔVT for the hydrogen migration and a positive ΔVT for the recovery of hydrogen migration. For the flat load transistors, as shown in Figure 3c, the largest positive ΔVT was observed in low-voltage stress, which is attributed to the dominant electron trapping. In the recovery condition, the total amount of charge contributed by the recovery of hydrogen migration is dominant, which results in a positive ΔVT. The measurement results in the bending condition were similar, as shown in Figure 3d-f. The larger ΔVT range is attributed to the increased oxygen vacancy during the tensile stress along the channel direction, which can increase the hydrogen migration [28,29].
The ΔVT over time for the driver transistors in the PBS stress/recovery conditions is shown in Figure 4. The biggest difference from the result of the load transistor in Figure 3 is that, because there is no drain bias, electrons and hydrogens move only with gate bias. This could enhance the effect of VGS bias throughout the entire channel region. The driver transistors in the flat state are shown in Figure 4a   As shown above, the physical and electrical stresses can cause various ∆V T trends, which could affect the operation of the complex circuit. Therefore, based on the DC characteristics of a single device and its appropriate modeling, the V T instability of the load and driver transistors was predicted for an accurate transient simulation. In detail, the beta (β) and tau (τ) were extracted using the measured ∆V T and Equation (1). A more detailed SEF model is presented in the below Equation (2), which reflects both negative and positive ∆V T cases.
The extracted ∆V T0 and τ for various conditions are shown in Figure 5. The τ, ∆V T0 , and β functions for every physical and electrical stress condition are summarized in Table 1.
Reflecting the repeated stress/recovery in AC bias, a real-time ∆V T was successfully applied in the inverter simulation. In detail, each function presented in Table 1 was entered into the V T parameters in the analytical I-V model of Verilog-A [30]. After configuring an IGZO NMOS-only inverter in HSPICE, the SEF model and the extracted parameters were used for both device simulation and transient AC simulation.    2.2 × 10 1 e ( Vov

Inverter AC Driving Simulation
Inverter AC driving simulation was performed by applying the DC stress-based positive and negative SEF model. The detailed AC driving condition was as follows: 3 V to 7 V range of V OV = (V in − V T ), a duty of 50%, cycle of 10 ms or 20 ms, and toggle number of up to 10,000 times. The measured values and simulation results when V OV was 3 V or 5 V in a flat inverter are shown in Figure 7a-d. Similarly, the measured values and simulation results when Vov was 3 V or 7 V under the bending condition are shown in Figure 7e-h. In this simulation, the initial curve was matched with the measurement data, followed by a long-term simulation of 10,000-toggle. The degree of device/circuit deterioration is relatively small in AC driving because the bias time under which the device is stressed is 50% shorter, as compared with DC bias. It can be seen that the proposed compact modeling reflected the inverter's physical and electrical stress effects well, as the matching degree between the measured value and the simulation result was high. We expect that the proposed reliability-aware SPICE simulation will help predict the circuit operation of flexible a-IGZO TFTs.

Conclusions
In this study, both DC and AC bias-induced instability characteristics of flexible a-IGZO transistors and inverters were analyzed under electrical and mechanical stress. In particular, the electron trapping and hydrogen migration mechanisms that can occur in the IGZO transistors were analyzed and modeled under PBS/CS stress conditions. In this compact modeling, simulation parameters were extracted from both positive and negative ∆V T by applying the SEF model. When performing DC and AC simulation by loading the extracted parameter in HSPICE, real-time dependent ∆V T was successfully reflected, showing a high consistency of measurement values and simulation results.
The proposed method enables a reliability-aware circuit simulation so that the operation of the flexible IGZO transistor and circuit can be predicted with high accuracy.
Future studies with various operating conditions, such as different duty, voltage, and toggle numbers, will bring more accurate predictions of the flexible IGZO circuit operation.

Data Availability Statement:
The raw/processed data required to reproduce these findings will be shared upon request from the corresponding author.