Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET

: In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless ﬁeld-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor ﬁeld-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric ( T ILD ) and gate channel length ( L g ) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as T ILD decreases and they increase as L g increases, and thus there is a strong coupling in M3INV at the range of T ILD ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same T ILD and L g . The switching threshold voltage ( V m ) and noise margins ( NM s) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the V m variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of V m , respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL. Author Contributions: Conceptualization, T.J.A. Y.S.Y.; methodology, T.J.A. Y.S.Y.; investi-gation, T.J.A. Y.S.Y.; data curation, T.J.A.; writing—original draft preparation, T.J.A.; writing— review editing, T.J.A. and Y.S.Y.; supervision, Y.S.Y.; project administration, Y.S.Y.; funding acquisition, Y.S.Y.


Introduction
Since metal-oxide-semiconductor field-effect transistors (MOSFETs) were developed, the performance of semiconductor integrated circuits has been steadily developed in accordance with Moore's Law [1]. Semiconductor devices with the gate length of less than 10 nm, which are core technologies required for the 4th industrial revolution such as artificial intelligence (AI), internet of thing (IOT), cloud computing, big data, and virtual reality [2], have been developing. As the process technology advances by scalingdown, the physical limitations of silicon-based semiconductor processes and the increased integration have led to the problems in thermal budget, delay, and power consumption [3]. In order to solve such problems, various types of researches related on developments of semiconductor materials, process technology, and devices have been actively carried out [4]. The monolithic 3-dimensional (3D) integrated-circuit (M3IC), which vertically stacks each tier on a previously fabricated tier, is one of the promising techniques to break the physical limits [5,6]. This technology is more advantageous in density, delay, and cost because of the smaller length of the Via than the existing parallel integration which makes devices on each wafer and connects them with through-silicon via (TSV) between wafers [7]. This is one of the main problems with M3IC which has the reduction the thermal budget of the MOSFETs in the 2nd and subsequent tiers on the M3DIC [8,9]. MOSFET and junctionless field-effect transistor (JLFET) have opposite operating principles. The MOSFET controls the current through depletion and inversion, and the JLFET controls the current with or without depletion. MOSFET has different source/drain and channel doping types (n/p), whereas JLFET use one doping type for source/drain and channel. Therefore, JLFET is advantageous in terms of thermal budget because the dopant activation process of the MOSFET is unnecessary. The thermal budget of upper tier is constrained by maximum thermal budget of the lower tier or tiers. JLFET has little effect of short channel effect, which is a major problem in MOSFET, and shows good performance in terms of carrier mobility. In order to solve the thermal budget problem, enhance the immunity of mobility degradation, and possess the simplicity of fabrication, JLFET [10,11] on M3IC has been proposed as the replacement of MOSFET [12].
M3IC technology stacking field-programmable gate-array (FPGA) logics and sensor devices have been reported, but the M3IC consisted of stacked MOSFETs and its thickness of interlayer dielectric (ILD), T ILD , between vertically stacked devices was over 100 nm so that there are no electrical coupling between stacking devices [9]. Recently, a study considering the electrical coupling between stacked devices has been performed when the ILD in monolithic 3D inverter (M3INV) consisting of MOSFETs is very thin (i.e., T ILD < 50 nm) [13,14]. Interlayer coupling in monolithic 3D static random access memory (M3SRAM) stacked vertically with tunnel field-effect transistor (TFET) and MOSFET has been investigated in terms of stability and performance [15]. However, no research has been reported on the electrical coupling between the upper and lower devices of the M3IC consisting of JLFET [16] which can replace the MOSFETs.
Therefore, it is necessary to investigate the electrical interaction between devices in M3IC stacked with the next generation devices. In this paper, we will introduce the electrical coupling in terms of thickness variation of ILD in M3INV stacked vertically with JLFETs, compared with one with MOSFETs. The structures and simulation method of the M3INV with MOSFETs or JLFETs will be introduced (Section 2), and the electrical coupling of upper device at different gate voltage of lower devices, simulated with the DC/AC device parameter, will be investigated (Section 3). In Section 4, electrical characteristics of two types of M3INV (MOSFETs and JLFETs) will be explained. Finally, Section 5 concludes. Figure 1 shows two types of M3INV structures used in the simulation. The M3INV consists of N-type and P-type transistors in the upper and lower tiers, respectively. Figure 1a,b are schematics of M3INV consisting of MOSFET (M3INV-MOS) [5] and JLFET (M3INV-JL) [12], respectively. The doping concentrations of source/drain, LDD, and channel in MOSINV-MOS are 10 21 , 10 18 , and 10 15 cm −3 , respectively [13,14]. The doping concentrations of source/drain and channel of M3INV-JL is 10 20 and 10 19 cm −3 , respectively [12]. The detailed parameters in both M3INV-MOS and M3INV-JL are shown in Table 1. Three types of structures for both M3INV-MOS and M3INV-JL are simulated: gate lengths/gate oxide thicknesses are 20/0.9 nm, 30/1 nm, and 50/1.1 nm, respectively [14]. SiO 2 was used for the regions in gate oxide, ILD, and bulk oxide (Box). Figure 1c shows the equivalent circuit of M3INV-MOS and M3DINV-JL. Silvaco's technology computer-aided-design (TCAD) simulator ATLAS [17] was used in this simulation. The models used in the simulation are CVT, SRH, AUGER, and FERMI. The leakage currents of both MOSFET and JLFET in each M3INV were set equal to 10 −8 A, in order to simulate the inverter characteristics with same leakage current condition. The V th variation, g m variation, C ngng variation, V m , and noise margin of both M3INV-MOS and M3INV-JL were compared through TCAD simulation.

Structure and Simulation Method
Threshold voltage * of the top transistor V * The threshold voltage V th is defined as V ngs when I nds = 10 −7 A.

DC/AC Characteristics
where Xbar means the distance between the front SiO2/Si interface and barycenter location of charge in the silicon channel [22]   respectively, and the squares, circles, and triangles denote those at L G = 20, 30, and 50 nm, respectively. As T ILD decreases, ∆V th , ∆V gm , and ∆V Cngng increases at both M3INV-MOS and M3INV-JL. When T ILD is over 30 nm, ∆V th , ∆V gm , and ∆V Cngng are below 50 mV, the coupling between stacked transistors in both M3INV-MOS [14] and M3INV-JL can be ignored. As L G increases in both M3INV-MOS and M3INV-JL, ∆V th , ∆V gm , and ∆V Cngng increase. ∆V th , ∆V gm , and ∆V Cngn of M3INV-JL has larger than those of M3INV-MOS as T ILD decreases, and the average variations of ∆V th and ∆V gm in M3INV-JL are smaller than those in M3INV-MOS as L G increases, but the variation of ∆V Cngng does not depend on L G at both M3INV-MOS and M3INV-JL. As the channel length decreases, PN + junction in M3DINV-MOS makes the effective channel length decrease, resulting in short-channel effects (SCEs), but the junctionless in M3DINV-JL can make the SCEs decrease [18][19][20]. Because JLFET is more immune than MOSFET with PN junction in terms of SCE, the average variations of ∆V th and ∆V gm in M3INV-JL are smaller than those in M3INV-MOS as L G decreases. In the case of both M3INV-MOS and M3INV-JL, these results are dependent on the bottom-gate voltage variation (∆V pgs ) are similar to the classical capacitive coupling ratio γ (=∆V th /∆V pgs ) of asymmetric double-gate (DG) ultra-thin body silicon on insulator (UTB-SOI) MOSFET [21] because both structures of the top N-type transistors in M3INV-MOS and M3INV-JL are similar to one of asymmetric DG UTB-SOI MOSFET. As T ILD decreases, γ increases [14,21], as follows.
where X bar means the distance between the front SiO 2 /Si interface and barycenter location of charge in the silicon channel [22] [21] and inversion [20], respectively.
It is noted that dependence of back-gate voltage for full-depletion in all the channel of M3INV-JL is larger than one for strong inversion of M3INV-MOS. transistors are depleted without any accumulation [21] and inversion [20], respectively. It is noted that dependence of back-gate voltage for full-depletion in all the channel of M3INV-JL is larger than one for strong inversion of M3INV-MOS.

Inverter Characteristics
Mixed-mode circuit simulation of ATLAS was used to verify the inverter characteristics by both M3INV-MOS and M3INV-JL including the electrical coupling. Figures 5 and 6 show the voltage transfer characteristics (VTC) of M3INV-MOS and M3INV-JL, respectively. Figures 5a and 6a show the simulation results of LG = 20 nm and Figures 5b and 6b show those of LG = 50 nm. M3INV-MOS shifts VTC from right to left as TILD increases, but M3INV-JL shifts VTC from left to right as TILD increases. Figure 7 shows ΔVm versus TILD of both M3INV-MOS and M3INV-JL. As TILD decreases, ΔVm increases. When TILD is over 30 nm, ΔVm are below 10 mV, and thus the coupling in the structures can be ignored. In the case of M3INV-MOS, the larger LG, the larger ΔVm, but in the case of M3INV-JL, the smaller LG, the larger ΔVm.

Inverter Characteristics
Mixed-mode circuit simulation of ATLAS was used to verify the inverter characteristics by both M3INV-MOS and M3INV-JL including the electrical coupling. Figures 5 and 6 show the voltage transfer characteristics (VTC) of M3INV-MOS and M3INV-JL, respectively. Figures 5a and 6a show the simulation results of L G = 20 nm and Figures 5b and 6b show those of L G = 50 nm. M3INV-MOS shifts VTC from right to left as T ILD increases, but M3INV-JL shifts VTC from left to right as T ILD increases. Figure 7 shows ∆V m versus T ILD of both M3INV-MOS and M3INV-JL. As T ILD decreases, ∆V m increases. When T ILD is over 30 nm, ∆V m are below 10 mV, and thus the coupling in the structures can be ignored. In the case of M3INV-MOS, the larger L G , the larger ∆V m , but in the case of M3INV-JL, the smaller L G , the larger ∆V m .     Figure  9 shows the noise margins of M3INV-MOS and M3INV-JL at different LGs and TILDs. In the       Table 2 shows the propagation delays extracted from the transient response in Figure 10. As TILD decreases, propagation delays of M3INV-MOS and M3INV-JL increase and decrease, respectively. As LG increases, propagation delays of both M3INV-MOS and M3INV-JL increase. When TILD is over 30 nm, the maximum variations of propagation delay of both M3INV-MOS and M3INV-JL are below 0.2 ps, and thus the coupling in the structures can be also ignored.   Table 2 shows the propagation delays extracted from the transient response in Figure 10. As T ILD decreases, propagation delays of M3INV-MOS and M3INV-JL increase and decrease, respectively. As L G increases, propagation delays of both M3INV-MOS and M3INV-JL increase. When T ILD is over 30 nm, the maximum variations of propagation delay of both M3INV-MOS and M3INV-JL are below 0.2 ps, and thus the coupling in the structures can be also ignored.
denote SNMs of M3INV-MOS and M3INV-JL with TILD = 5, 10, 50, and 100 nm, respectively. Squares, circles, and triangles denote SNMs of M3INV-MOS and M3INV-JL with LG = 20, 30, and 50 nm, respectively. Figure 10 show the transient responses of M3INV-MOS and M3INV-JL with LG = 20 nm at different TILDs, respectively. Table 2 shows the propagation delays extracted from the transient response in Figure 10. As TILD decreases, propagation delays of M3INV-MOS and M3INV-JL increase and decrease, respectively. As LG increases, propagation delays of both M3INV-MOS and M3INV-JL increase. When TILD is over 30 nm, the maximum variations of propagation delay of both M3INV-MOS and M3INV-JL are below 0.2 ps, and thus the coupling in the structures can be also ignored.

Conclusions
In this paper, we investigated the electrical coupling through the threshold voltage, transconductance, and gate capacitance variation according to T ILD of M3INV-MOS and M3INV-JL through TCAD simulation and compared the VTC and V m and SNM characteristics in M3INV-MOS and M3INV-JL. In both M3INV-MOS and M3INV-JL, ∆V th , ∆V gm , and ∆V Cngng increase as T ILD decreases. The smaller L G , the larger ∆V th and ∆V gm , but ∆V Cngng is not significant. In addition, as T ILD increased, M3INV-MOS and M3INV-JL shifted VTCs from right to left and from left to right, respectively. The larger L G , the larger and smaller ∆V m of M3INV-MOS and M3INV-JL, respectively. The noise margin and inverter characteristics of M3INV-MOS is larger and better than those of M3INV-JL. M3INV-MOS has less electrical coupling in terms of ∆V th , ∆Vg m , ∆V Cngng , ∆V m , NM H , NM L , and propagation delay than M3INV-JL. When T ILD is over 30 nm, ∆V th , ∆V gm , and ∆V Cngng are below 50 mV, ∆V m are below 10 mV, the maximum variations of SNM of both M3INV-MOS and M3INV-JL are below 20 mV, and the maximum variations of propagation delay of both M3INV-MOS and M3INV-JL are below 0.2 ps, and thus the coupling in the structures can be ignored. Data Availability Statement: The raw/processed data required to reproduce these findings will be shared upon request from the corresponding author.