Understanding of Feedback Field-E ﬀ ect Transistor and Its Applications

: Feedback ﬁeld-e ﬀ ect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent subthreshold swing (~0 mV / decade at 300 K), a high on- / o ﬀ current ratio (~10 10 ), and a clear saturation region. The power consumption of both the turn-on state and turn-o ﬀ state is signiﬁcantly low until operation commences. In addition, the hysteresis caused by the carriers accumulated in the potential wall allows the FBFET to act as a memory device. Moreover, the power consumption of neuromorphic devices can be suppressed by ~100 times with the use of FBFETs. In this work, we analyze the device structure and operating principle of the FBFET and summarize its applications.


Introduction
Metal-oxide-semiconductor field-effect transistors (MOSFETs) have been scaled down over the last half-century to achieve high density, high performance, and high cost-effectiveness [1][2][3]. In spite of the advantages of scaling, some issues have arisen as the device sizes continue to shrink. For instance, the power consumption and operating temperature of the transistor have increased significantly [2,3]. In addition, the leakage current has increased to the extent that it may surpass the dynamic power consumption [2,3]. Various techniques have been introduced to reduce both the leakage current and power consumption, but those efforts have thus far been restricted by the theoretical limit of subthreshold swing (SS) (i.e., SS~60 mV/decade at 300 K) of MOSFET [2]. In order to improve the subthreshold swing of the transistor, various novel steep-switching devices have been explored. The major novel devices are classified as follows: negative capacitance FET (NCFET) that exhibits steep slope by using the negative capacitance effect of ferroelectric layer [4][5][6][7][8], phase FET, which consolidates additional components to use the unique properties of phase transition material like abrupt and reversible resistivity switching with a conventional thermionic emission process through low-drive voltage [9,10], Nano-Electro-Mechanical (NEM) relay using the mechanical operation for causing connection and disconnection of the channel [11], impact ionization MOS (I-MOS) device controlled by impact ionization which is generated by a high electric field [12][13][14], and tunnel FET (TFET), utilizing the band-to-band tunneling (BTBT) operational mechanism [15][16][17].
Of these, field-effect transistors (FETs) using a positive feedback mechanism have attracted particular attention. Feedback FETs (FBFETs) show excellent subthreshold swing (~0 mV/decade at 300 K) and high on-/off current ratios (~10 10 ) [18,19]. For those reasons, many researchers have expressed interest in FBFETs and proposed various types of FBFETs, such as positive feedback devices (PF devices) [20][21][22], zero-impact ionization, zero subthreshold swing FETs (Z 2 -FETs) [23][24][25][26][27][28][29], and zero  The FBFET can overcome the limits of conventional MOSFETs. The FBFET can have steep switching values (i.e., subthreshold swing ~2 mV/decade at room temperature) and a high on-/off current ratio (~10 7 ) [63,64]. Based on the voltage applied to the gate, the FBFET can, of course, operate as both an n-type and p-type transistor. However, the mechanism that depends on the trapped charge can cause issues. For example, as the device operates, the stimulus applied to the spacer creates instability. Furthermore, an additional process is needed to store the carrier on the spacer attached to the source and drain regions, which should be simplified.
Based on the FBFET structure, many studies have been conducted to improve the electrical role of potential barriers on the FBFET (see Figure 1). Each barrier that blocks the flow of electrons and holes makes it possible to utilize P-I-N diodes as FBFETs. This can be understood and analyzed using energy band diagrams (see Figure 2). The whole steps for the mechanism above are described in detail in Section 2.2.  The FBFET can overcome the limits of conventional MOSFETs. The FBFET can have steep switching values (i.e., subthreshold swing ~2 mV/decade at room temperature) and a high on-/off current ratio (~10 7 ) [63,64]. Based on the voltage applied to the gate, the FBFET can, of course, operate as both an n-type and p-type transistor. However, the mechanism that depends on the trapped charge can cause issues. For example, as the device operates, the stimulus applied to the spacer creates instability. Furthermore, an additional process is needed to store the carrier on the spacer attached to the source and drain regions, which should be simplified.
Based on the FBFET structure, many studies have been conducted to improve the electrical The FBFET can overcome the limits of conventional MOSFETs. The FBFET can have steep switching values (i.e., subthreshold swing~2 mV/decade at room temperature) and a high on-/off current ratio (~10 7 ) [63,64]. Based on the voltage applied to the gate, the FBFET can, of course, operate as both an n-type and p-type transistor. However, the mechanism that depends on the trapped charge can cause issues. For example, as the device operates, the stimulus applied to the spacer creates instability. Furthermore, an additional process is needed to store the carrier on the spacer attached to the source and drain regions, which should be simplified.
Based on the FBFET structure, many studies have been conducted to improve the electrical properties of the FBFET [23][24][25][26][27][28][29][30][31][32][37][38][39][40][41][42]. The most common framework among them is to change the means of fabricating the two potential barriers implemented by the trapped charges of the gate-sidewall spacers. There are two approaches: (1) the first is to replace them with potential barriers created by the junctions of Si regions with different doping concentrations. Depending on the location of the gate, next to the source or drain, the type of operation is determined by the n-or p-type FET. Therefore, it can play the role of n-and p-type transistors simultaneously through the modification of device structure having double gates adjacent to the source and drain [63][64][65]. (2) The other approach is to form an additional gate next to the source (S) and drain (D) regions by using electrical energy as a potential barrier. This device structure can perform as an n-or p-type FET, depending on the voltage applied to the gate. However, it has the disadvantage that there is the energy consumption by the gate voltage for the barrier.

Positive Feedback Mechanism
Feedback indicates that all or part of the output returns back to the input. Positive feedback has the characteristic that the input condition increases after a single process, and the re-input condition is repeated for the second process. Regenerative cycles thus continue to be positively amplified.
FBFETs have two potential barriers, which are located in the channel region next to the source and drain, as in thyristors, and these prevent the flow of electrons and holes. As the potential barrier is formed, a potential wall is simultaneously formed on the opposite side, which has the lowest energy state for carriers. When a gate voltage is applied, positive feedback begins to operate through the lowered potential barrier. It is possible for carriers to flow from the source to the drain through the lowered potential barrier. Some electrons or holes are trapped in the potential wall in the channel region [63][64][65]. Charges induced by carriers trapped in the potential wall act on the energy band. Electrons increase the energy band in the adjacent region, meaning that the potential barrier on the opposite side of the potential wall is lowered. Holes have the opposite effect of electrons, causing the energy band to become higher. Trapped holes near the potential wall will cause barrier collapse. As the barriers have a lowered height, additional carrier flow occurs through the lowered barrier to operate the former process repeatedly. Once the operation has begun, the positive feedback loop can continue to operate without any additional voltage. As a result, higher currents can flow, as compared with the case in which only voltage was applied to the gate primarily to lower the potential barrier [63][64][65]. Figure 3 shows the loop for showing the positive feedback mechanism after the spacer is conditioned with trapped charges. The potential barrier height to block the electron flow induced by the trapped charge on the spacer is expressed as V Be , with an initial state between the N+ doping concentration region and the spacer region adjacent to the N+ region without the gate and drain bias at equilibrium. If there is super-elevation on the gate bias (V G0 ) and drain bias (V D0 ) at equilibrium, the additional reduction of the electron (hole) injection barrier can be defined as φ e (φ h ). The height of the potential barrier blocking the electrons can be defined as (V Be − φ e ) [65]. The drift current can be neglected owing to the dominance of the diffusion current in the ideal diode equation. D n and D p are the diffusivity of electrons or holes, and L n and L p are the diffusion length for electrons or holes, respectively. n p is the minority carrier concentration at the boundary x = −x p , and p n is the minority carrier concentration at the boundary x = x n . k is Boltzmann's constant. When V G0 is applied to the gate and V D0 is applied to the drain, the initial electron current can be written using the Shockley equation, as follows: I e0 = qA(D p p n L P −1 + D n n p L n −1 ) (e [qV/(kT)] − 1), Appl. Sci. 2020, 10, x FOR PEER REVIEW 5 of 19 Figure 3. Positive feedback mechanism: the operational principles are divided into two steps [65].
Step 1. If we set the condition of a small change in the gate voltage or drain voltage, a small perturbation, ΔY, of the electron injection barrier will occur. The ΔY caused by an exterior change will allow more electrons to be injected into the intrinsic Si region from the N+ region. The resulting change in electron current (Δ ) is presented as follows: Using the Taylor's expansion on the e[ΔY/(kT)] for the first two terms yields the following: Assuming that no recombination occurs in the channel region, the electrons flowing from the N+ region will accumulate in the potential wall next to the P+ region. Some carriers will be stored in the wall, while others will cross the potential wall barrier and have sufficient kinetic energy to be injected into the drain and be recombined. Letting the charge stored in the potential wall be Δ −, the electron carrier lifetime be τ_, the barrier potential seen by the electrons in the potential wall be ϕBh, and A be a parameter, the following can be obtained: The charge, −, from the electrons stored in the potential wall can be given by: Step 2. VBh will be decreased and ϕh will be increased by the − affected by the stored electrons. More holes will be injected into the channel from the collapsing potential barrier. The changes in the hole barrier (Δ ) and hole current (ΔIh) are given as follows: The capacitance under the P+ spacer is Cp. Again, using the Taylor's expansion on e[ΔZ/(kT)] and only including the first two terms yields the following: For the same bias, the hole barrier (at the drain side) induced by the initial hole current can be written as follows: I h0 = qA(D p P n L P −1 + D n n p L n −1 ) (e [qV/(kT)] − 1) Step 1. If we set the condition of a small change in the gate voltage or drain voltage, a small perturbation, ∆Y, of the electron injection barrier will occur. The ∆Y caused by an exterior change will allow more electrons to be injected into the intrinsic Si region from the N+ region. The resulting change in electron current (∆I e ) is presented as follows: Assuming that no recombination occurs in the channel region, the electrons flowing from the N+ region will accumulate in the potential wall next to the P+ region. Some carriers will be stored in the wall, while others will cross the potential wall barrier and have sufficient kinetic energy to be injected into the drain and be recombined. Letting the charge stored in the potential wall be ∆Q−, the electron carrier lifetime be τ _ , the barrier potential seen by the electrons in the potential wall be φBh, and A be a parameter, the following can be obtained: The charge, ∆Q−, from the electrons stored in the potential wall can be given by: Step 2. V Bh will be decreased and φ h will be increased by the ∆Q− affected by the stored electrons. More holes will be injected into the channel from the collapsing potential barrier. The changes in the hole barrier (∆Z) and hole current (∆I h ) are given as follows: The capacitance under the P+ spacer is C p . Again, using the Taylor's expansion on e[∆Z/(kT)] and only including the first two terms yields the following: Through the same processes and conditions as perturbation of energy band next to the drain, the hole current flows to the source side and is trapped in a potential wall near the N+ source, affecting the valance band (E V ) potential. Thus, V Be decreases by δY.
Let the charge stored in the potential wall be ∆Q+ near the N+ region, C n be the capacitance under the potential wall conditioning with trapped electrons region, the hole carrier lifetime be τ + , the barrier potential seen by the hole in the potential wall be φ Be , and B be a parameter. The equation for gain can be described with these parameters: where, When the gain is ≥1, FBFET will be operated with steep-switching by the positive feedback. As the positive feedback mechanism uses both electrons and holes, the type of transistor is determined by which of the two potential barriers blocks the flow of holes/electrons and applies a negative/positive voltage to initiate a feedback operation (see Figure 4) [63][64][65].
Appl. Sci. 2020, 10, x FOR PEER REVIEW 6 of 19 Through the same processes and conditions as perturbation of energy band next to the drain, the hole current flows to the source side and is trapped in a potential wall near the N+ source, affecting the valance band (EV) potential. Thus, VBe decreases by δY.
Let the charge stored in the potential wall be Δ + near the N+ region, Cn be the capacitance under the potential wall conditioning with trapped electrons region, the hole carrier lifetime be τ+, the barrier potential seen by the hole in the potential wall be ϕBe, and B be a parameter. The equation for gain can be described with these parameters: where, When the gain is ≥1, FBFET will be operated with steep-switching by the positive feedback. As the positive feedback mechanism uses both electrons and holes, the type of transistor is determined by which of the two potential barriers blocks the flow of holes/electrons and applies a negative/positive voltage to initiate a feedback operation (see Figure 4) [63][64][65].

PF and Band-Modulation Devices (FED, Z 2 -FET, Z 3 -FET)
Depending on the specific mechanisms and the device structures, FBFETs have various names, such as PF devices [21,22], band-modulation devices (BM devices) [66,67], Z 2 -FET devices [23][24][25][26][27][28][29], and Z 3 -FET devices (see Figure 5) [30][31][32]. The positive feedback first proposed in FBFETs is their key operation principle. Based on the positive feedback mechanism, two potential barriers are created in three ways: the first one is through a trapped charge of the spacer or insulator layer (see Figure 1) [23,63,64,68,69], the second one is by creating a virtual doping concentration through the gate voltage in the channel region next to the source/drain (see Figure 5) [30][31][32][70][71][72][73], and the third one is through the junction of Si regions with different doping concentrations (see Figure 6) [74,75]. The mechanism used in the first and second is called band modulation, and devices with positive feedback and band modulation can be classified separately (see the list in Table 1).
Appl. Sci. 2020, 10, x FOR PEER REVIEW 7 of 19 and Z 3 -FET devices (see Figure 5) [30][31][32]. The positive feedback first proposed in FBFETs is their key operation principle. Based on the positive feedback mechanism, two potential barriers are created in three ways: the first one is through a trapped charge of the spacer or insulator layer (see Figure 1) [23,63,64,68,69], the second one is by creating a virtual doping concentration through the gate voltage in the channel region next to the source/drain (see Figure 5) [30][31][32][70][71][72][73], and the third one is through the junction of Si regions with different doping concentrations (see Figure 6) [74,75]. The mechanism used in the first and second is called band modulation, and devices with positive feedback and band modulation can be classified separately (see the list in Table 1).     and Z 3 -FET devices (see Figure 5) [30][31][32]. The positive feedback first proposed in FBFETs is their key operation principle. Based on the positive feedback mechanism, two potential barriers are created in three ways: the first one is through a trapped charge of the spacer or insulator layer (see Figure 1) [23,63,64,68,69], the second one is by creating a virtual doping concentration through the gate voltage in the channel region next to the source/drain (see Figure 5) [30][31][32][70][71][72][73], and the third one is through the junction of Si regions with different doping concentrations (see Figure 6) [74,75]. The mechanism used in the first and second is called band modulation, and devices with positive feedback and band modulation can be classified separately (see the list in Table 1).     First, all devices including FBFETs that rely on positive feedback can be considered as PF devices. Secondly, these devices can be identified as band-modulation devices if they depend on the band modulation mechanism for barrier formation. Band-modulation devices include field-effect diodes (FEDs) [77][78][79], Z 2 -FETs, and Z 3 -FETs, as already shown in Figure 5. The Z 3 -FET device appears similar to forward-biased P-I-N diodes with undoped ultra-thin silicon films. The device configuration can be seen as a reverse FED. This new device is configurable by applying the standard design rules for fully depleted silicon-on-insulator (FDSOI) technologies [30][31][32]. The ground plane under the thin buried oxide (BOX) allows the threshold voltage of the complementary metal-oxide-semiconductor (CMOS) circuit to be adjusted. As the top gate stack is replaced with a buried ground plane, a reliability issue arises concerning whether it can withstand much higher breakdown voltage through a sufficiently thick BOX rather than the previous thin gate insulator layer. An important feature of Z 3 -FETs that benefit from using a gate oxide as a BOX is that a high back gate bias can be maintained. Compared with Z 2 -FETs, Z 3 -FETs have no high-voltage metal gate stack, and thus there is no problem with high-voltage stability [30,31]. Z 3 -FETs with these features show their potential as sensors with internal memory for various applications.
When the temperature or the V DS value increases, the on-/off current ratio increases. As the depth of the channel decreases, the device exhibits features that have characteristics more suitable for Appl. Sci. 2020, 10, 3070 9 of 19 FDSOI structures. As the dielectric constant of the insulator layer increases, threshold voltage (V TH ) increases, while V TH decreases with increasing the work function of gate material. Depending on the gate voltage, there is a limit to the channel length, and, depending on the gate length, there is a limit on V TH . N-/p-type FBFETs are formed based on the gate location adjacent to the source/drain [75]. As the channel length increases over 500 nm, V on increases, I on decreases, and abrupt switching decreases due to the fast regeneration of minority carriers. In addition, hysteresis disappears as the channel length increases [80].
Various simulation studies have found that, the shorter the region of the FBFET channel is, the better the performance is. Shortening the channel length improves the switching characteristics, and the outstanding characteristics of the FBFET are represented with the benefits from scaling a device, unlike the existing MOSFETs [75]. In contrast, as the channel length increases, low SS values and on-/off-current without saturation can be obtained. For channel lengths longer than 100 nm, FBFETs do not exhibit ideal switching characteristics. Nevertheless, all of the SS values were less than 60 mV/decade at 300 K.
However, recent studies have shown that the positive feedback mechanism does not work, in contrast to the improved characteristics that have been achieved on the~10 nm scale. The cause lies in the role of the potential barriers, which are key in the operation of FBFET. As the channel length increases, the potential barrier becomes wider. The energy and time required to collapse the potential barrier increase when the channel length is longer than 40 nm. At smaller scales, however, the potential barrier becomes too narrow, resulting in short channel effects (SCE), which are expected to block the carrier flow. To solve this limitation, it is necessary to consider ways to overcome the SCE, as in conventional MOSFETs [75].
When the channel length decreases, the threshold voltage decreases and the on-/off current ratio increases. However, there are limitations on V DS , depending on the channel length. If the channel length is 40 nm, the V DS value will not be able to cut off the current at 1.1 V. When V DS is 1 V, the channel length of 30 nm cannot cut off the current. As a result, there is a limit on the possible shrinking in FBFET, as shown in Figure 7 [75]. In addition, as the drain current increases, a problem arises in that the value of the potential voltage preventing carrier flow in the drain becomes low [63][64][65]75].
When the temperature or the VDS value increases, the on-/off current ratio increases. As the depth of the channel decreases, the device exhibits features that have characteristics more suitable for FDSOI structures. As the dielectric constant of the insulator layer increases, threshold voltage (VTH) increases, while VTH decreases with increasing the work function of gate material. Depending on the gate voltage, there is a limit to the channel length, and, depending on the gate length, there is a limit on VTH. N-/p-type FBFETs are formed based on the gate location adjacent to the source/drain [75]. As the channel length increases over 500 nm, Von increases, Ion decreases, and abrupt switching decreases due to the fast regeneration of minority carriers. In addition, hysteresis disappears as the channel length increases [80].
Various simulation studies have found that, the shorter the region of the FBFET channel is, the better the performance is. Shortening the channel length improves the switching characteristics, and the outstanding characteristics of the FBFET are represented with the benefits from scaling a device, unlike the existing MOSFETs [75]. In contrast, as the channel length increases, low SS values and on-/off-current without saturation can be obtained. For channel lengths longer than 100 nm, FBFETs do not exhibit ideal switching characteristics. Nevertheless, all of the SS values were less than 60 mV/decade at 300 K.
However, recent studies have shown that the positive feedback mechanism does not work, in contrast to the improved characteristics that have been achieved on the ~10 nm scale. The cause lies in the role of the potential barriers, which are key in the operation of FBFET. As the channel length increases, the potential barrier becomes wider. The energy and time required to collapse the potential barrier increase when the channel length is longer than 40 nm. At smaller scales, however, the potential barrier becomes too narrow, resulting in short channel effects (SCE), which are expected to block the carrier flow. To solve this limitation, it is necessary to consider ways to overcome the SCE, as in conventional MOSFETs [75].
When the channel length decreases, the threshold voltage decreases and the on-/off current ratio increases. However, there are limitations on VDS, depending on the channel length. If the channel length is 40 nm, the VDS value will not be able to cut off the current at 1.1 V. When VDS is 1 V, the channel length of 30 nm cannot cut off the current. As a result, there is a limit on the possible shrinking in FBFET, as shown in Figure 7 [75]. In addition, as the drain current increases, a problem arises in that the value of the potential voltage preventing carrier flow in the drain becomes low. [63][64][65]75].

Logic Device Applications (FBFET-Based Inverter)
An inverter design that functions properly requires efficient operation of the pullup and pulldown devices. As the device must be operated under a forward bias, the magnitude of V DS should be higher than the built-in potential of FBFET [81]. This can be optimized through various combinations of bias, which requires a significant amount of effort. Nevertheless, the advantages of an inverter with a combined FBFET are as follows: FBFETs have a steep-switching feature and high current on/off-current ratio; moreover, the saturation region is clear, especially beyond V TH . In other words, the amount of current supplied to the operating and non-operating regions can be distinguished by the gate voltage (V g ), and thus the power consumption during operation and in the off-state can become minimal. The steep-switching characteristic of the FBFET is utilized in digital integrated circuits. A typical example is that the switching is controlled by an FBFET in the inverter. In a conventional inverter circuit, as the input voltage continues to increase, the charge stored in the capacitor of the circuit tends to run low over a long period of time [81,82]. However, if the FBFET plays the role of controlling the input voltage supply for the operation of the inverter, the voltage stored in the capacitor changes rapidly at V TH of the FBFET. In addition, starting from V TH , the voltage supply appears as a saturation region, showing stable on/off-states. The FBFET-based inverter is shown in Figure 8.

Logic Device Applications (FBFET-Based Inverter)
An inverter design that functions properly requires efficient operation of the pullup and pulldown devices. As the device must be operated under a forward bias, the magnitude of VDS should be higher than the built-in potential of FBFET [81]. This can be optimized through various combinations of bias, which requires a significant amount of effort. Nevertheless, the advantages of an inverter with a combined FBFET are as follows: FBFETs have a steep-switching feature and high current on/off-current ratio; moreover, the saturation region is clear, especially beyond VTH. In other words, the amount of current supplied to the operating and non-operating regions can be distinguished by the gate voltage (Vg), and thus the power consumption during operation and in the off-state can become minimal. The steep-switching characteristic of the FBFET is utilized in digital integrated circuits. A typical example is that the switching is controlled by an FBFET in the inverter. In a conventional inverter circuit, as the input voltage continues to increase, the charge stored in the capacitor of the circuit tends to run low over a long period of time [81,82]. However, if the FBFET plays the role of controlling the input voltage supply for the operation of the inverter, the voltage stored in the capacitor changes rapidly at VTH of the FBFET. In addition, starting from VTH, the voltage supply appears as a saturation region, showing stable on/off-states. The FBFET-based inverter is shown in Figure 8.

Memory Cells
The traditional 1T-1C DRAM has allowed the reduction of device sizes to improve the performance and density of cells. The conventional 6-transistor static random-access memory (6T-SRAM) exhibits high performance with low density [83][84][85][86][87][88][89], while DRAM exhibits relatively low performance but provides high density [90]. FBFETs can be used for next-generation DRAM and SRAM to overcome the technical limits of each. A large amount of research has been carried out to demonstrate the competitive characteristics in the field of DRAM, and the capacitor-less DRAM (1T-DRAM), which was first proposed twenty years ago, has received much attention [33]. 1T-DRAM utilizes side effects such as hysteresis, which some studies consider harmful and have tried to remove. When the parasitic carriers that generally cause hysteresis are stored in the body and increase the potential, the threshold voltage is lowered and high current can be achieved-this is defined as the

Memory Cells
The traditional 1T-1C DRAM has allowed the reduction of device sizes to improve the performance and density of cells. The conventional 6-transistor static random-access memory (6T-SRAM) exhibits high performance with low density [83][84][85][86][87][88][89], while DRAM exhibits relatively low performance but provides high density [90]. FBFETs can be used for next-generation DRAM and SRAM to overcome the technical limits of each. A large amount of research has been carried out to demonstrate the competitive characteristics in the field of DRAM, and the capacitor-less DRAM (1T-DRAM), which was first proposed twenty years ago, has received much attention [33]. 1T-DRAM utilizes side effects such as hysteresis, which some studies consider harmful and have tried to remove. When the parasitic carriers that generally cause hysteresis are stored in the body and increase the potential, the threshold voltage is lowered and high current can be achieved-this is defined as the '1' state. The '0' state features a lower current achieved by removing the carriers from the body [34][35][36][43][44][45][46][47][48]88].
The 1T-DRAM has remained stalled in its current state as a potential next-generation candidate. While the 1T-DRAM has great structural advantages, it is necessary to demonstrate its ability to be fully commercialized in order for it to replace the conventional DRAM. Unfortunately, fatal drawbacks such as low reliability, high power consumption, or incompatibility with standard process technologies have emerged for various proposed models [37][38][39][40][41][42]. Most importantly, the traditional DRAM continues to succeed in the development process without serious problems. At present, the conventional 1T-1C DRAM memory cell is reaching its scaling limit. One of its biggest problems is that scaling the cell capacitor can no longer keep up with the transistor [41,42]. To ensure correct memory cell operation, a minimum space is required to store a certain amount of charge. The conventional methods for improving performance through scaling are thus now stagnating in the 1T-1C DRAM device architecture. In addition to devising various technologies to overcome these difficulties, it seems reasonable to consider a new DRAM structure. One promising candidate is memory cell types that store charges in the body of the transistor, thus modulating the threshold voltage and exhibiting distinct drain currents without the capacitor facing scale limitations. The body of the memory cell is then fully depleted of the accumulated carriers to obtain two distinct current levels corresponding to the complementary logic states. There are some device structures, such as MSDRAM [34] and A2RAM [37,38], that can meet most of the DRAM requirements: the ability to work under low voltage, low power consumption, long retention times, and scalability. Among 1T-DRAM cell candidates, the devices containing FBFETs exhibit excellent possibilities with a steep subthreshold swing owing to their positive feedback mechanism. These devices stand out for their performance and feasible integration with the standard fabrication process for ultra-thin body structures (see Figure 9). drawbacks such as low reliability, high power consumption, or incompatibility with standard process technologies have emerged for various proposed models [37][38][39][40][41][42]. Most importantly, the traditional DRAM continues to succeed in the development process without serious problems. At present, the conventional 1T-1C DRAM memory cell is reaching its scaling limit. One of its biggest problems is that scaling the cell capacitor can no longer keep up with the transistor [41,42]. To ensure correct memory cell operation, a minimum space is required to store a certain amount of charge. The conventional methods for improving performance through scaling are thus now stagnating in the 1T-1C DRAM device architecture. In addition to devising various technologies to overcome these difficulties, it seems reasonable to consider a new DRAM structure. One promising candidate is memory cell types that store charges in the body of the transistor, thus modulating the threshold voltage and exhibiting distinct drain currents without the capacitor facing scale limitations. The body of the memory cell is then fully depleted of the accumulated carriers to obtain two distinct current levels corresponding to the complementary logic states. There are some device structures, such as MSDRAM [34] and A2RAM [37,38], that can meet most of the DRAM requirements: the ability to work under low voltage, low power consumption, long retention times, and scalability. Among 1T-DRAM cell candidates, the devices containing FBFETs exhibit excellent possibilities with a steep subthreshold swing owing to their positive feedback mechanism. These devices stand out for their performance and feasible integration with the standard fabrication process for ultra-thin body structures (see Figure 9). There are reasons why FBFET devices should command particular attention. First, the MSDRAM uses a mechanism based on the meta-stable dip hysteresis effect, which requires hysteresis [34]. However, the super-coupling effect, which occurs below 10 nm, makes it difficult for the electrons and hole channels to coexist [35,36]. Secondly, A2RAM considers the high state as that when sufficient holes are stored in the body to create a current bridge from the source to the drain [37]. The other state is defined by the disconnected bridge in the fully depleted state [38]. However, the fabrication and variability of bridges in films is limited when the overall thickness is less than 10 nm. The operation mechanism of the FBFET as 1T-DRAM is as follows. The FBFET has potential barriers controlled by the gate voltage that blocks the flow of electrons or holes along the channel. The mechanism by which hysteresis occurs is that the voltage applied to the gate causes a small collapse owing to the band modulation at the potential barrier [43][44][45][46][47][48]. A flow of carriers then occurs, which are sequentially trapped in the potential wall. The potential walls affected by the accumulated carriers cause a constant change in the height of the opposite potential barrier, which controls the There are reasons why FBFET devices should command particular attention. First, the MSDRAM uses a mechanism based on the meta-stable dip hysteresis effect, which requires hysteresis [34]. However, the super-coupling effect, which occurs below 10 nm, makes it difficult for the electrons and hole channels to coexist [35,36]. Secondly, A2RAM considers the high state as that when sufficient holes are stored in the body to create a current bridge from the source to the drain [37]. The other state is defined by the disconnected bridge in the fully depleted state [38]. However, the fabrication and variability of bridges in films is limited when the overall thickness is less than 10 nm. The operation mechanism of the FBFET as 1T-DRAM is as follows. The FBFET has potential barriers controlled by the gate voltage that blocks the flow of electrons or holes along the channel. The mechanism by which hysteresis occurs is that the voltage applied to the gate causes a small collapse owing to the band modulation at the potential barrier [43][44][45][46][47][48]. A flow of carriers then occurs, which are sequentially trapped in the potential wall. The potential walls affected by the accumulated carriers cause a constant change in the height of the opposite potential barrier, which controls the flow of the other carriers. As a result, there is a huge difference in the current flowing to the source and drain repeatedly, which eventually collapses both potential barriers through the carriers trapped in the potential walls [46].
The condition in which carriers are trapped in the potential wall to allow the current to flow well is defined as "1". Accordingly, the process of trapping the carriers in the potential wall is referred to as the process of "writing", whereas "holding" is the process of maintaining the data value, and "reading" is the current value in the trapped state [43][44][45][46][47][48]. In contrast, the carrier is released from the potential wall, and thus the height of the potential barrier is high, and the current is blocked. In this case, the state can be written by removing the trapped carrier by adding applied voltage to the opposite gate voltage to release the carrier.
To write the state of '0', the gate voltage is dropped to 0 V to remove the carrier from the channel region located below the gate. Holding state '0' involves returning to a highly negative V G (V Ge ) range, the device is not in equilibrium because there are no carriers that can be pulled to construct the inversion layer (deep depletion). The rapid change in potential makes the hole injection barrier very steep. To read the '0' state, data is read with a negative pulse. V D should be allowed to select between the measured V De values in the DC and transient modes, so that the diode does not turn on to ignore uncalled current. State '0' must be refreshed constantly because the energy barrier and V De are lowered by trapped carriers that are generated to recharge the channel region under the gate (see Figures 10 and 11) [46].
in the potential walls [46].
The condition in which carriers are trapped in the potential wall to allow the current to flow well is defined as "1". Accordingly, the process of trapping the carriers in the potential wall is referred to as the process of "writing", whereas "holding" is the process of maintaining the data value, and "reading" is the current value in the trapped state [43][44][45][46][47][48]. In contrast, the carrier is released from the potential wall, and thus the height of the potential barrier is high, and the current is blocked. In this case, the state can be written by removing the trapped carrier by adding applied voltage to the opposite gate voltage to release the carrier.
To write the state of '0', the gate voltage is dropped to 0 V to remove the carrier from the channel region located below the gate. Holding state '0' involves returning to a highly negative VG (VGe) range, the device is not in equilibrium because there are no carriers that can be pulled to construct the inversion layer (deep depletion). The rapid change in potential makes the hole injection barrier very steep. To read the '0' state, data is read with a negative pulse. VD should be allowed to select between the measured VDe values in the DC and transient modes, so that the diode does not turn on to ignore uncalled current. State '0' must be refreshed constantly because the energy barrier and VDe are lowered by trapped carriers that are generated to recharge the channel region under the gate (see Figure 10 and Figure 11) [46].  in the potential walls [46].
The condition in which carriers are trapped in the potential wall to allow the current to flow well is defined as "1". Accordingly, the process of trapping the carriers in the potential wall is referred to as the process of "writing", whereas "holding" is the process of maintaining the data value, and "reading" is the current value in the trapped state [43][44][45][46][47][48]. In contrast, the carrier is released from the potential wall, and thus the height of the potential barrier is high, and the current is blocked. In this case, the state can be written by removing the trapped carrier by adding applied voltage to the opposite gate voltage to release the carrier.
To write the state of '0', the gate voltage is dropped to 0 V to remove the carrier from the channel region located below the gate. Holding state '0' involves returning to a highly negative VG (VGe) range, the device is not in equilibrium because there are no carriers that can be pulled to construct the inversion layer (deep depletion). The rapid change in potential makes the hole injection barrier very steep. To read the '0' state, data is read with a negative pulse. VD should be allowed to select between the measured VDe values in the DC and transient modes, so that the diode does not turn on to ignore uncalled current. State '0' must be refreshed constantly because the energy barrier and VDe are lowered by trapped carriers that are generated to recharge the channel region under the gate (see Figure 10 and Figure 11) [46].  . Diagram of a capacitor-less DRAM equivalent circuit with logic values "0" and "1" in three states: writing, holding, and reading (logic). The arrow line at Hold "0" corresponds to the leakage current of the reverse-biased drain junction limiting the hold time [43].
As the gate voltage is set to 0 V to remove the potential barrier, state '1' is written. The V A pulse causes the forward bias of the P-I-N diode, allowing electrons and holes to flow into the channel region when the FBFET is viewed separately from the gate. To hold state '1', V G is applied such that carriers flowing through the channel region are attracted to a certain space under the gate. The barrier is lower than that in the state of holding '0', and V ON is reduced. Reading state '1' uses the pulse on the source of the FBFET to create a current in the device, which should be high [46].
In summary, in the '1' state, carriers are stored in the potential wall located in the channel on the body and increase the potential, thus lowering the potential barrier, which leads to a reduced threshold voltage and a high current. In state '0', carriers are removed from the trap located in the channel region on the body and reduce the affordable current [43][44][45][46][47][48].
In addition, a novel FBFET-based SRAM cell has been proposed. For these SRAM cells, the steep-switching characteristic conferred by the positive feedback operation allows for high-speed memory operation, while the high cell area, which has been considered a limitation in conventional SRAM, is solved through a simple device structure using the FBFET (see Figure 12) [52][53][54]. The cell achieves a small area of 8F 2 , enabling high-density integrated memory cell design, while the low switching current dramatically reduces the switching characteristics, simultaneously allowing the performance of low-power memory. The SRAM bit-cell also demonstrates the excellent operating performance of SRAM, including a write speed, fast read speed, and competent retention time based on the trapped charges in the channel region next to the source/drain [52][53][54]. As a result, these results show the great potential of FBFET DRAM and SRAM for the next-generation memory applications. Figure 11. Diagram of a capacitor-less DRAM equivalent circuit with logic values "0" and "1" in three states: writing, holding, and reading (logic). The arrow line at Hold "0" corresponds to the leakage current of the reverse-biased drain junction limiting the hold time [43].
As the gate voltage is set to 0 V to remove the potential barrier, state '1' is written. The VA pulse causes the forward bias of the P-I-N diode, allowing electrons and holes to flow into the channel region when the FBFET is viewed separately from the gate. To hold state '1', VG is applied such that carriers flowing through the channel region are attracted to a certain space under the gate. The barrier is lower than that in the state of holding '0', and VON is reduced. Reading state '1' uses the pulse on the source of the FBFET to create a current in the device, which should be high [46].
In summary, in the '1' state, carriers are stored in the potential wall located in the channel on the body and increase the potential, thus lowering the potential barrier, which leads to a reduced threshold voltage and a high current. In state '0', carriers are removed from the trap located in the channel region on the body and reduce the affordable current [43][44][45][46][47][48].
In addition, a novel FBFET-based SRAM cell has been proposed. For these SRAM cells, the steepswitching characteristic conferred by the positive feedback operation allows for high-speed memory operation, while the high cell area, which has been considered a limitation in conventional SRAM, is solved through a simple device structure using the FBFET (see Figure 12) [52][53][54]. The cell achieves a small area of 8F 2 , enabling high-density integrated memory cell design, while the low switching current dramatically reduces the switching characteristics, simultaneously allowing the performance of low-power memory. The SRAM bit-cell also demonstrates the excellent operating performance of SRAM, including a write speed, fast read speed, and competent retention time based on the trapped charges in the channel region next to the source/drain [52][53][54]. As a result, these results show the great potential of FBFET DRAM and SRAM for the next-generation memory applications.

Neuromorphic Cells
ANNs, which have been developed based on the neurotransmitter structure of biological neurons, have been proposed as a powerful method that can be used in place of conventional Neumann computing, especially for pattern recognition and classification [57,58]. Unlike von Neumann's existing computer architecture, ANNs have been proposed to solve the problem of not being able to compete with the energy efficiency of the biological brain. A new generation of ANNs have been proposed using spiking neural networks (SNNs) (see Figure 13) [59][60][61][62]. However, the traditional neuron circuits of SNNs require large areas as well as high power consumption. The application of FBFETs to neuromorphic devices is being investigated to solve these issues. PF devices with a split-gate floating body are proposed as new neuron devices that demonstrate integrationand-fire capabilities (see Figure 13). This simulation used a common magnetic controller in the

Neuromorphic Cells
ANNs, which have been developed based on the neurotransmitter structure of biological neurons, have been proposed as a powerful method that can be used in place of conventional Neumann computing, especially for pattern recognition and classification [57,58]. Unlike von Neumann's existing computer architecture, ANNs have been proposed to solve the problem of not being able to compete with the energy efficiency of the biological brain. A new generation of ANNs have been proposed using spiking neural networks (SNNs) (see Figure 13) [59][60][61][62]. However, the traditional neuron circuits of SNNs require large areas as well as high power consumption. The application of FBFETs to neuromorphic devices is being investigated to solve these issues. PF devices with a split-gate floating body are proposed as new neuron devices that demonstrate integration-and-fire capabilities (see Figure 13). This simulation used a common magnetic controller in the neuron layer and demonstrated the successful operation of a high-density multiple-PF neuron system exhibiting reset and lateral suppression. A reduction in power consumption of~100 times was reported, demonstrating the potential for use of FBFETs in neuromorphic circuits. The energy consumption of the current is proportional to the number of spikes. The average energy consumption of the total output neurons was reduced by approximately 94% compared to conventional neuron circuits. When the PF device value was applied, a low threshold swing (0.04 mV/decade) of the device was obtained, which reduced the existing 25 pJ/spike of the neuron circuit to~0.25 pJ/spike (see Figure 13c,d). In addition, charge storage through trapping in the potential walls of the wider body of the FBFET functions to imitate the integration in biological neurons without large capacitors. By replacing the C mem of the conventional neuron circuit, which requires a large space, by using positive feedback for the charge trap layer of the device, a smaller area and higher density of devices are available. Note that C mem refers to the membrane capacitor of the average neural circuit. As many transistors and capacitors have traditionally been needed for neuromorphic circuits, creating high density is important for their development. A 17-fold reduction in the area of the neurons was reportedly achieved through the use of FBFETs [21].
Appl. Sci. 2020, 10, x FOR PEER REVIEW 14 of 19 neuron layer and demonstrated the successful operation of a high-density multiple-PF neuron system exhibiting reset and lateral suppression. A reduction in power consumption of ~100 times was reported, demonstrating the potential for use of FBFETs in neuromorphic circuits. The energy consumption of the current is proportional to the number of spikes. The average energy consumption of the total output neurons was reduced by approximately 94% compared to conventional neuron circuits. When the PF device value was applied, a low threshold swing (0.04 mV/decade) of the device was obtained, which reduced the existing 25 pJ/spike of the neuron circuit to ~0.25 pJ/spike (see Figure 13 (c, d)). In addition, charge storage through trapping in the potential walls of the wider body of the FBFET functions to imitate the integration in biological neurons without large capacitors. By replacing the Cmem of the conventional neuron circuit, which requires a large space, by using positive feedback for the charge trap layer of the device, a smaller area and higher density of devices are available. Note that Cmem refers to the membrane capacitor of the average neural circuit. As many transistors and capacitors have traditionally been needed for neuromorphic circuits, creating high density is important for their development. A 17-fold reduction in the area of the neurons was reportedly achieved through the use of FBFETs [21].

Conclusions
In this paper, starting with the first proposed FBFET, various device structures were explored, and the positive feedback mechanism comprising their principle of operation was explained in detail. As a result of the positive feedback phenomenon, FBFETs show excellent subthreshold swing values (~0 mV/decade at 300 K) and high on-/off current ratios (~10 10 ), giving them potential for use as nextgeneration memory cells with hysteresis. FBFETs are applied to 1T-1C DRAM to create a capacitorless DRAM and to 6T-SRAM to create 2T-SRAM. These novel DRAM and SRAM devices can overcome the limits of conventional devices. FBFETs have also been applied to neuromorphic circuits, which have shown significantly improved performance. They can simultaneously solve both the power consumption and large-required areas. These data confirm the possibility of replacing existing devices with next-generation devices having ultra-low power, high performance, and high density.
Author Contributions: L.C. and S. J. equally contributed to this work. All authors have read and agreed to the published version of the manuscript.

Conflicts of Interest:
The authors declare that there is no conflict of interest.

Conclusions
In this paper, starting with the first proposed FBFET, various device structures were explored, and the positive feedback mechanism comprising their principle of operation was explained in detail. As a result of the positive feedback phenomenon, FBFETs show excellent subthreshold swing values (~0 mV/decade at 300 K) and high on-/off current ratios (~10 10 ), giving them potential for use as next-generation memory cells with hysteresis. FBFETs are applied to 1T-1C DRAM to create a capacitor-less DRAM and to 6T-SRAM to create 2T-SRAM. These novel DRAM and SRAM devices can overcome the limits of conventional devices. FBFETs have also been applied to neuromorphic circuits, which have shown significantly improved performance. They can simultaneously solve both the power consumption and large-required areas. These data confirm the possibility of replacing existing devices with next-generation devices having ultra-low power, high performance, and high density.