An Interleaved DC / DC Converter with Soft-switching Characteristic and high Step-up Ratio

: This study presents a dc / dc converter featuring soft-switching characteristic, high conversion e ﬃ ciency, and high step-up ratio. The proposed circuit is composed of two parallel-connected boost converters. Only one coupled inductor is used to replace inductors of the boost converters which are interleaved operated at discontinuous-conduction mode (DCM). The current ripples at the input and the output terminals are reduced due to the interleaved operation. By freewheeling the current of the coupled inductor to discharge the stored electric charges in the parasitic capacitors of the active switches, both active switches can fulﬁll zero-voltage switching on (ZVS). Owing to DCM operation, the freewheeling diodes can fulﬁll zero-current switching o ﬀ (ZCS). Therefore, the power conversion e ﬃ ciency is improved. The operation principle for each operation mode is analyzed in detail and design equations for the component parameters are provided in this report. Finally, a prototype 200 W 48–400 V converter was implemented and measured to demonstrate the e ﬀ ectiveness of the proposed circuit.


Introduction
Recently, renewable energies have been increasingly used to meet growing energy demands and mitigate climate change caused by the greenhouse effect due to the burning of large amounts of fossil fuels. Batteries are often used in energy storage systems to compensate the power fluctuation between renewable power generation systems and consumption [1][2][3]. Since battery voltage is usually small and has a wide range of variation, a high step-up dc/dc converter is indispensable on application where high dc voltage is required [4][5][6]. The boost converter has been widely adopted for step-up application because it has the advantages of simple circuit architecture and easy control [7,8]. Theoretically, the voltage gain of a boost converter is tremendous high when its duty ratio is close to 1. Under ideal conditions, the value of the voltage gain at the 0.9 duty cycle is equal to 10. Nevertheless, it is impractical to operate a boost converter at such a high duty cycle, because when the resistance of the inductor and the semiconductor device is considered in the actual circuit, both the circuit efficiency and the voltage gain will be greatly reduced [9]. On the other hand, the voltage gain of a boost converter operating at discontinuous-conduction mode (DCM) is higher than that of a boost converter operating at continuous-conduction mode (CCM). A DCM operated boost converter could provide a reasonable solution for achieving high voltage gain. Nevertheless, a smaller inductor is used at DCM operation Figure 1 shows the proposed interleaved dc/dc converter. It is mainly composed of two boost converters where the coupled inductor (T 1 ) served as the energy-stored inductor. The coupled inductor is made up of a magnetic core and two windings with the same number of turns. Two MOSFETs (S 1 , S 2 ) play the role of active switches. Two diodes (D 1 , D 2 ) are used to freewheel the inductor current while the other two diodes (D S1 , D S2 ) respectively in parallel with S 1 and S 2 are the intrinsic diodes of the MOSFETs. The gate-source voltages (v GS1 , v GS2 ) are used to alternatively turn the active switches on and off at a high switching frequency f s . The waveforms of v GS1 and v GS2 are shown in Figure 2. They are complementary rectangular waveforms with a short overlap time between them. Appl. Sci. 2020, 3, x FOR PEER REVIEW 3 of 12 Ignoring the winding resistance and the core loss, the equivalent circuit of the coupled inductor is shown in Figure 3. TM is a transformer with a turn ratio equal to 1, and LM is its mutual inductance. L1 and L2 represent the leakage inductances in the primary winding and the secondary ones, respectively. Based on the equivalent circuit, the currents flowing into L1 and L2, denoted by iL1 and iL2 can be expressed as where iT1, iT2, and iLM are the primary current, the secondary current and the magnetic exciting current of the transformer, respectively. From Figure 1, the input current denoted by iin would be equal the sum of iL1 and iL2. Based on Equations (1) and (2), iin is equal to the magnetic exciting current.
The voltages across both windings of the transformer are equal and can be expressed as:

Circuir Analysis
In order to simplify the circuit analysis, some assumptions are made as follows. Ignoring the winding resistance and the core loss, the equivalent circuit of the coupled inductor is shown in Figure 3. TM is a transformer with a turn ratio equal to 1, and LM is its mutual inductance. L1 and L2 represent the leakage inductances in the primary winding and the secondary ones, respectively. Based on the equivalent circuit, the currents flowing into L1 and L2, denoted by iL1 and iL2 can be expressed as where iT1, iT2, and iLM are the primary current, the secondary current and the magnetic exciting current of the transformer, respectively. From Figure 1, the input current denoted by iin would be equal the sum of iL1 and iL2. Based on Equations (1) and (2), iin is equal to the magnetic exciting current.
The voltages across both windings of the transformer are equal and can be expressed as:

Circuir Analysis
In order to simplify the circuit analysis, some assumptions are made as follows. Ignoring the winding resistance and the core loss, the equivalent circuit of the coupled inductor is shown in Figure 3. T M is a transformer with a turn ratio equal to 1, and L M is its mutual inductance. L 1 and L 2 represent the leakage inductances in the primary winding and the secondary ones, respectively. Based on the equivalent circuit, the currents flowing into L 1 and L 2 , denoted by i L1 and i L2 can be expressed as where i T1 , i T2 , and i LM are the primary current, the secondary current and the magnetic exciting current of the transformer, respectively. From Figure 1, the input current denoted by i in would be equal the sum of i L1 and i L2 . Based on Equations (1) and (2), i in is equal to the magnetic exciting current. Ignoring the winding resistance and the core loss, the equivalent circuit of the coupled inductor is shown in Figure 3. TM is a transformer with a turn ratio equal to 1, and LM is its mutual inductance. L1 and L2 represent the leakage inductances in the primary winding and the secondary ones, respectively. Based on the equivalent circuit, the currents flowing into L1 and L2, denoted by iL1 and iL2 can be expressed as where iT1, iT2, and iLM are the primary current, the secondary current and the magnetic exciting current of the transformer, respectively. From Figure 1, the input current denoted by iin would be equal the sum of iL1 and iL2. Based on Equations (1) and (2), iin is equal to the magnetic exciting current.
The voltages across both windings of the transformer are equal and can be expressed as:

Circuir Analysis
In order to simplify the circuit analysis, some assumptions are made as follows. The voltages across both windings of the transformer are equal and can be expressed as: Appl. Sci. 2020, 10, 2167 4 of 12

Circuir Analysis
In order to simplify the circuit analysis, some assumptions are made as follows.
• The semiconductor devices are ideal in spite of considering the intrinsic diode and the parasitic capacitance of the MOSFETs.

•
The leakage inductances are equal (L 1 = L 2 = L l ). The mutual inductance L M is large enough and the magnetic exciting current i LM is constant.

•
The output capacitance C o is large enough. Hence, the output voltage V o is regarded as constant.
Accorrding the conducting status of the semiconductor devices, there are eigth operation modes in one high-frequency cycle at steady-state operation. Figure 4 shows the current loops for each operation mode and Figure 5 illustrates the conceptual voltage and current waveforms of the main components. Accorrding the conducting status of the semiconductor devices, there are eigth operation modes in one high-frequency cycle at steady-state operation. Figure 4 shows the current loops for each operation mode and Figure 5 illustrates the conceptual voltage and current waveforms of the main components.
D2 iD2  Appl. Sci. 2020, 3, x FOR PEER REVIEW 5 of 12 Before the beginning of Mode I, both active switches S1 and S2 are on. There are two current loops. One is iL1 flows through S1. The other is iL2 flows through S2. Since S2 is turned on before S1, most of the magnetic exciting iLM are supplied by iL2.
Mode I starts at the instant when vGS2 drops to zero volts to turn off S2. The equivalent circuit is shown in Figure 4a. The current in the secondary winding iL2 diverts from S2 to flow into its parasitic capacitance CDS2. Since the parasitic capacitance is generally very small, it takes a very short time for the voltage across CDS2 being charged to equal the output voltage Vo. Thereafter, iL2 diverts from CDS2 to flow through D2 and the output capacitance Co. During this period, Co is charged. The voltage equations of the two converters are as follows. A. Mode I (t 0 < t < t 1 ) Before the beginning of Mode I, both active switches S 1 and S 2 are on. There are two current loops. One is i L1 flows through S 1 . The other is i L2 flows through S 2 . Since S 2 is turned on before S 1 , most of the magnetic exciting i LM are supplied by i L2 .
Mode I starts at the instant when v GS2 drops to zero volts to turn off S 2 . The equivalent circuit is shown in Figure 4a. The current in the secondary winding i L2 diverts from S 2 to flow into its parasitic capacitance C DS2 . Since the parasitic capacitance is generally very small, it takes a very short time for the voltage across C DS2 being charged to equal the output voltage V o . Thereafter, i L2 diverts from C DS2 to flow through D 2 and the output capacitance C o . During this period, C o is charged. The voltage equations of the two converters are as follows.
where v L1 and v L2 represent the voltages across the leakage inductances L 1 and L 2 , respectively. Adding Equations (5) and (6) gives From Equation (3), the following equation is obtained.
The voltage across the mutual inductance can be obtained by substituting Equations (4) and (8) into Equation (7).
By designing V o to be higher than two times of V in , v T would be negative and i LM would decrease linearly in this mode. The voltages across the leakage inductances can be expressed as Equations (10) and (11) by substituting Equation (9) into Equations (5) and (6), respectively.
From Equations (10) and (11), v L1 is positive and v L2 is negative since L m is much larger than L l . Hence, i L1 rises and i L2 decreases linearly. It means that the magnetic exciting current diverts form the secondary winding to the primary winding. As soon as i L2 decreases to zero, D 2 turns off and the circuit operation enters Mode II.

B. Mode II (t 1 < t < t 2 )
This mode describes the short transient for the C DS2 discharging from V o to −0.7 V. The equivalent circuit is shown in Figure 4b. During this mode, the voltage across L 2 can be expressed as The voltage v L2 is negative and i L2 continuously decreases from zero. In other words, i L2 changes polarity and becomes negative. The current loop of i L2 is C DS2 , the secondary winding, V in . The voltages v L1 , v L2 and v T are expressed as Appl. Sci. 2020, 10, 2167 7 of 12 During this mode, C DS2 is discharged and v DS2 keeps decreasing. From Equations(13) - (15), v L1 decreases. On the contrary, v L2 and v T both increase. As soon as v DS2 decreases to −0.7 V, i L2 diverts from C DS2 to D S2 and Mode II ends.
The equivalent circuit of Mode III is shown in Figure 4c. Neglecting the diode conduction voltage (0.7 V), the voltage equations for both converters are Adding Equation (16) and Equation (17) results in Substituting Equations (4) and (8) into Equation (18) Substituting Equation (19) into Equations (16) and (17) results in From Equations (19) and (20), v T , v L1, and v L2 are all positive. Since the mutual inductance L M is usually much higher than the leakage inductance L l , the v L1 and v L2 are very small and the currents i L1 and i L2 rises slowly. During this mode, D S2 is on and the drain to source voltage of S 2 is clamped at 0.7 V. The gated voltage v GS2 becomes high level before i L2 rises to zero. When i L2 rises to zero and then becomes positive, S 2 is turned on at ZVS and Mode III ends.

D. Mode IV (t 3 < t < t 4 )
The voltage equations for v T , v L1 , and v L2 are as same as that of Mode III. The voltages v T , v L1 , and v L2 are all positive. Therefore, the currents i LM , i L1 , and i L2 keep rising. When the gated voltage v GS1 becomes zero volts. S 1 is turned off and the circuit enters Mode V.
The equivalent circuits of Mode V to Mode VIII are shown in Figure 4e-h, respectively. Owing to the symmetrical operation for both boost converters, the operation of Mode V -Mode VIII is similar to the operation of Mode I-Mode IV. As soon as v GS2 drops zero, S 2 is turned off and Mode VIII ends. The circuit goes to the first mode of the next high frequency cycle.

Design Equations
Since the mutual inductance L M is large enough, I LM is assumed to be constant. Based on the principle of energy conservation, the output power is equal to where η represents the circuit conversion efficiency. From (21), I LM can be expressed as By assuming that the mutual inductance L M is much larger than the leakage inductance L l , from Equations (9)- (11), v T , v L1 , and v L2 in Mode I are approximately equal to In practical circuits, parasitic capacitors are very small. It takes only a short time to fully discharge the parasitic capacitor. It means that the period of Mode II is very short and hence i L2 is near zero at the end of this mode. Based on Equation (3), the peak value of i L2 is approximately equal to I LM . In Mode I, i L2 decreases and the time required for the current i L2 to drop from its maximum value to zero is equal to The voltage equations for v T in Mode I and in Mode III and Mode IV are Equations (9) and (19), respectively. At steady state, its average value should be zero.
where t f is the period of Mode I and t r is that of Mode III plus Mode IV. The fall time t f plus the rise time t r equals to half of the switching period where T s represents the switching period. Combining Equations (27) and (28) gets Substituting Equation (29) into Equation (26) gets Combining Equations (22) and (30), the leakage inductance is obtained as

Illustrative Example and Experimental Results
A 200 W prototype was built and tested to verify the feasibility of the proposed circuit. The circuit specification is shown in Table 1 and the values of the circuit component are shown in Table 2. The input and output voltages are 48V dc and 400V dc , respectively. The switching frequency of 50 kHz is chosen. From Equation (31), the output power is inverse proportional to leakage inductance L l . Assuming a circuit efficiency of 95%, L l can be obtained.
2V o 2 f s = 0.95 × 48 2 2 × 200 × 50 × 10 3 = 0.11 mH The control circuit is illustrated in Figure 6. It includes a half-bridge self-oscillating driver (IR2153), two inverters (74LS04P) and two power metal-oxide-semiconductor field-effect transistor (MOSFET) gate drivers (TLP250). The IR2153 provides two complementary square voltages with dead time between them. After being inverted by 74LS04P, the output becomes two square voltages with overlapping times. Finally, the overlapping voltages are sent to the TLP250 and their outputs are used to drive the MOSFETs.
The waveforms of the gate voltages, vDS1 and vDS2 are shown in Figure 7. As shown, there are overlapping time between them. Figure 8 shows the current waveforms in the primary and the secondary windings of the coupled inductor. As expected, both currents decrease from the peak value to a negative value near zero. The current and voltage waveforms of the active switches are shown in Figure 9. It demonstrates that both active switches are operated at ZVS. The drain-to-source voltages of S1 and S2 are clamped at 0.7 V when the current is negative. It is believed that the negative currents flow through the intrinsic diodes of S1 and S2. The output voltage and output current are shown in Figure 10. The measured voltage and current are 400V and 0.5A, consistent with the theoretical prediction. The measured circuit efficiency is 94.3%. C3D10060A Active switches S1, S2 35N65M5 Figure 6. Control circuit. Figure 6. Control circuit.
The waveforms of the gate voltages, v DS1 and v DS2 are shown in Figure 7. As shown, there are overlapping time between them. Figure 8 shows the current waveforms in the primary and the secondary windings of the coupled inductor. As expected, both currents decrease from the peak value to a negative value near zero. The current and voltage waveforms of the active switches are shown in Figure 9. It demonstrates that both active switches are operated at ZVS. The drain-to-source voltages of S 1 and S 2 are clamped at 0.7 V when the current is negative. It is believed that the negative currents flow through the intrinsic diodes of S 1 and S 2 . The output voltage and output current are shown in Figure 10. The measured voltage and current are 400V and 0.5A, consistent with the theoretical prediction. The measured circuit efficiency is 94.3%.    and iS1, and (b) vDS2 and iS2. (vDS1, vDS2: 200 V/div, iS1, iS2: 2 A/div, time: 5 μs/div)

Conclusions
This paper proposes an interleaved dc/dc converter that is composed of two boost converters. Both boost converters share a coupled inductor that is made up of one magnetic core with two windings. It effectively reduces the product size and cost. Owing to the interleaved operation, the

Conclusions
This paper proposes an interleaved dc/dc converter that is composed of two boost converters. Both boost converters share a coupled inductor that is made up of one magnetic core with two windings. It effectively reduces the product size and cost. Owing to the interleaved operation, the power capacity is doubled. Moreover, low current ripple at both the input and the output sides is achieved due to the interleaved operation. By operating the boost converters at DCM, the freewheeling diodes and the active switches can respectively fulfill ZCS operation and ZVS operation, without the need to use any active clamping or snubber circuits. It helps to reduce the component count and improve the circuit efficiency. In summary, the proposed interleaved converter has the advantages of less component count, low current ripple, high circuit efficiency, and easy control. A 200 W prototype converter was implemented and measured. The circuit efficiency is 94.3% at rated power operation.