Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-E ﬀ ect Transistors (NWTFETs)

: The hump behavior of gate-normal nanowire tunnel ﬁeld-e ﬀ ect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing ( SS ) and on-current ( I on ) because the corners and sides of nanowires (NWs) have di ﬀ erent surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature ( R ) of NWs and reducing gate insulator thickness ( T ins ).


Introduction
The aggressive downscaling of metal oxide semiconductor field-effect transistors (MOSFETs) has raised some problems regarding the off-current (I off ) and supply voltage [1]. A tunnel field-effect transistor (TFET) has been considered as one of the most promising candidates for extremely low-power applications thanks to its low I off and abrupt on-off switching [2,3]. However, TFETs suffer from low on-current (I on ) [4]. For higher I on , several strategies have been proposed: the introduction of low bandgap materials [5], and hetero-gate-dielectric (HG) [6] and hetero-material-gate (HMG) structures [7]. Additionally, gate-normal TFETs were proposed to boost I on by increasing the tunneling cross-sectional area [8][9][10][11]. The band-to-band tunneling (BTBT) generation of gate-normal TFETs occurs perpendicular to the channel in the gate-source overlap region. Thus, the gate-normal tunneling area can be enlarged by increasing the gate-source overlap length (L ov ) to increase I on .
Recently, silicon nanowire (SiNW) TFETs have been developed for superior subthreshold swing (SS), I off , and short-channel-effect immunity [12,13]. The fabrication of SiNW TFETs using a top-down process has great advantages in terms of being a reproducible process, having compatibility with CMOS and having good control over the dimensions, while a bottom-up process has been seriously limited due to a difficulty in the fabrication process [14][15][16]. In this manuscript, as shown in Figure 1, gate-normal NWTFETs are discussed, which combine the advantages of gate-normal TFETs and NWFETs. One of the most serious problems of gate-normal NWTFETs is the hump behavior stemming from the three-dimensional corner effect: the surface potentials are different between the corner and side of an NW. This means that different BTBT turn-on voltages exist in an NW, which induces the hump behavior of degrading SS and I on [17]. Thus, it is necessary to suppress the corner effect of gate-normal NWTFETs. There are several studies on the hump behavior of TFETs and various methods of mitigating hump behavior [18][19][20][21]. However, this study discusses the hump behavior originated from the geometrical effect of the three-dimensional NW structure. Even if many studies have been performed regarding the corner effect of NWMOSFETs [22][23][24][25], that of gate-normal NWTFETs has rarely been discussed. In this manuscript, the hump behavior of gate-normal NWTFETs is investigated and its solution is proposed by three-dimensional (3D) technology computer-aided design (TCAD) simulation. Figure 1 shows the bird's eye and cross-sectional views of gate-normal NWTFETs. It features a gate-source overlapped thin intrinsic epitaxial layer to fix the tunnel width. The device parameters are summarized in Table 1. The channel length (Lch) is 20 nm. The gate-source overlap length (Lov) is 40 nm. Both the inner width (Winner) and inner height (Hin ner) are 20 nm, respectively. The gate insulator thickness (Tins) is 2 nm. The epi-layer thickness (Tepi) is 2 nm. The source (NS) and drain doping concentrations (ND) are 10 20 cm -3 , respectively.

Device Structure and Simulation Methodology
3D TCAD device simulation has been performed by using a commercial simulator [26]. For the accurate calculation of the BTBT generation rate, a dynamic nonlocal BTBT model is used after calibration [27]. Additionally, the Shockley-Read-Hall recombination, Philips unified mobility model and Fermi distribution are used in our simulation. On the contrary, quantization effects and the gate leakage current have not been considered. The threshold voltage (VT) is defined as the gate voltage (VG) when the drain current (ID) is equal to 0.1 nA/μm, while the turn-on voltage (Vturn-on) is defined as VG when ID is equal to 0.01 fA/μm. The Ion and Ioff are defined as ID when the overdrive voltages (VG -Vturn-on) are 0.5 V and −0.2 V, respectively. The average SS (SSavg) is calculated from VG = Vturn-on to VG = Vturn-on + 0.5 V. Drain-induced barrier thinning (DIBT) is calculated as the VT difference between VD = 0.05 V and 0.5 V.  In this manuscript, the hump behavior of gate-normal NWTFETs is investigated and its solution is proposed by three-dimensional (3D) technology computer-aided design (TCAD) simulation. Figure 1 shows the bird's eye and cross-sectional views of gate-normal NWTFETs. It features a gate-source overlapped thin intrinsic epitaxial layer to fix the tunnel width. The device parameters are summarized in Table 1. The channel length (L ch ) is 20 nm. The gate-source overlap length (L ov ) is 40 nm. Both the inner width (W inner ) and inner height (H in ner ) are 20 nm, respectively. The gate insulator thickness (T ins ) is 2 nm. The epi-layer thickness (T epi ) is 2 nm. The source (N S ) and drain doping concentrations (N D ) are 10 20 cm -3 , respectively. 3D TCAD device simulation has been performed by using a commercial simulator [26]. For the accurate calculation of the BTBT generation rate, a dynamic nonlocal BTBT model is used after calibration [27]. Additionally, the Shockley-Read-Hall recombination, Philips unified mobility model and Fermi distribution are used in our simulation. On the contrary, quantization effects and the gate leakage current have not been considered. The threshold voltage (V T ) is defined as the gate voltage (V G ) when the drain current (I D ) is equal to 0.1 nA/µm, while the turn-on voltage (V turn-on ) is defined as V G when I D is equal to 0.01 fA/µm. The I on and I off are defined as I D when the overdrive voltages (V G − V turn-on ) are 0.5 V and −0.2 V, respectively. The average SS (SS avg ) is calculated from V G = V turn-on to V G = V turn-on + 0.5 V. Drain-induced barrier thinning (DIBT) is calculated as the V T difference between V D = 0.05 V and 0.5 V. Figure 2 shows the simulated transfer curves of the gate-normal NWTFETs, which show clear hump behavior degrading SS and I on . Two noteworthy phenomena are observed. First, hump behavior occurs and the SS is abruptly changed around V G = 0.7 V. In order to analyze the hump behavior, the electron BTBT generation rates in the gate-source overlap region are simulated at around V G = 0.7 V at V D = 0.5 V. As shown in Figure 3, gate-normal BTBT occurs at the corners earlier than at the sides, which is called the corner effect. To be specific, the area wherein BTBT occurs is extended from the corner to the side as V G increases. In addition, the electron BTBT generation rate is not constant through the NW, and is stronger at the corner. This means that different BTBT turn-on voltages exist in an NW, which induce the hump behavior. Second, as shown in Figure 2, the hump becomes more severe as V D decreases. At low V D , it is vulnerable to the hump because the influence of the gate increases as the V D decreases, while the hump is more affected by the structure of the gate.

Analysis of Hump Behavior of Gate-Normal NWTFETs
Appl. Sci. 2020, 10, 8880 3 of 11 Figure 2 shows the simulated transfer curves of the gate-normal NWTFETs, which show clear hump behavior degrading SS and Ion. Two noteworthy phenomena are observed. First, hump behavior occurs and the SS is abruptly changed around VG = 0.7 V. In order to analyze the hump behavior, the electron BTBT generation rates in the gate-source overlap region are simulated at around VG = 0.7 V at VD = 0.5 V. As shown in Figure 3, gate-normal BTBT occurs at the corners earlier than at the sides, which is called the corner effect. To be specific, the area wherein BTBT occurs is extended from the corner to the side as VG increases. In addition, the electron BTBT generation rate is not constant through the NW, and is stronger at the corner. This means that different BTBT turnon voltages exist in an NW, which induce the hump behavior. Second, as shown in Figure 2, the hump becomes more severe as VD decreases. At low VD, it is vulnerable to the hump because the influence of the gate increases as the VD decreases, while the hump is more affected by the structure of the gate.  The definition of the corner and side of an NW is shown in Figure 4. Because the tunneling width is determined by the epi-layer thickness (T epi ), gate-normal tunneling occurs mainly in the epi-layer [28]. Thus, by integrating electron BTBT generation rates over the cross-section of an NW, electron BTBT generation rates per channel length are calculated. In order to evaluate the influence of the corners on I D , the electron BTBT generation rates at the corners and sides are compared with each other. Figure 5 shows that gate-normal tunneling occurs first in the corner region and then in the side region of an NW. The corner effect is dominant at a low V G while it becomes less strong as V G increases. Thus, it degrades the on-off transition abruptness of the total electron BTBT generation rates. Figure 6a shows the 2D contour of electrostatic potential. As shown in Figure 6b,c, the surface potential is higher at the corner than at the side in the entire range of V G . This is because the charge at the corner is shared by the surrounding gate. The charge sharing effect at the corner contributes to the higher surface potential compared with the side one [29,30]. The difference in surface potentials in an NW affects the energy band diagrams of gate-normal NWTFETs. Figure 7 shows the energy band diagrams extracted, Appl. Sci. 2020, 10, 8880 4 of 9 at the corner and side, from the middle of the gate-source overlap region, respectively. Gate-normal tunneling, which is a main current mechanism of the gate-normal NWTFETs, occurs vertically in the gate-source overlap region, whereas the current is conducted laterally along the gate-controlled surface channel [10]. Then, in order to induce gate-normal tunneling, the band alignment in the direction perpendicular to the channel in the gate-source overlap region should be required [28]. When the V G is 0.6 V, the conduction energy band edge (E C ) of the epi-layer is aligned with the valence energy band edge (E V ) of the source region at the corner, while the E C of the epi-layer is not aligned with the E V of the source region at the side. This is because the higher surface potential of the corner leads the energy band of the surface to shift down, which causes the gate-normal tunneling to turn on early. Thus, the corner and side of an NW have different BTBT turn-on voltages, which induce the hump behavior. The definition of the corner and side of an NW is shown in Figure 4. Because the tunneling width is determined by the epi-layer thickness (Tepi), gate-normal tunneling occurs mainly in the epi-layer [28]. Thus, by integrating electron BTBT generation rates over the cross-section of an NW, electron BTBT generation rates per channel length are calculated. In order to evaluate the influence of the corners on ID, the electron BTBT generation rates at the corners and sides are compared with each other. Figure 5 shows that gate-normal tunneling occurs first in the corner region and then in the side region of an NW. The corner effect is dominant at a low VG while it becomes less strong as VG increases. Thus, it degrades the on-off transition abruptness of the total electron BTBT generation rates. Figure 6a shows the 2D contour of electrostatic potential. As shown in Figure 6b,c, the surface potential is higher at the corner than at the side in the entire range of VG. This is because the charge at the corner is shared by the surrounding gate. The charge sharing effect at the corner contributes to the higher surface potential compared with the side one [29,30]. The difference in surface potentials in an NW affects the energy band diagrams of gate-normal NWTFETs. Figure 7 shows the energy band diagrams extracted, at the corner and side, from the middle of the gate-source overlap region, respectively. Gate-normal tunneling, which is a main current mechanism of the gate-normal NWTFETs, occurs vertically in the gate-source overlap region, whereas the current is conducted laterally along the gate-controlled surface channel [10]. Then, in order to induce gate-normal tunneling, the band alignment in the direction perpendicular to the channel in the gate-source overlap region should be required [28]. When the VG is 0.6 V, the conduction energy band edge (EC) of the epi-layer is aligned with the valence energy band edge (EV) of the source region at the corner, while the EC of the epi-layer is not aligned with the EV of the source region at the side. This is because the higher surface potential of the corner leads the energy band of the surface to shift down, which causes the gate-normal tunneling to turn on early. Thus, the corner and side of an NW have different BTBT turn-on voltages, which induce the hump behavior.  The definition of the corner and side of an NW is shown in Figure 4. Because the tunneling width is determined by the epi-layer thickness (Tepi), gate-normal tunneling occurs mainly in the epi-layer [28]. Thus, by integrating electron BTBT generation rates over the cross-section of an NW, electron BTBT generation rates per channel length are calculated. In order to evaluate the influence of the corners on ID, the electron BTBT generation rates at the corners and sides are compared with each other. Figure 5 shows that gate-normal tunneling occurs first in the corner region and then in the side region of an NW. The corner effect is dominant at a low VG while it becomes less strong as VG increases. Thus, it degrades the on-off transition abruptness of the total electron BTBT generation rates. Figure 6a shows the 2D contour of electrostatic potential. As shown in Figure 6b,c, the surface potential is higher at the corner than at the side in the entire range of VG. This is because the charge at the corner is shared by the surrounding gate. The charge sharing effect at the corner contributes to the higher surface potential compared with the side one [29,30]. The difference in surface potentials in an NW affects the energy band diagrams of gate-normal NWTFETs. Figure 7 shows the energy band diagrams extracted, at the corner and side, from the middle of the gate-source overlap region, respectively. Gate-normal tunneling, which is a main current mechanism of the gate-normal NWTFETs, occurs vertically in the gate-source overlap region, whereas the current is conducted laterally along the gate-controlled surface channel [10]. Then, in order to induce gate-normal tunneling, the band alignment in the direction perpendicular to the channel in the gate-source overlap region should be required [28]. When the VG is 0.6 V, the conduction energy band edge (EC) of the epi-layer is aligned with the valence energy band edge (EV) of the source region at the corner, while the EC of the epi-layer is not aligned with the EV of the source region at the side. This is because the higher surface potential of the corner leads the energy band of the surface to shift down, which causes the gate-normal tunneling to turn on early. Thus, the corner and side of an NW have different BTBT turn-on voltages, which induce the hump behavior.

Hump Suppression by Rounding NW Corners and Reducing Gate Insulator Thickness
In order to improve the SS and Ion of the gate-normal NWTFETs, the hump behavior must be suppressed. In this paragraph the radius of curvature (R) of an NW and Tins are optimized for the suppression of the hump behavior. The normalized R (Rnorm) is defined as 2R/Winner. The three Rnorm values are discussed as shown in Figure 8: 0, 0.4, and 1. Figure 9 shows the simulated transfer curves of the gate-normal NWTFETs with various Rnorms ranging from 0 to 1. As the Rnorm increases, the hump behavior becomes weaker because the surface potential difference between the corner and side becomes smaller, as shown in Figure 10. The surface potential difference in an NW becomes 0 as Rnorm becomes 1. In addition, as the corner behavior is alleviated, the short channel behavior is suppressed down [22,23]. Thus, it is observed that the Vturn-on increases, the SSavg improves, the Ion/Ioff ratio increases, and the DIBT decreases, as shown in Figure 11. In the case of a cylindrical NW whose Rnorm is 1, the gate-normal BTBT evenly occurs on the entire surface. The gate-normal NWTFET whose Rnorm is 1 shows a twofold higher Ion and a 5.4-fold higher Ion/Ioff than that whose Rnorm is 0.

Hump Suppression by Rounding NW Corners and Reducing Gate Insulator Thickness
In order to improve the SS and I on of the gate-normal NWTFETs, the hump behavior must be suppressed. In this paragraph the radius of curvature (R) of an NW and T ins are optimized for the suppression of the hump behavior. The normalized R (R norm ) is defined as 2R/W inner . The three R norm values are discussed as shown in Figure 8: 0, 0.4, and 1. Figure 9 shows the simulated transfer curves of the gate-normal NWTFETs with various R norm s ranging from 0 to 1. As the R norm increases, the hump behavior becomes weaker because the surface potential difference between the corner and side becomes smaller, as shown in Figure 10. The surface potential difference in an NW becomes 0 as R norm becomes 1. In addition, as the corner behavior is alleviated, the short channel behavior is suppressed down [22,23]. Thus, it is observed that the V turn-on increases, the SS avg improves, the I on /I off ratio increases, and the DIBT decreases, as shown in Figure 11. In the case of a cylindrical NW whose R norm is 1, the gate-normal BTBT evenly occurs on the entire surface. The gate-normal NWTFET whose R norm is 1 shows a twofold higher I on and a 5.4-fold higher I on /I off than that whose R norm is 0.
values are discussed as shown in Figure 8: 0, 0.4, and 1. Figure 9 shows the simulated transfer curves of the gate-normal NWTFETs with various Rnorms ranging from 0 to 1. As the Rnorm increases, the hump behavior becomes weaker because the surface potential difference between the corner and side becomes smaller, as shown in Figure 10. The surface potential difference in an NW becomes 0 as Rnorm becomes 1. In addition, as the corner behavior is alleviated, the short channel behavior is suppressed down [22,23]. Thus, it is observed that the Vturn-on increases, the SSavg improves, the Ion/Ioff ratio increases, and the DIBT decreases, as shown in Figure 11. In the case of a cylindrical NW whose Rnorm is 1, the gate-normal BTBT evenly occurs on the entire surface. The gate-normal NWTFET whose Rnorm is 1 shows a twofold higher Ion and a 5.4-fold higher Ion/Ioff than that whose Rnorm is 0.      Another way to suppress the hump behavior is to reduce the Tins. Figure 12 shows the simulated transfer curves with various Tinss. As Tins decreases, that hump is suppressed and the SS is improved because the gate's controllability over the channel becomes better. The surface potential on the gatesource overlap region increases as the Tins decreases. However, as shown in Figure 13a, the potential at the side becomes higher than that at the corner as the Tins decreases. It should be noted that the potential at the corner is less sensitive to Tins than that at the side because the corners of an NW are surrounded by the gate [17]. Thus, as shown in Figure 13b, the surface potential difference between the corner and side decreases as the Tins decreases. In other words, the difference in BTBT turn-on voltages in an NW is reduced, which means less hump behavior.  Another way to suppress the hump behavior is to reduce the T ins . Figure 12 shows the simulated transfer curves with various T ins s. As T ins decreases, that hump is suppressed and the SS is improved because the gate's controllability over the channel becomes better. The surface potential on the gate-source overlap region increases as the T ins decreases. However, as shown in Figure 13a, the potential at the side becomes higher than that at the corner as the T ins decreases. It should be noted that the potential at the corner is less sensitive to T ins than that at the side because the corners of an NW are surrounded by the gate [17]. Thus, as shown in Figure 13b, the surface potential difference between the corner and side decreases as the T ins decreases. In other words, the difference in BTBT turn-on voltages in an NW is reduced, which means less hump behavior. Another way to suppress the hump behavior is to reduce the Tins. Figure 12 shows the simulated transfer curves with various Tinss. As Tins decreases, that hump is suppressed and the SS is improved because the gate's controllability over the channel becomes better. The surface potential on the gatesource overlap region increases as the Tins decreases. However, as shown in Figure 13a, the potential at the side becomes higher than that at the corner as the Tins decreases. It should be noted that the potential at the corner is less sensitive to Tins than that at the side because the corners of an NW are surrounded by the gate [17]. Thus, as shown in Figure 13b, the surface potential difference between the corner and side decreases as the Tins decreases. In other words, the difference in BTBT turn-on voltages in an NW is reduced, which means less hump behavior.

Conclusions
The hump behavior of gate-normal NWTFETs is analyzed by using 3D TCAD simulation. It is discussed that the hump originates from the corner effect induced by the surrounding gate. BTBT occurs at the corner earlier than at the side due to the higher surface potential at the corner. By increasing R norm and decreasing T ins , the hump behavior can be suppressed. Cylindrical gate-normal NWTFETs with low T ins are recommended for extremely low-power applications.