A Voltage Multiplier Circuit Based Quadratic Boost Converter for Energy Storage Application

: In this paper, a new transformerless high voltage gain dc-dc converter is proposed for low and medium power application. The proposed converter has high quadratic gain and utilizes only two inductors to achieve this gain. It has two switches that are operated simultaneously, making control of the converter easy. The proposed converter’s output voltage gain is higher than the conventional quadratic boost converter and other recently proposed high gain quadratic converters. A voltage multiplier circuit (VMC) is integrated with the proposed converter, which signiﬁcantly increases the converter’s output voltage. Apart from a high output voltage, the proposed converter has low voltage stress across switches and capacitors, which is a major advantage of the proposed topology. A hardware prototype of 200 W of the proposed converter is developed in the laboratory to validate the converter’s performance. The e ﬃ ciency of the converter is obtained through PLECS software by incorporating the switching and conduction losses.


Introduction
High gain dc to dc converters have increasingly become popular due to their suitability in solar Photovoltaic (PV) systems, electric vehicles, and HVDC transmission systems. The output voltage from solar PV modules, fuel cells, and batteries is generally low and needs to be boosted up to maintain the dc-link voltage at the inverter's input. Conventional boost converters suffer from high voltage stress across the switch, low gain, and poor efficiency at higher duty ratios [1]. The high gain dc-dc boost converter uses a combination of inductors, capacitors, diodes, and switches to transfer the power between capacitors and inductors to increase the output voltage. These converters use various combinations, such as voltage multiplier cells (VMCs), coupled inductors, switched capacitors, and switched inductors to increase the output voltage. Each of these techniques has its own merits and demerits [1]. Many topologies utilizing different strategies to increase the output voltage are reported in the literature.
Moreover, the challenge is to keep the number of components in the converter low to decrease the cost and increase the converter's efficiency. The dc-dc converter's isolated topologies are used in low (1) The voltage gain is higher than the conventional quadratic boost converter (CQBC) [18], and twice the quadratic boost converter (TCQBC) proposed in [30]. The voltage gain of more than 10 times can be achieved for the duty of less than 0.5. (2) The voltage stress across switches of the proposed converter is much less than the output voltage V o, which is an improvement over the quadratic converters proposed in [18,30] in which the voltage stress is equal to V o . Moreover, the diodes and capacitors also have low voltage stress, leading to the selection of low voltage rating devices and subsequently improving the converter's efficiency. (3) To achieve this high voltage gain, the coupled inductor is not used, and hence the problem of leakage inductance and the need for a snubber circuit is avoided. (4) The input current is continuous, which is another significant advantage of the proposed topology. (5) The control of the proposed converter is easy, as two switches are turned ON and OFF simultaneously.
In Section 2 the structure and working of the proposed converter is discussed. In Section 3 losses in the converter and non-ideal gain of the converter are shown. In Section 4 comparison of the proposed converter with other converters are shown. In Sections 5 and 6, hardware results and conclusions are discussed.

Structure
The circuit of CQBC and TCQBC are shown in Figure 1a,b. It can be seen that both these converters use two inductors, but their gain is less than the proposed topology. The switch is also directly connected across the load, which makes the voltage stress across the switch equal to output voltage V O . The proposed converter structure is presented in Figure 1c with a voltage multiplier cell, which increases the output voltage gain. Two Inductors (L 1 and L 2 ), four diodes (D 1 , D 2 , D 3 , D 4 ), four capacitors (C 1 , C 2 , C 3, and C 4 ), and two switches (S 1 and S 2 ) are used to realize the proposed converter. This VMC can also be placed before diode D 1, but the voltage gain would not be that high, as in the converter case presented in Figure 1c. One more configuration is also possible in which the VMC is placed at two points before diode D 1 and before diode D 4 . This increases the voltage gain further but makes the circuit more complex and less efficient.
The VMC integration increases the output voltage and reduces the voltage stress on the diodes and switches with respect to the output voltage. This VMC can also be placed before diode D 1, but the voltage gain would not be that high, as in the converter case presented in Figure 1c. One more configuration is also possible in which the VMC is placed at two points before diode D 1 and before diode D 4 . This increases the voltage gain further but makes the circuit more complex and less efficient. (a)

Working
Mode 1: In this mode, both the switches are ON, and diode D3 conducts. This interval exists for a time interval of DT where D is the duty ratio, and T is the time period. The equivalent circuit for the first mode of operation is shown in Figure 2. During the first mode of operation, the inductor L1 is energized by the capacitor C1, and the charge of the capacitor C1 decreases during the first mode of operation, as shown in Figure 3. While the DC supply energizes inductor L2, capacitor C2 discharges into C3, and the energy of capacitor C4 is transferred to the load.

Working
Mode 1: In this mode, both the switches are ON, and diode D 3 conducts. This interval exists for a time interval of DT where D is the duty ratio, and T is the time period. The equivalent circuit for the first mode of operation is shown in Figure 2. During the first mode of operation, the inductor L 1 is energized by the capacitor C 1, and the charge of the capacitor C 1 decreases during the first mode of operation, as shown in Figure 3. While the DC supply energizes inductor L 2 , capacitor C 2 discharges into C 3, and the energy of capacitor C 4 is transferred to the load.   The related equations during the first mode of operation are as follows: Mode 2: When both the switches are turned off during the second mode of operation, the diode D1, D2, and D4 are conducting while diode D3 is reversed biased. During the second mode of operation, the capacitor C1 is charged by the DC power supply, the energy of the inductors is transferred to the capacitor C2 while the capacitor C3 charges C4. The equivalent circuit for the second mode of operation is shown in Figure 4. The related equations are as follows: The related equations during the first mode of operation are as follows: Mode 2: When both the switches are turned off during the second mode of operation, the diode D 1 , D 2 , and D 4 are conducting while diode D 3 is reversed biased. During the second mode of operation, the capacitor C 1 is charged by the DC power supply, the energy of the inductors is transferred to the capacitor C 2 while the capacitor C 3 charges C 4 . The equivalent circuit for the second mode of operation is shown in Figure 4. The related equations are as follows: Appl. Sci. 2020, 10, x FOR PEER REVIEW 6 of 16

Now applying volt-sec balance in inductor
Now applying volt-sec balance in inductor L 1 After combining the above equations, the voltage gain (M) of the converter can be written as: The voltage across the capacitors are as follows: For the continuous mode of operation, the value of the inductors and capacitors should be selected as follows

Voltage and Current Stress across Components
The voltage and current stress across the switches and diodes are presented in Table 1. The voltage across the diode and switches is lower than the output voltage, which is not valid in the conventional quadratic boost converter. The selection of the lower rating components means a reduction in the manufacturing cost.

Bifurcation of Losses
The bifurcation of losses at 45 W is shown in Figure 5a. Switches and diodes constitute more than 60% of the total losses. Loss analysis is done in PLECS software by developing a converter's thermal model and putting the switching and conduction loss data in the look-up table from the datasheet. The converter's efficiency is 92.6% at 45 W and 12 V. From Figure 5b, as Vin increases, the converter's maximum efficiency improves substantially. This is because at higher input voltages, a small duty ratio is required to get the same amount of voltage gain, and hence conduction losses are significantly reduced. Higher input voltage leads to lower current in the circuit for the same output voltage, improving efficiency by reducing the conduction losses.

Bifurcation of Losses
The bifurcation of losses at 45 W is shown in Figure 5a. Switches and diodes constitute more than 60% of the total losses. Loss analysis is done in PLECS software by developing a converter's thermal model and putting the switching and conduction loss data in the look-up table from the datasheet. The converter's efficiency is 92.6% at 45 W and 12 V. From Figure 5b, as Vin increases, the converter's maximum efficiency improves substantially. This is because at higher input voltages, a small duty ratio is required to get the same amount of voltage gain, and hence conduction losses are significantly reduced. Higher input voltage leads to lower current in the circuit for the same output voltage, improving efficiency by reducing the conduction losses.

Non-Ideal Gain
Using the principle of energy conservation, the proposed converter's non-ideal gain with parasitic inductor resistance can be derived as follows.

Non-Ideal Gain
Using the principle of energy conservation, the proposed converter's non-ideal gain with parasitic inductor resistance can be derived as follows.
where r L1 and r L2 are parasitic resistances of L 1 and L 2. It can be seen that the non-ideal gain depends on load resistance (R) and parasitic resistances. The variation of this gain with duty-cycle is as shown in Figure 6. As the load resistance is decreased, the voltage gain also reduces for the same value parasitic resistances.
where rL1 and rL2 are parasitic resistances of L1 and L2. It can be seen that the non-ideal gain depends on load resistance (R) and parasitic resistances. The variation of this gain with duty-cycle is as shown in Figure 6. As the load resistance is decreased, the voltage gain also reduces for the same value parasitic resistances.

Comparison with Other Recent Topologies
The comparison of the proposed converter with similar kinds of existing converters is shown in Table 2. The voltage gain of the proposed is compared with the other converters and presented in Figure 7. The proposed converter can achieve a voltage gain of 16 at a low duty ratio of around 0.6,

Comparison with Other Recent Topologies
The comparison of the proposed converter with similar kinds of existing converters is shown in Table 2. The voltage gain of the proposed is compared with the other converters and presented in Figure 7. The proposed converter can achieve a voltage gain of 16 at a low duty ratio of around 0.6, which is relatively high compared to the other converter presented in Figure 7. The converter proposed in [7] has four inductors, but its gain is much less than the proposed converter. As discussed earlier, the gain of the CQBC presented in [18] is much less than the proposed converter.
Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 16   Similarly, the converter proposed in [21] has utilized two switches, and the total number of components used in the converter is also the same as the proposed converter; still, its gain is high. The converter proposed in [30] has twice the gain as compared to CQBC, but even with three inductors and the same number of components, its gain is less than the proposed converter. The normalized voltage stress across the proposed converter switches as a function of voltage gain is plotted in Figure 8.
The voltage stress across switch S 1 is the lowest among all the topologies, and the stress across switch S 2 up to a gain of 11 times is also less than the topologies proposed [7,14,18,25,30] Appl. Sci. 2020, 10, x FOR PEER REVIEW 11 of 16

Experimental Verification of the Proposed Converter
A laboratory prototype is developed by using the power circuit board technique (PCB). The main circuit and gate driver circuit with various components are soldered on the power circuit board, as shown in Figure 9. The testing parameters are shown in Table 3, and the experimental setup is presented in Figure 10. Two power supplies are used-one for the gate driver circuit and another for the main converter circuit. The hardware prototype tested at a duty ratio of 0.4, and the results are presented in Figure 10.

Experimental Verification of the Proposed Converter
A laboratory prototype is developed by using the power circuit board technique (PCB). The main circuit and gate driver circuit with various components are soldered on the power circuit board, as shown in Figure 9. The testing parameters are shown in Table 3, and the experimental setup is presented in Figure 10. Two power supplies are used-one for the gate driver circuit and another for the main converter circuit.  Figure 9. Prototype of the proposed converter. Table 3. Specifications of the proposed converter.

Elements Specification
Input

Experimental Results at Vin = 12 V
As shown in Figure 11a, the measured output voltage is 90 volts, which is slightly lower than the ideal calculated voltage at 0.4 duty ratio and 12 volts input. It can further be observed that the inductor currents are continuous, and the converter is operating in CCM. The capacitor voltages are shown in Figure 11c. The measured voltage across capacitor C1 is 19.9 volts; for C2, it is 37.5 volts, and for C3, it is 49 volts. The voltage stress across the switches is lower than half of the output voltage. In the case of the first switch, the stress is around 20 volts and in the case of the second switch is around 35 volts, as shown in Figure 11d It can be validated from hardware results that the converter is working satisfactorily and the high voltage gain along with reduced voltage stresses. The hardware prototype tested at a duty ratio of 0.4, and the results are presented in Figure 10.

Experimental Results at V in = 12 V
As shown in Figure 11a, the measured output voltage is 90 volts, which is slightly lower than the ideal calculated voltage at 0.4 duty ratio and 12 volts input. It can further be observed that the inductor currents are continuous, and the converter is operating in CCM. The capacitor voltages are shown in Figure 11c. The measured voltage across capacitor C 1 is 19.9 volts; for C 2, it is 37.5 volts, and for C 3, it is 49 volts. The voltage stress across the switches is lower than half of the output voltage. In the case of the first switch, the stress is around 20 volts and in the case of the second switch is around 35 volts, as shown in Figure 11d It can be validated from hardware results that the converter is working satisfactorily and the high voltage gain along with reduced voltage stresses.  Figure 12 shows the experimental waveforms of the proposed converter at Vin = 20 V. The output voltage is found to be 155 V. The inductor currents are also continuous and are shown in Figure 12b. In Figure 12c, the input current is shown. The average value of input current is equal to 4.8 A. It can be observed that the input current is continuous, which is another advantage of the converter. The continuous input current is a desirable feature of this converter, especially for solar PV applications.

Experimental
Results at V in = 20 V Figure 12 shows the experimental waveforms of the proposed converter at V in = 20 V. The output voltage is found to be 155 V. The inductor currents are also continuous and are shown in Figure 12b. In Figure 12c, the input current is shown. The average value of input current is equal to 4.8 A. It can be observed that the input current is continuous, which is another advantage of the converter. The continuous input current is a desirable feature of this converter, especially for solar PV applications.   Figure 12 shows the experimental waveforms of the proposed converter at Vin = 20 V. The output voltage is found to be 155 V. The inductor currents are also continuous and are shown in Figure 12b. In Figure 12c, the input current is shown. The average value of input current is equal to 4.8 A. It can be observed that the input current is continuous, which is another advantage of the converter. The continuous input current is a desirable feature of this converter, especially for solar PV applications.

Conclusions
A voltage multiplier circuit based quadratic boost converter has been realized, and a prototype is developed for energy storage application. Comparing the proposed topology with other recently proposed boost and quadratic boost topology shows its better performance in terms of voltage gain and voltage stress across the switch for a wide range of duty cycles. Loss analysis with the converter's thermal model also shows efficiency above 91% for the entire 200 Watt input power operation. The peak efficiency of 94.5% is obtained for an input voltage of 24 Volts. The proposed converter with continuous input current would be a strong candidate for energy storage and renewable energy application.