An Improved Investigation into the Effects of the Temperature-Dependent Parasitic Elements on the Losses of SiC MOSFETs

This paper presents an improved investigation into the effects of temperature-dependent parasitic elements on the silicon carbide (SiC) MOSFET power losses. Based on the physical knowledge of MOSFET, a circuit-level loss analytical model is proposed, which takes the parasitic elements of the power devices and the stray inductances of the Printed Circuit Board (PCB) traces into consideration. The state equations derived from the equivalent circuit of each stage is solved by iteration to calculate the loss in the switching transients. In order to study the temperature characteristic completely, the key parameters needed in the calculation are extracted from power device test platform based on Agilent B1505A. The loss assessment of the proposed analytical model with varied elements has been successfully substantiated by the experimental results of a 400-V, 15-A double-pulse-test bench. Finally, some practical knowledge about loss mechanisms is given to help estimate the power losses and optimize the efficiency of power converters.


Introduction
In recent years, silicon carbide (SiC) has attracted extensive attention and has been gradually applied to power semiconductor devices due to its higher breakdown electric field, electron saturation velocity and thermal conductivity than conventional silicon (Si) materials [1][2][3][4][5]. In addition, increasing switching frequency has always been a common method to push up the power density and facilitate the miniaturization of switching converters by reducing the size of the passive components [6,7]. With a significant increase in switching speed, the effect of parasitic elements that mainly result from power semiconductor devices and PCB traces on switching performance can no longer be ignored and the losses become a crucial factor that determines the converter efficiency. Therefore, it is necessary to accurately calculate the loss of power devices and analyze the effects of the parasitic elements on it, helping designers to acquire in-depth knowledge of the switching loss mechanisms. There is considerable research in this filed. As discussed in [8], basically, investigation into loss can be classified into three categories. They are physical model, behavioral model, and analytical model (also called mathematical model).
Based on the knowledge of semiconductor physics and microelectronics, the physical model solves the characteristic expression of power devices by conducting the finite element analysis (FEA) [9][10][11][12]. Figure 1 shows a simplified physical structure of Vertical Double-diffused MOSFET (VDMOSFET) considering the discrete package. There is an internal resistance due to the gate contact. The pad parasitic inductances and the internal bonding between the carbon silicon die and the package pads, which are relevant to the package technology, contribute to the total parasitic inductance in the power device. The only viable alternative to further lower the parasitic inductances is to concurrently address the underlying package problem, using clip lead or sandwich package assembly methods to eliminate bond wires while maximizing the ratio of die area to package footprint [25]. As a unipolar device, the dynamic characteristics of SiC MOSFET are mainly determined by the charging and discharging process of the junction capacitances which are composed of oxide capacitances and depletion edge capacitances [26]. The width of depletion edge is related to the applied voltage between drain terminal and source terminal, so that the value of the junction capacitances is nonlinear. When a positive voltage applied between the gate terminal and source terminal, the depletion region gets wider towards the body, and it begins to drag the free electrons to the interface. As the density of the free holes of the body and the density of the free electrons of the interface becomes equal, the free electron layer is called the inversion layer (N channel). Based on the above knowledge, the equivalent circuit of the MOSFET is obtained, as shown in Figure 2. The junction capacitances are represented by three nonlinear capacitances connected in parallel with each internal node. The parasitic inductances in series in each terminal of the device (the gate terminal also includes the internal resistance). The channel is the key element of modeling, which determines the accuracy of the model and should be carefully considered. The equivalent of the channel in the switching transients will be thoroughly discussed in the next section.

Analysis of the Switching Transients
The switching process of the MOSFET will be studied stage by stage in this section. A double-pulse test circuit is adopted for the modeling of MOSFET switching transients, as shown in Figure 3. The input is a constant voltage source V DD and the load is a clamped-inductive load which can provide a constant current I DD . The gate signal V pulse is assumed to flip between V SS and V GG with zero rise time and fall time in the analysis. In order to investigate the switching process better, two different external gate resistances R g_on and R g_off are used in the turn-on transients and turn-off transients, respectively. Similar to the MOSFET, the freewheeling diode is modeled by two parasitic inductances L c_1 and L a_1 and a parasitic resistance R f in series with an ideal diode D f , and then in parallel with a nonlinear junction capacitance Cf. In addition to these power devices, there also are a lot of stray inductances result from the PCB traces of the power loop, which are represented by L bus1 , L bus2 , L c_2 , L a_2 , L d_2 , L g_2 and L s_2 . In order to simplify the model and the equations, some parameters are merged in the equivalent circuit. L d1 = L d_ext + L d_int , L g1 = L g_ext + L g_int and L s1 = L s_ext + L s_int are denoted as the total parasitic inductances at each terminal of the MOSFET, respectively. It should be noted that the stray inductance of the ground lead of a measuring loop is hard to quantitatively analyze and its influence on the loss assessment can be ignored. Therefore, it was not considered in this model.

Turn-On Switching Transients
Stage 1 [t0-t1] turn-on delay time: Before the gate source voltage v gs reaches the threshold voltage V th , the SiC MOSFET power device is still in the cut-off region. At this stage, the value of the drain current id is assumed to be zero. According to Figure 4a and Kirchhoff's law, the following equations are obtained: where R GG = R g_on + R g_int , L g = L g1 + L g2 . There are three independent state variables: the drain current i g , the gate-source voltage v gs and the drain-source voltage v ds . The state equations derived from above equations are shown in Appendix A Equation (A1). As the power device is not activated, there is no switching loss P sw during this period.
Stage 2 [t1-t2] current rise time: When the gate source voltage v gs goes beyond the threshold voltage V th , the conductive pass (channel) enabling the current flow begins to form. Due to the fast speed of the SiC MOSFET power device, the drain current i d surges, which generates the induced voltage across the parasitic inductances. This induced voltage deservers special attention, as it determines whether the drain current (id) will rise to its full value I DD before or after the drain-source voltage v ds drops to v gs − V th (the boundary condition between the saturation region and the ohmic region of MOSFET). If the power device works in the saturation region, the channel of the SiC MOSFET can be equivalent to a voltage-controlled current source (the relationship between the channel current i ch and gate-source voltage v gs is governed by (6)), otherwise it can be equivalent to a nonlinear resistance which is related to the junction temperature T j and the drain current i d . Both of them are discussed as follows.
where g f is trans-conductance of the SiC MOSFET, which is also nonlinear.
Appl. Sci. 2020, 10, 7192 6 of 22 Case I: The MOSFET works in the saturation region. In this situation, as shown in Figure 4b, the drain current i d consists of three parts: the channel current i ch and the current flowing through the junction capacitor C gd and C ds . The circuit equations can be expressed as: where Case II: The MOSFET works in ohmic region directly. As discussed above, the channel of MOSFET can be represented by a nonlinear resistance in this scenario. Therefore, (10) is changed to (12), and the rest remains unchanged.
A new independent state variable i d appears in this stage compared to the previous one, and the state equations derived from the above equations are shown in Appendix A Equation (A3). This stage ends when the drain current id reaches the bus current I DD . The switching loss E sw expression in this period is as follows.
However, a more appropriate switching loss analysis is to replace (13) with (14), taking into account the assumption that the junction capacitances of MOSFET are only lossless energy buffers. The discrepancy between the two types of calculation methods will be further elucidated in Section 5 with the experimental verification.
Stage 3 [t2-t3] voltage falling time I: As the current is transferred to the SiC MOSFET, the SiC Schottky Diode (SBD) becomes capable of blocking the voltage; Figure 4c shows the equivalent circuit of this stage, and the drain-source voltage v ds drops dramatically at the same time, if the case I occurs in the previous stage. The gate-source voltage v gs is maintained at the Miller Plateau, because the gate current i g is completely absorbed by the drain-source capacitance C ds without flowing to the gate-source capacitance C gs . Although SBD features zero reverse recovery current, the drain current id continues to increase since the charging current of junction capacitance C f of the SiC SBD. Therefore, (11) is replaced by (15), and the rest remains unchanged. A resonant period begins in this moment, which induced by the oscillations between L p and C f . This stage ends when drain-source voltage v ds decreases to v gs − V th . dv f There are five independent state variables: the drain current i g , the drain current i d , the gate-source voltage v gs , the drain-source voltage v ds and the free freewheeling diode voltage v f . The state equations at this stage are shown in Appendix A Equation (A4).
During this period, the two type of switching loss calculation as following: Stage 4 [t3-t4] voltage falling time II: When the drain-source voltage v ds decreases to v gs − V th , the SiC MOSFET will come out of the saturation region and get into the ohmic region. As shown in Figure 4d, the channel is equivalent to a nonlinear resistance (also called on-state resistance) in this stage. Therefore, (10) is replaced by (18). The gate-source voltage v gs breaks out of the Miller Plateau and begins to increase again. The drain-source voltage v ds drops slightly in this period, and the drain current id drops back to I DD simultaneously. The oscillations in the power loop will be damped by the stray resistance resulting from the PCB traces. In order to specify this point, a lumped resistance R stray is added in the equivalent circuit, as same as the stray inductances, to compensate for the active power consumption and (9) should be replaced by (19). Once the drain-source voltage v ds decreases to i d ·R on , this stage ends and the channel can be seen as completely conductive.
The independent state variables at this stage remain unchanged and the state equations are shown in Appendix A Equation (A5). The switching loss in this period can be calculated as: Stage 5 [t4-t5] On-State Operation: The gate current i g still continues to charge the gate-source capacitance C gs until the gate-source voltage v gs reaches the positive drive voltage V GG . The state equations and the equivalent circuit are the same as the previous stage, while the loss at this stage is considered as conduction loss E cond and can be calculated as:

Turn-Off Switching Transients
It is known that the turn-off switching transients are a reversely symmetrical process of the turn-on switching transients, in which the channel can also be equivalent to a nonlinear resistance, voltage-controlled current source, or an open circuit. Therefore, some repeated equations are omitted in the derivation of the stage equations for the turn-off switching transients.
Stage 6 [t6-t7] Turn-Off Delay Time: Before the gate source voltage v gs reduces to the Miller Voltage V miller , which is governed by (23), the SiC MOSFET power device operates in the ohmic region. It is assumed that the drain current i d remains unchanged (i d = I DD ) at this stage. As shown in Figure 5a the gate-source capacitance and the gate-drain capacitance are being discharged through R g and L s . The circuit equations are shown from (24) to (26): where where RSS = Rg_off + Rg_int.
As with the stage 1, there are three independent state variables: the drain current ig, the gatesource voltage vgs and the drain-source voltage vds, and the state equations derived from the above equations are shown in Appendix A Equation (A6). Since the device is still activated, the loss during this period is conduction loss Econd, which can be calculated as: Stage 7 [t7-t8] Voltage Rising Time I: During this stage, the power device still works in the ohmic region until the drain-source voltage vds reaches vgs − Vth. Therefore, the drain current id stays constant at IDD and the gate-source voltage vgs (almost) remains at the Miller voltage. The equivalent circuit and equations during this period are the same as the previous one, while the loss during this period is regarded as the switching loss Esw and can be calculated as:

Stage 8 [t8-t9] Voltage Rising Time II:
When the drain-source voltage vds reaches vgs − Vth, the device begins to operate in saturation region. Therefore, the channel is equivalent to a voltage-controlled current source, as shown in Figure 5b. The drain-source voltage vds continues to increase until the forward voltage vf of the SBD decreases to the forward voltage −Vf. The voltage slew rate will be faster than in the previous stage, since the value of junction capacitance significantly decreases with the increase in drain-source voltage vds. A part of IDD will be flowing through the freewheeling diode to discharge the Cf, which will be causing the drain current id drop. During this period, the channel current ich is also governed by (6). Hence the drain current id expression is changed to (10) and the rest of the circuit equations are the same as the stage 4 and the state equations are shown in Appendix A Equation (A8). During this period, the switching loss Esw is given by (30) and (31). As with the stage 1, there are three independent state variables: the drain current i g , the gate-source voltage v gs and the drain-source voltage v ds , and the state equations derived from the above equations are shown in Appendix A Equation (A6). Since the device is still activated, the loss during this period is conduction loss E cond , which can be calculated as: Stage 7 [t7-t8] Voltage Rising Time I: During this stage, the power device still works in the ohmic region until the drain-source voltage v ds reaches v gs − V th . Therefore, the drain current i d stays constant at I DD and the gate-source voltage v gs (almost) remains at the Miller voltage. The equivalent circuit and equations during this period are the same as the previous one, while the loss during this period is regarded as the switching loss E sw and can be calculated as: Stage 10 [t10-t11] Off-State Operation: After the gate-source voltage v gs decreases to V th , the device works in the cut-off region. For a similar reason, a lumped resistance is added in the circuit (shown in Figure 5d). This stage ends, when the gate-source voltage v gs decreases to the negative drive voltage V SS . The state equations are shown in Appendix A Equation (A9) Since the channel is inactive, there is no power loss during this period. As discussed above, the power loss during the switching transient can be categorized and summarized as (34) to (37).

Experimental Setup
Based on the proposed analytical model, except for the operating condition V DD , I DD , V GG , and V SS , the parameters needed in the calculation are the junction capacitances C gs , C gd , C gs and C f , the stray inductances of the PCB traces L bus , L line , the parasitic inductances of the terminal L g , L d , L s , L a and L c , and the static characteristic of power devices: the trans-conductance g f , the internal resistance R g_int and R f , the threshold voltage V th , the forward voltage V f , and on-state resistance R on . Apart from the junction capacitances and the parasitic, stray inductances, all the other parameters are temperature dependent. Therefore, it is necessary to build a test platform for the measurement. The approaches to obtain these parameters can be divided into three categories.

Static Characteristic Test Platform
According to the standards of IEC 60747-8 [27] and datasheet of the device vendor [28,29], the static characteristic test platform based on Power Device Analyzer Curve Tracer (PDACT) Agilent B1505A with the heating plate was established to measure the static characteristic of SiC MOSFET C2M0025120D (Cree, 1200 V, 90 A) and SiC SBD C4D20120A (Cree, 1200 V, 90 A), as shown in Figure 6. Considering the materials and components that make up the package are not compatible with high temperature (usually lower than 175 • C) [30], the testing temperature ranges from 25 to 150 • C. It should be noted that the case temperature T c obtained by infrared thermal camera is used to approximate the junction temperature T j , since the latter is difficult to measure by conventional methods. The specific settings of each module are shown in Table 1.

ANSYS Q3D Extractor
A common approach to measure the value of the stray inductance is computational electromagnetics [31], which relies on finite-element analysis (FEA) simulation (e.g., ANSYS Q3D Extractor) to solve Maxwell's equations through the PCB layout and component material information.
The stray resistance and stray inductance, including both self-inductance and mutual-inductance, can be accurately extracted through this approach. However, in order to simplify the calculation, the mutual inductances are neglected in this analytical model.

Vector Network Analyzer
The parasitic inductance is mainly determined by the devices package. However, the above approach suffers from being time-consuming and having poor convergence, since the physical structure of a package is complex. There is a more practical approach which is based on Impedance Analyzer or Vector Network Analyzer (VNA) [32]. By calibrating the test system using a mathematical technique called vector error correction, VNA provides high measurement accuracy [33]. The power device is performed over a frequency range of 100 kHz to 200 MHz by Keysight VNA (E5061B). Since the MOSFET under zero applied voltage is equivalent to a second-order RLC circuit, as shown in Figure 7, it has a self-resonant frequency (SRF). The parasitic inductances and internal resistances can be calculated through its SRF [34]. The testing temperature also ranges from 25 to 150 • C.

Experimental Results
The static characteristic parameters obtained from the above methods are shown in Figure 8e (the black scatter plot). All of these measured scatters require nonlinear fitting before they can be used for calculation. The extraction results of the stray inductances of PCB traces and the parasitic inductances of power device terminals are shown in Table 2, respectively. Due to the maximum difference of less than 5%, the parasitic inductances are treated as a constant (the average) in the later calculation. The internal resistance R g_int and R f obtained through VNA measuring are shown in Figure 8f while the others, such as R s_int and R d_int , are ignored in the proposed model since their values are very small.

Fitting to the Key Parameters
For the sake of a trade-off between the precision and simplicity, the polynomial fitting is adopted to fit the static characteristic curve of the SiC MOSFET C2M0025120D. An appropriate polynomial order is chosen to ensure the R-squared (coefficient of determination, a goodness of fit) higher than 0.995. The trans-conductance gf and on-state resistance R on can be regarded as a two-variable function Appl. Sci. 2020, 10, 7192 13 of 22 of V gs and T j and function of id and T j , respectively. The fitting equations are given in (38) and (39), the fitted curves are shown in the Figure 8a,b. g f (v gs , T j ) = p 00 + p 10 v gs + p 01 T j + p 20 v 2 gs + p 11 v gs T j + p 02 T 2 where p 1 = 6.104 × 10 −8 , p 2 = 7.835 × 10 −6 , p 3 = −4.974 × 10 −3 , p 4 = 1.524.
Nevertheless, polynomial does not perform well in the junction capacitance versus the applied voltage curve fitting. According to [35,36], the input capacitance C iss was treated as two discrete values and (44) is adopted to characterize the nonlinearity of the output capacitance C oss and the reverse transfer capacitance C rss (see Table 3). The transform relationship between C iss , C rss , C oss and C gs , C gd , C ds is shown in (45).
where v is the applied voltage, C 0 is the capacitance value under v = 0 V, a and b are two adjustment parameters extracted from the capacitance versus voltage curve.

Loss Assessment
Based on the discussion above, the flowchart in Figure 9 presents the calculation routine for applying the model. Compared with traditional method, the iterative method is adopted to solve the state equations, from which the numerical solution can be derived without simplification [37]. Therefore, the calculation accuracy is improved. As mentioned in the previous section, there are two switching loss calculation methods in this model. In turn-on transients, the calculation I will be less than calculation II, since the discharging current of C ds and C gd , which opposes the trend of the drain current is included in i d . However, the turn-off loss of calculation I will be greater than calculation I due to the charging current of C ds and C gd . As a result, the two types of calculation would not vary the E total but would instead vary the distribution of power losses between E sw_on and E sw_off . The experimental prototype of a 400-V, 15-A double-pulse-test setup is shown in Figure 10, in which the chip inductors are added to simulate the varied stray inductances. As stated in [38], the measurement system bandwidth should be higher than ten times the highest equivalent frequency of the measured signal, which can be approximated by where t r is the rise time, t f is the fall time.
The typical rise/fall time of C2M0025120D is 32/28 ns. According to (46), the equivalent frequency is 8.9 MHz. The measurement system specified in Table 4 can meet the bandwidth requirement. It must be pointed out that for the sake of emulating the switching waveforms taken in the experiment, the induced voltage drops across the parasitic inductances of the package terminal; L s1 and L d1 have to be included in the analytical waveforms for v ds , as they are intrinsic and inside the package.  Figure 11, the switching waveforms of the proposed analytical model match the experiment well. Voltage and current overshoot are also important factors in the application of the power device, which should be considered together with the power losses. The quantitative comparison of loss and voltage and current overshoot is listed in Table 5. The maximum error is 7.13%, which proves the good accuracy of the model. The variation patterns of power losses with each parameter element can be worked out by the calculation, as shown in Figure 8, to present a further investigation into the loss mechanism and they will be demonstrated experimentally. The ±10% error bars of the experimental results are added to illustrate the accuracy. It can be seen that the calculation results are in good accordance with the experiment.  Junction Temperature: In Figure 8, it can be seen that most of the key parameters are temperature-dependent. As a result, the temperature will affect the switching performances of SiC MOSFET obviously. The comparison of power losses between experiment and calculation with varied junction temperature T j are illustrated in Figure 12a. It is easy to see that the increase in T j reduces the turn-on loss and increases the turn-off loss contrarily. The conduction loss increases slightly, since the on-state resistance R on is positively correlated with T j . As a result, the total loss does not exhibit great variation at different T j . In the turn-off transients, with the increased trans-conductance g f affected by the rising junction temperature T j , the Miller voltage will decrease consequently, which leads to a reduction in the current slew rate. Hence, the voltage overshoot decreases with the increase in T j , as shown in Figure 12b. Gate Driver Resistance: Figure 13a presents the power losses with varied R g . It shows that the switching loss (both turn-on and turn-off) exhibit distinctive increases with the increase in R g , which is due to the slower switching speed resulting from larger R g . For the same reason, the voltage and current overshoot will all decrease (see Figure 13b). It is necessary for designers to make a trade-off between switching speed and switching loss. The double-gate-resistances is a useful solution; a proper turn-on resistance to ensure the switching speed and a low turn-off resistance to discharge the C gs fast. Loop Parasitic Inductance: L p denotes all the stray inductances along the power loop and the parasitic inductances of the terminal of the power devices. Figure 14a illustrates the power losses with varied L p . It can be seen that the turn-on loss decreases obviously with the increase in L p , because the greater L p will induce a larger voltage drop in stage 2, so that the voltage falling time will be shorter. However, as shown in Figure 14b, the larger L p will generate a larger voltage overshoot and current voltage.  Figure 14a illustrates the power losses with varied Lp. It can be seen that the turn-on loss decreases obviously with the increase in Lp, because the greater Lp will induce a larger voltage drop in stage 2, so that the voltage falling time will be shorter. However, as shown in Figure 14b, the larger Lp will generate a larger voltage overshoot and current voltage. Common Source Stray Inductance: Ls2 differ from other stray inductances of PCB traces since it coexists in both the power stage and the gate drive stage. When the MOSFET works in the saturation region (the channel equivalent to a voltage-controlled current source), the fast-changing drain current will induce a voltage drop across Ls2, which provides a negative feedback to the gate drive stage. Hence, the effect of Ls2 on switching loss is similar to Rg, as shown in Figure 15. In common engineering practice, the gate driver is normally placed next to the power device as close as possible to reduce this inductance.

As shown in
External Gate Stray Inductance: The comparison of power losses, voltage overshoot and current overshoot between experiment and calculation with varied external gate stray inductance Lg2 is illustrated in Figure 16a,b, respectively. There is no recognizable difference with varied Lg2. In fact, according to the circuit design guidelines, Lg2 should be kept small to avoid the oscillations between Lg and Cgs. Common Source Stray Inductance: L s2 differ from other stray inductances of PCB traces since it co-exists in both the power stage and the gate drive stage. When the MOSFET works in the saturation region (the channel equivalent to a voltage-controlled current source), the fast-changing drain current will induce a voltage drop across L s2 , which provides a negative feedback to the gate drive stage. Hence, the effect of L s2 on switching loss is similar to R g , as shown in Figure 15. In common engineering practice, the gate driver is normally placed next to the power device as close as possible to reduce this inductance. External Gate Stray Inductance: The comparison of power losses, voltage overshoot and current overshoot between experiment and calculation with varied external gate stray inductance L g2 is illustrated in Figure 16a,b, respectively. There is no recognizable difference with varied L g2 . In fact, according to the circuit design guidelines, L g2 should be kept small to avoid the oscillations between L g and C gs. According to the aforementioned experimental and analytical investigation, the effects of the varied elements including the T j , R g , L p , L s2 and L g2 on the power losses and voltage and current overshoot in the switching transients are summarized in Table 6. Table 6. Quantitative comparison of loss, voltage and current overshoot.
↑/↓, denotes increase/decrease with the increase in the varied element; → denotes no obvious change the with the increase in the varied element.

Conclusions
This paper has presented an improved analytical loss model which takes the parasitic elements of the power devices and the stray inductances of the PCB traces into consideration. A comprehensive power device test platform is built to extract the key temperature-dependent parameters in the calculation. The measurement results show that the trans-conductance g f , on-state resistance R on , threshold voltage v th and internal resistance R g-int are sensitive to junction temperature. The switching waveforms of the proposed analytical model successfully match the experiment results of a 400-V, 15-A double-pulse-test bench. In addition, the variation patterns of power losses both in calculation and experiments can be summarized as follows.
(1) The increase in the gate driver resistance R g or the common stray inductance L s2 will increase the total loss while decreasing the voltage overshoot and the current overshoot at the same time.
In common practical applications, the gate driver resistance R g is the only component that can be changed. Therefore, it should be chosen to compromise the conflicts between power loss and device stresses.
(2) The increase in the loop parasitic inductances L p will decrease the total loss while increasing the voltage overshot and the current overshoot in the meantime.
(3) The total loss does not change obviously with the varied junction temperature T j and the varied external gate stray inductance L g2 .
The summarized conclusions above are expected to assist PCB layout design in practical applications of the SiC MOSFET, which is aimed at achieving a low power loss with proper device stresses. Future studies will be dedicated to varied circuits based on this study.
Author Contributions: Y.Z. and Y.Y. conceived and designed the study; Y.Z. gave the theoretical and data analysis; Y.Y. and P.L. revised the whole manuscript; Y.Z. wrote the paper. All authors have read and agreed to the published version of the manuscript.

Funding:
This research was full supported by the National Key R&D Program of China (Grant No. 2018YFB0106300).

Conflicts of Interest:
The authors declare no conflict of interest.

Appendix A
where, C ∆ = C gd C gs + C ds (C gs + C ds )