Small-Signal Analysis and Control of Soft-Switching Naturally Clamped Snubberless Current-Fed Half-Bridge DC / DC Converter

: This paper presents small-signal analysis of a soft-switching naturally clamped snubberless isolated current-fed half-bridge (CFHB) DC-DC converter using state-space averaging. A two-loop average current controller was designed and implemented on a digital signal processor. The complete design procedure is presented here. Simulation results using software PSIM 11.1 are shown to validate the stability of the control system and the controller design. Experimental results for the step changes in load current vividly demonstrated satisfactory transient performance of the converter and validated the developed small-signal model and the control design. This paper studied small-signal modeling and derived transfer functions of an isolated naturally clamped snubberless current-fed half-bridge DC-DC converter. A two-loop average current controller was designed o ﬀ ering ﬁxed-frequency duty cycle modulation of the semiconductor devices using two controllers. Initial veriﬁcation of the small-signal model and the controller was done using PSIM 11 and investigation of the dynamic performance of the converter. Experimental results on a laboratory hardware proof-of-concept prototype demonstrated the satisfactory and smooth transient performance of the converter and the e ﬀ ectiveness of the designed closed-loop controller. The simplicity of implementation and practicality of the proposed control are the beneﬁts of the overall system. The proposed analysis is e ﬀ ective for non-isolated as well as interleaved half-bridge and interleaved-boost topologies. It is suitable for fuel cell applications.


Introduction
Electric transportation, energy storage, renewable energy systems, hybrid electric vehicles (HEV), and fuel cell vehicles require bidirectional power electronics for power processing [1][2][3][4]. A DC-DC front-end converter is the major part of a fuel cell inverter, which boosts the low-voltage fuel cell stack's voltage to the peak of utility line alternating current (AC) voltage [5]. Among various categories of high-frequency (HF) soft-switching isolated DC-DC converters, a current-fed converter is popular in fuel cell applications. Fuel cells produce low-voltage direct current (DC), which has a wide variation with load current and requires a high voltage conversion ratio [6][7][8][9][10]. Current-fed topologies offer high voltage gain with a stiff DC input current [11]. The historical problem with current-fed converters has been the necessity of a passive snubber [12,13] or an active-clamping circuit [14][15][16] to clamp voltage overshoot across the semiconductor devices at their turn-off. Passive snubbers lead to poor efficiency because the energy stored by the clamping capacitor is later dissipated into the resistor. However, better efficiency is obtained, along with zero voltage switching (ZVS) of the semiconductor devices, with an active-clamping circuit [14][15][16], at the cost of additional footprints of floating active device(s) and a large HF clamp capacitor for accurate and effective voltage clamping. Additionally, the boost factor of the converter is reduced as well as the high peak, and circulating currents can be observed at light load. In [17], a new modulation technique of high-voltage side devices was proposed to solve the voltage spike problem of primary devices, eliminating the requirement for an external snubber. A current-fed half-bridge DC-DC converter was proposed as shown in Figure 1 with a new modulation, eliminating the requirement for an external snubber. A current-fed half-bridge DC-DC converter was proposed as shown in Figure 1 with a new modulation, which was studied in [17] to achieve zero current switching (ZCS) commutation of semiconductor devices along with natural device voltage clamping. Steady-state analysis, power circuit design, and steady-state experimental performance results of the converter have previously been presented in [17]. However, its small-signal modeling, controller design, and dynamic performance results have not yet reported. The authors reported the small-signal modeling and derived the transfer functions in [18]. Controller design and simulation results were presented to show initial results and investigation on the transient performance of the converter. This paper presents systematic small-signal analysis and experimental results to demonstrate the closed-loop dynamic performance of the converter.

Small-Signal Analysis
The following procedure was followed to derive the small-signal model and converter transfer functions: (1) Make assumptions (2) Define state variables (3) Write state equations for each interval of operation (4) Average the state equations over a switching cycle (5) Introduce perturbation in state variables (6) Equate AC and DC quantities and proceed with AC equations (7) Take Laplace transform (8) Prepare matrix small-signal model (9) Calculate desired transfer functions The following assumptions were made for the small-signal modeling of the converter: (1) all the power semiconductor devices are lossless and ideal; (2) inductors L1 and L2 are large enough to maintain constant current through them; (3) inductor Ls includes the leakage inductance of the HF transformer; steady-state operating waveforms are shown in Figure 2; (4) snubber/device capacitance charging and discharging intervals are short and neglected.
The primary side devices S1 and S2 are operated with identical gating signals phase-shifted with each other by 180°. The duty cycle of the primary switches is always kept above 50%. The operation during different intervals in a one-half switching cycle is explained with equivalent circuits shown in Figure 3. Steady-state analysis, power circuit design, and steady-state experimental performance results of the converter have previously been presented in [17]. However, its small-signal modeling, controller design, and dynamic performance results have not yet reported. The authors reported the small-signal modeling and derived the transfer functions in [18]. Controller design and simulation results were presented to show initial results and investigation on the transient performance of the converter. This paper presents systematic small-signal analysis and experimental results to demonstrate the closed-loop dynamic performance of the converter.

Small-Signal Analysis
The following procedure was followed to derive the small-signal model and converter transfer functions: (1) Make assumptions (2) Define state variables (3) Write state equations for each interval of operation (4) Average the state equations over a switching cycle (5) Introduce perturbation in state variables (6) Equate AC and DC quantities and proceed with AC equations (7) Take Laplace transform (8) Prepare matrix small-signal model (9) Calculate desired transfer functions The following assumptions were made for the small-signal modeling of the converter: (1) all the power semiconductor devices are lossless and ideal; (2) inductors L 1 and L 2 are large enough to maintain constant current through them; (3) inductor L s includes the leakage inductance of the HF transformer; steady-state operating waveforms are shown in Figure 2; (4) snubber/device capacitance charging and discharging intervals are short and neglected.
The primary side devices S 1 and S 2 are operated with identical gating signals phase-shifted with each other by 180 • . The duty cycle of the primary switches is always kept above 50%. The operation during different intervals in a one-half switching cycle is explained with equivalent circuits shown in Figure 3.     Reproduced with permission from [17], IEEE, 2020. (a) S2 in blocking mode; (b) S2 is turned-on; (c) ZVS turn-on of S4 and S5; (d) ZCS turn-off of S1 and body diode conducts; (e) D3 and D6 start conduction for rectification; (f) S1 goes in blocking mode.
Interval 1 (Figure 3a; t1 < t < t2) During this interval, primary side switch S1 and anti-parallel body diodes D4 and D5 of secondary switches are conducting to rectify the HF AC waveform across the transformer secondary. Power is transferred to the load through an HF transformer. Transformer primary current is negative and constant. Switch S1 is carrying the entire input current. State equations of this interval are: Interval 2 (Figure 3b; t2 < t < t3) Primary side switch S2 is turned on and starts conducting. The current from S1 is transferred to the switch S2 through the transformer primary winding with a slope limited by transformer leakage inductance Ls. State equations of this interval are: Interval 1 (Figure 3a; t 1 < t < t 2 ) During this interval, primary side switch S 1 and anti-parallel body diodes D 4 and D 5 of secondary switches are conducting to rectify the HF AC waveform across the transformer secondary. Power is transferred to the load through an HF transformer. Transformer primary current is negative and constant. Switch S 1 is carrying the entire input current. State equations of this interval are: Interval 2 ( Figure 3b; t 2 < t < t 3 ) Primary side switch S 2 is turned on and starts conducting. The current from S 1 is transferred to the switch S 2 through the transformer primary winding with a slope limited by transformer leakage inductance L s . State equations of this interval are: Appl. Sci. 2020, 10, 6130 Interval 3 (Figure 3c; t 3 < t < t 4 ) Secondary side devices S 4 and S 5 are turned on with ZVS. The current waveforms follow the same pattern and slope. State equations of interval 2 still hold good.
Interval 4 (Figure 3d; t 4 < t < t 5 ) Primary side device S 1 turns off with ZCS, and its anti-parallel body diode starts conducting. State equations of interval 2 still hold good.
Interval 5 (Figure 3e; t 5 < t < t 6 ) Secondary side devices S 4 and S 5 are forced commutated, and anti-parallel body diodes D 3 and D 6 of secondary switches take over the current.
Equations (1), (3), and (5) hold good for inductor currents i L1 , i L2 , and output capacitor c o . Identically, state equations for the other half-cycle can also be derived. State equations are averaged over an HF cycle. The average value for the rate of change of i Ls over one complete HF cycle is zero, and the averaged state equation is: So, the state variable i Ls is omitted for the following analysis. Define: The averaged state equations of defined state variables over an HF cycle are given: where i average is the average current feeding the output capacitor and load from secondary side H-bridge switches and is given by: Substituting Equation (12) into Equation (11) gives: The duty ratio of the main switches, including conduction of the anti-parallel diodes, is defined as: Perturbation is introduced around the steady-state values of the state variables and input voltage such that The state equations are modified to the following: Neglecting the second order terms and steady-state or DC terms results in the following equations: Taking Laplace transform, and then solving results in: Writing in matrix form: where Writing in matrix form: where The control-to-output transfer function is obtained from Equation (28) by keepingv in = 0, resulting in the following equation:v

Two-Loop Closed-Loop Control Design
The two-loop control system is shown in Figure 4 with two proportional integral (PI) controllers and two identical modulators phase-shifted by 180 • . Active current ripple is the major issue in the design of a fuel cell converter. The key to ripple reduction is to control the average inductor current i L to be DC, which requires separating the bandwidths of voltage and current loops far apart using a slow voltage loop and a fast current loop [19]. Bandwidth (BW) of the inner current loop is selected to be higher than the outer voltage loop, which simplifies the design [20]. Therefore, it is possible to adjust the inductor current more quickly than the load voltage. The outer voltage loop regulates the load voltage by deriving reference for the input inductor current, i L1,ref , and i L2,ref reference. Inductor currents i L1 and i L2 are tuned to this reference value by adjusting the duty ratio of the switches.

Two-Loop Closed-Loop Control Design
The two-loop control system is shown in Figure 4 with two proportional integral (PI) controllers and two identical modulators phase-shifted by 180°. Active current ripple is the major issue in the design of a fuel cell converter. The key to ripple reduction is to control the average inductor current iL to be DC, which requires separating the bandwidths of voltage and current loops far apart using a slow voltage loop and a fast current loop [19]. Bandwidth (BW) of the inner current loop is selected to be higher than the outer voltage loop, which simplifies the design [20,21]. Therefore, it is possible to adjust the inductor current more quickly than the load voltage. The outer voltage loop regulates the load voltage by deriving reference for the input inductor current, iL1,ref, and iL2,ref reference. Inductor currents iL1 and iL2 are tuned to this reference value by adjusting the duty ratio of the switches. A bode plot of the control-to-output voltage transfer function given by Equation (30) is given in Figure 5. The phase margin (PM) is negative. This makes the system sensitive to small disturbances in operating points of input or source voltage and load current. Figure 6 shows that this transfer faction has right half plane zero, which adds a negative phase to the system. Instead of the phase increasing from 0 to 90 degrees, its phase increases from 0 to −90 degrees. This causes a delay in system response, which can lead to instability if not properly compensated.  A bode plot of the control-to-output voltage transfer function given by Equation (30) is given in Figure 5. The phase margin (PM) is negative. This makes the system sensitive to small disturbances in operating points of input or source voltage and load current. Figure 6 shows that this transfer faction has right half plane zero, which adds a negative phase to the system. Instead of the phase increasing from 0 to 90 degrees, its phase increases from 0 to −90 degrees. This causes a delay in system response, which can lead to instability if not properly compensated.

Two-Loop Closed-Loop Control Design
The two-loop control system is shown in Figure 4 with two proportional integral (PI) controllers and two identical modulators phase-shifted by 180°. Active current ripple is the major issue in the design of a fuel cell converter. The key to ripple reduction is to control the average inductor current iL to be DC, which requires separating the bandwidths of voltage and current loops far apart using a slow voltage loop and a fast current loop [19]. Bandwidth (BW) of the inner current loop is selected to be higher than the outer voltage loop, which simplifies the design [20,21]. Therefore, it is possible to adjust the inductor current more quickly than the load voltage. The outer voltage loop regulates the load voltage by deriving reference for the input inductor current, iL1,ref, and iL2,ref reference. Inductor currents iL1 and iL2 are tuned to this reference value by adjusting the duty ratio of the switches. A bode plot of the control-to-output voltage transfer function given by Equation (30) is given in Figure 5. The phase margin (PM) is negative. This makes the system sensitive to small disturbances in operating points of input or source voltage and load current. Figure 6 shows that this transfer faction has right half plane zero, which adds a negative phase to the system. Instead of the phase increasing from 0 to 90 degrees, its phase increases from 0 to −90 degrees. This causes a delay in system response, which can lead to instability if not properly compensated.

Current Control Loop Design
The schematic diagram of the inner current control loop is shown in Figure 7. The input inductor current is fed back to the error amplifier with the gain of H1(s). The error is processed by a PI controller, and the output of the controller is compared with the modulator to generate the gating signals of the devices. The inductors' currents iL1 and iL2 are then regulated by adjusting the duty ratio of the switches.
Duty ratio to the inductor current transfer function is derived from Equation (27) and given by: For the given specifications as shown in Table 1, the duty ratio to inductor current transfer function is given by:

Current Control Loop Design
The schematic diagram of the inner current control loop is shown in Figure 7. The input inductor current is fed back to the error amplifier with the gain of H 1 (s). The error is processed by a PI controller, and the output of the controller is compared with the modulator to generate the gating signals of the devices. The inductors' currents i L1 and i L2 are then regulated by adjusting the duty ratio of the switches.

Current Control Loop Design
The schematic diagram of the inner current control loop is shown in Figure 7. The input inductor current is fed back to the error amplifier with the gain of H1(s). The error is processed by a PI controller, and the output of the controller is compared with the modulator to generate the gating signals of the devices. The inductors' currents iL1 and iL2 are then regulated by adjusting the duty ratio of the switches.
Duty ratio to the inductor current transfer function is derived from Equation (27) and given by: For the given specifications as shown in Table 1, the duty ratio to inductor current transfer function is given by: Duty ratio to the inductor current transfer function is derived from Equation (27) and given by: For the given specifications as shown in Table 1, the duty ratio to inductor current transfer function is given by: The gain margin and PM of the current control loop without controller is plotted in Figure 8, which shows PM = 90 • at 177 krad/s. The PI controller is designed at PM of 60 • in Figure 9 to increase the low-frequency gain and to reduce the steady-state error [21].  The gain margin and PM of the current control loop without controller is plotted in Figure 8, which shows PM = 90 at 177 krad/s. The PI controller is designed at PM of 60 in Figure 9 to increase the low-frequency gain and to reduce the steady-state error [22].   The gain margin and PM of the current control loop without controller is plotted in Figure 8, which shows PM = 90 at 177 krad/s. The PI controller is designed at PM of 60 in Figure 9 to increase the low-frequency gain and to reduce the steady-state error [22].  The transfer function of a PI controller is given by: The open-loop transfer function of the current loop is given by: LEM sensor LA25-NP is used to sense the inductor current and to provide the isolation between power circuit and controller. Here, H 1 (s) is the current feedback gain and T m (s) is the overall gain of the modulator.
Here, the current feedback gain is selected as H 1 (s) = 1.
Overall gain of the modulator is chosen to be: To realize PM = 60 • , the following angle condition for the open-loop transfer function is applied: To realize the desired crossover frequency, the following gain condition of unity is applied for the open-loop transfer function, i.e., T OL1 ( jw c ) = 1 : PI controller parameters are designed to obtain PM of 60 • [21,22] at the gain crossover frequency of 31.5k rad/s (5000 Hz) (Figure 9). Low-frequency gain is improved. It results in the gain K p and K i as 0.16 and 7269.58, respectively.

Voltage Control Loop Design
The outer voltage control loop regulates the output voltage at the reference value by setting reference for the current through the input inductors as shown in Figure 10. The inner current control loop has faster dynamics compared to the outer voltage loop. Hence, the current loop dynamics are neglected during the design of the voltage controller [23]. Its transfer function is not included, and the perturbation in the duty cycle can be neglected. Therefore, the inductor current to output voltage transfer function T p2 (s) is obtained as: LEM sensor LV20-P is used to sense output voltage and also to provide the necessary isolation. Here, the voltage feedback gain is chosen as: The gain crossover frequency for the voltage controller is selected to be 10 times slower than that of the inner current loop. Application of angle and gain conditions similar to the current control loop for the desired PM of 60° a at gain crossover frequency of 3150 rad/s results in the gain Kp and Ki as 16.83 and 9767.8, respectively. Taking into account the dynamics of the current control loop, the overall transfer function of the system can be given as Equation (44).

T s T s T s H s T s T s T s H s T s T s T s H s H s
The Bode plot of the compensated voltage control loop is shown in Figure 12. Low-frequency gain is improved, indicating reduced steady-state error. The desired positive PM of 60° indicates a stable system rejecting disturbances for wide operating input voltage and load power variations.
The gain crossover frequency for the voltage controller is selected to be 10 times slower than that of the inner current loop. Application of angle and gain conditions similar to the current control loop for the desired PM of 60° a at gain crossover frequency of 3150 rad/s results in the gain Kp and Ki as 16.83 and 9767.8, respectively. Taking into account the dynamics of the current control loop, the overall transfer function of the system can be given as Equation (44).

T s T s T s H s T s T s T s H s T s T s T s H s H s
The Bode plot of the compensated voltage control loop is shown in Figure 12. Low-frequency gain is improved, indicating reduced steady-state error. The desired positive PM of 60° indicates a stable system rejecting disturbances for wide operating input voltage and load power variations.
The gain crossover frequency for the voltage controller is selected to be 10 times slower than that of the inner current loop. Application of angle and gain conditions similar to the current control loop for the desired PM of 60 • a at gain crossover frequency of 3150 rad/s results in the gain K p and K i as 16.83 and 9767.8, respectively. Taking into account the dynamics of the current control loop, the overall transfer function of the system can be given as Equation (44).
The Bode plot of the compensated voltage control loop is shown in Figure 12. Low-frequency gain is improved, indicating reduced steady-state error. The desired positive PM of 60 • indicates a stable system rejecting disturbances for wide operating input voltage and load power variations.

Simulation and Experimental Results
The simulation model of the circuit topology and two-loop control was developed on software package PSIM 11 and was run to capture waveforms and observe transient performance of the converter under load-current variations. Simulation results are illustrated in Figures 13 and 14.

Simulation and Experimental Results
The simulation model of the circuit topology and two-loop control was developed on software package PSIM 11 and was run to capture waveforms and observe transient performance of the converter under load-current variations. Simulation results are illustrated in Figures 13 and 14.

Simulation and Experimental Results
The simulation model of the circuit topology and two-loop control was developed on software package PSIM 11 and was run to capture waveforms and observe transient performance of the converter under load-current variations. Simulation results are illustrated in Figures 13 and 14.   converter. Figure 14d (zoomed waveform in transient period) shows voltage across the primary side devices is clamped at the reflected output voltage, while voltage on the secondary side devices is always clamped at output voltage. Figure 14e,f shows steady-state (zoomed) waveforms at rated load and half load, respectively. It should be noted that primary side devices maintain ZCS, and secondary side devices maintain ZVS under both conditions.
(e) (f) Figure 14. Simulation waveforms for Vin = 12 V with step change in load from rated load to half load with identical nomenclature. (a) Vo is output voltage, Io is output current, (b) IL1 and IL2 are input inductor currents, and (c) Vs1 and Vs3 are voltages across the switches and , respectively, (d) zoomed waveform of Vs1 and Vs3, (e). ILs is the transformer primary current and IS1 and IS2 are the current through the switches and , respectively at full-load steady-state and (f) ILs is the transformer primary current and IS1 and IS2 are the current through the switches and , respectively at half-load steady-state.

Figure 14.
Simulation waveforms for V in = 12 V with step change in load from rated load to half load with identical nomenclature. (a) V o is output voltage, I o is output current, (b) I L1 and I L2 are input inductor currents, and (c) V s1 and V s3 are voltages across the switches S 1 and S 3 , respectively, (d) zoomed waveform of V s1 and V s3 , (e). I Ls is the transformer primary current and I S1 and I S2 are the current through the switches S 1 and S 3 , respectively at full-load steady-state and (f) I Ls is the transformer primary current and I S1 and I S2 are the current through the switches S 1 and S 3 , respectively at half-load steady-state.
The load is changed from 50% load to rated load ( Figure 13) and from full load to 50% load ( Figure 14). It should be observed that the overshoot or undershoot in output voltage for both step changes is 2V, which demonstrates the excellent stability of control. Load current and the two input inductor currents smoothly change to the next steady-state value. The settling time of the inductors' current and load voltage is nearly 25 ms. The voltage across the primary switches (VS1) is clamped at the reflected output voltage, and the voltage across the secondary devices (VS3) is clamped at the output voltage V o without any overshoot during the load transients, ensuring safe operation of the converter. Figure 14d (zoomed waveform in transient period) shows voltage across the primary side devices is clamped at the reflected output voltage, while voltage on the secondary side devices is always clamped at output voltage. Figure 14e,f shows steady-state (zoomed) waveforms at rated load and half load, respectively. It should be noted that primary side devices maintain ZCS, and secondary side devices maintain ZVS under both conditions. Figure 15 shows the experimental prototype of the converter. It is operated by the designed controller, which has been tested in the laboratory for the step changes in load for a fixed 12 V input voltage. Table 2 shows the details of the components used in the hardware prototype.
Appl. Sci. 2020, 10, x FOR PEER REVIEW 14 of 19 Figure 15 shows the experimental prototype of the converter. It is operated by the designed controller, which has been tested in the laboratory for the step changes in load for a fixed 12 V input voltage. Table 2 shows the details of the components used in the hardware prototype.  Output Capacitor 220 μF, 450 V electrolytic capacitor 0.68 μF, 450 V high frequency film capacitor Gating signals for the semiconductor devices are generated by Texas Instruments (TI) digital signal processor (DSP) TMS320F28335. Experimental waveforms for the step change in load are shown in Figures 16 and 17. Figure 16 demonstrates the experimental waveforms of inductor current iL, voltage VAB, and output voltage Vo with respect to time for the step change in load from rated load to 50% load. The similar waveforms for step change in load from 50% to rated load are manifested in Figure 17. Overshoot and undershoot in the output voltage are negligible during load transients. Further, output voltage is maintained at the constant value. The variations in inductor current and (transformer primary voltage, that is, the sum of voltage across the two primary switches S1 and S2) are within safe limiting values. Therefore, the switches do not experience any voltage spike during transition, which ensures safe and normal operation of the converter. Inductor current is adjusted to their new steady-state values smoothly. The settling time is nearly 20 ms. This demonstrates stable performance over a wide load variation. It should be noticed that the experimental settling time is higher than the simulation value because the hardware experiences power loss, voltage drop, stray inductance/capacitance, system delay, and parasitic elements, which cause aberration from the ideal model. Better dynamic performance may be achieved by proper tuning of the controller parameters.  Gating signals for the semiconductor devices are generated by Texas Instruments (TI) digital signal processor (DSP) TMS320F28335. Experimental waveforms for the step change in load are shown in Figures 16 and 17. Figure 16 demonstrates the experimental waveforms of inductor current i L , voltage V AB , and output voltage V o with respect to time for the step change in load from rated load to 50% load. The similar waveforms for step change in load from 50% to rated load are manifested in Figure 17. Overshoot and undershoot in the output voltage are negligible during load transients. Further, output voltage V o is maintained at the constant value. The variations in inductor current I L and V AB (transformer primary voltage, that is, the sum of voltage across the two primary switches S 1 and S 2 ) are within safe limiting values. Therefore, the switches do not experience any voltage spike during transition, which ensures safe and normal operation of the converter. Inductor current I L is adjusted to their new steady-state values smoothly. The settling time is nearly 20 ms. This demonstrates stable performance over a wide load variation. It should be noticed that the experimental settling time is higher than the simulation value because the hardware experiences power loss, voltage drop, stray inductance/capacitance, system delay, and parasitic elements, which cause aberration from the ideal model. Better dynamic performance may be achieved by proper tuning of the controller parameters.   Figures 18 and 19 show the steady-state zoomed waveforms under half load and full load, respectively. Figures 18a and 19a show the gate-to-source and drain-to-source Vds voltage waveforms across primary side MOSFET and transformer primary current is waveform at half load and full load, respectively. It is clearly demonstrated that the current through the switch naturally goes to zero. The negative current shows the antiparallel body diode conduction across the switch before turning off the gating signals, ensuring ZCS turn-off of the primary side semiconductor devices.  Figures 18 and 19 show the steady-state zoomed waveforms under half load and full load, respectively. Figures 18a and 19a show the gate-to-source and drain-to-source Vds voltage waveforms across primary side MOSFET and transformer primary current is waveform at half load and full load, respectively. It is clearly demonstrated that the current through the switch naturally goes to zero. The negative current shows the antiparallel body diode conduction across the switch before turning off the gating signals, ensuring ZCS turn-off of the primary side semiconductor devices.  Figures 18 and 19 show the steady-state zoomed waveforms under half load and full load, respectively. Figures 18a and 19a show the gate-to-source V GS and drain-to-source V ds voltage waveforms across primary side MOSFET and transformer primary current i s waveform at half load and full load, respectively. It is clearly demonstrated that the current through the switch naturally goes to zero. The negative current shows the antiparallel body diode conduction across the switch before turning off the gating signals, ensuring ZCS turn-off of the primary side semiconductor devices.   Voltage waveforms VGS and VDS across the devices clearly demonstrate the ZCS of the primary side devices and ZVS of the secondary side devices under both load conditions. The results are satisfactory during the transients that occurred due to sudden load disturbances while maintaining the steady-state performance. The steady-state performance is not compromised but retained at that originally proposed in [17].
Corresponding gate-to-source and drain-to-source voltage waveforms of the secondary side devices are shown in Figures 18b and 19b. In these waveforms, gate-to-source voltage ( ) is applied when the voltage across secondary device VDS is zero already, which ensures ZVS operation in secondary devices. It confirms the soft-switching of the primary and secondary side devices. Table 3 shows the comparison between the conventional active-clamped converter and the proposed snubberless topology. It is clear from the comparison that the snubberless operation with proposed control has several merits in terms of voltage gain, efficiency, reduced current, transformer size, and soft-switching range. Simple control has resulted in these merits with a demerit of limited duty range.  Figure 19. Experimental results for v in = 12 V at full load: (a) gate-to-source voltage V Gs1 (20 V/div), current across primary-side MOSFET i s1 (20 A/div), and voltage V AB = 50 V/div; (b) gate-to-source voltage V GS3 (20 V/div), drain-to-source voltage V ds3 (200 V/div), and current across secondary-side MOSFET i s3 (2 A/div).
Voltage waveforms V GS and V DS across the devices clearly demonstrate the ZCS of the primary side devices and ZVS of the secondary side devices under both load conditions. The results are satisfactory during the transients that occurred due to sudden load disturbances while maintaining the steady-state performance. The steady-state performance is retained at the originally proposed in [17]. Corresponding gate-to-source V GS and drain-to-source voltage V ds waveforms of the secondary side devices are shown in Figures 18b and 19b. In these waveforms, gate-to-source voltage (V GS ) is applied when the voltage across secondary device V DS is zero already, which ensures ZVS operation in secondary devices. It confirms the soft-switching of all the devices. Table 3 shows the comparison between the conventional active-clamped converter and the proposed snubberless topology. It is clear from the comparison that the snubberless operation with proposed control has several merits in terms of voltage gain, efficiency, reduced current, transformer size, and soft-switching range. Simple control has resulted in these merits with a demerit of limited duty range.

Conclusions
This paper studied small-signal modeling and derived transfer functions of an isolated naturally clamped snubberless current-fed half-bridge DC-DC converter. A two-loop average current controller was designed offering fixed-frequency duty cycle modulation of the semiconductor devices using two controllers. Initial verification of the small-signal model and the controller was done using PSIM 11 and investigation of the dynamic performance of the converter. Experimental results on a laboratory hardware proof-of-concept prototype demonstrated the satisfactory and smooth transient performance of the converter and the effectiveness of the designed closed-loop controller. The simplicity of implementation and practicality of the proposed control are the benefits of the overall system. The proposed analysis is effective for non-isolated as well as interleaved half-bridge and interleaved-boost topologies. It is suitable for fuel cell applications.