Reducing LUT Count for FPGA-Based Mealy FSMs

: Very often, digital systems include sequential blocks which can be represented using a model of Mealy ﬁnite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. The paper proposes a novel design method optimizing LUT counts of LUT-based Mealy FSMs. The method is based on simultaneous use of such methods of structural decomposition as the replacement of FSM inputs and encoding of the collections of outputs. The proposed method results in three-level logic circuits of Mealy FSMs. These circuits have regular systems of interconnections. An example of FSM synthesis with the proposed method is given. The experiments with standard benchmarks were conducted. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). This gain is accompanied by a small loss of FSM performance.


Introduction
One of the features of our time is a wide application of digital systems in various spheres of human activity [1,2]. Modern digital systems include different combinational and sequential blocks [3,4]. The behaviour of a sequential block can be represented using the model of finite state machine (FSM) [5,6]. To improve characteristics of a digital system, it is necessary to improve such characteristics of FSMs as internal occupied resources, performance and power consumption. This necessity explains the continuous interest in developing methods aimed at optimizing these characteristics of FSM circuits. As a rule, the less internal occupied resources are used by an FSM circuit, the less power it consumes [7]. So, it is very important to reduce internal occupied resources consumed by an FSM circuit.
A sequential block can be represented as either Mealy or Moore FSM [5,6]. There are thousands of monographs and articles devoted to problems of FSM circuits design. The vast majority of these works are devoted to Mealy FSMs. Based on this analysis, we have chosen Mealy FSM as the object of research in our current article.

Specifics of FPGAs and Mealy FSMs
The majority of modern FPGAs are organized using so called "island-style" architecture [16,28,30]. They include different configurable logic blocks (CLBs) and a matrix of programmable interconnections [10][11][12]. In this article, we consider CLBs consisting of LUTs and programmable flip-flops. To implement LUT-based circuits of sequential blocks, it is necessary to connect outputs of some LUTs with flip-flops [5].
An extremely small amount of LUT inputs leads to the necessity of functional decomposition [17] of functions representing combinational parts of FSMs. The functional decomposition produces multi-level circuits with irregular systems of interconnections. Such circuits resemble "spaghetti-type" programs [28]. Using terminology from programming, we can say that the functional decomposition produces LUT-based circuits with "spaghetti-type" interconnections.
A Mealy FSM is defined as a vector < X, Y, A, δ, λ, a 1 > [5], where X = {x 1 , . . . , x L } is a set of inputs, Y = {y 1 , . . . , y N } is a set of outputs, A = {a 1 , . . . , a M } is a set of internal states, δ is a function of transitions, λ is a function of output, and a 1 ∈ A is an initial state. A Mealy FSM can be represented using different tools, such as: state transition graphs [3,5], binary decision diagrams [31,32], and-inverter graphs [33], graph-schemes of algorithms [5]. In this article, we use state transition tables (STTs) for this purpose.
An STT includes the following columns [3,5]: a m is a current state; a s is a state of transition (a next state); X h is a conjunction of inputs (or their compliments) determined a transition from a m to a s ; Y h is a collection of outputs generated during the transition from a m to a s . The column h includes the numbers of transitions (h ∈ {1, . . . , H}). For example, the STT (Table 1) represents some Mealy FSM S 1 . x 2 x 3 y 2 y 6 4 a 5 x 2 x 3 y 1 y 4 y 6 5 a 3 a 2 x 4 y 2 y 3 6 a 5 x 4 x 5 y 1 y 7 7 a 6 x 4 x 5 y 4 y 6 8 a 4 a 5 1 y 5 9 a 5 a 2 x 3 x 6 y 2 10 a 3 x 3 x 6 y 3 y 4 11 a 6 x 3 x 7 y 2 y 6 12 a 1 x 3 x 7 y 5 y 7 13 a 6 a 4 x 8 y 2 14 a 1 x 8 − 15 Using STT (Table 1), the following parameters of S 1 can be found: the number of inputs L = 8, the number of outputs N = 7, the number of states M = 6, and the number of transitions H = 15. Furthermore, Table 1 uniquely defines the functions of transitions and output of FSM S 1 .
To find SBFs representing an FSM circuit, it is necessary [5]: (1) to encode states a m ∈ A by binary codes K(a m ); (2) to construct sets of state variables T = {T 1 , . . . , T R } and input memory functions (IMFs) Φ = {D 1 , . . . , D R } and (3) to transform an initial STT into a direct structure table (DST). States a m ∈ A are encoded during the step of state assignment [3].
In this article, we use the state codes having the minimum possible number of state variables This method is used, for example, in well-known academic system SIS [34]. There are other approaches for state encoding where the number of state variables differs from (1). For example, the academic system ABC [33] of Berkeley uses one-hot state assignment with R = M.
State codes are kept into a state register (RG). The RG consists of R flip-flops with mutual inputs of synchronization (Clock) and reset (Start). For LUT-based FSMs, D flip-flops are used to organize state registers [9]. The pulse Clock allows the functions D r ∈ Φ to change the RG content.
To find functions representing an FSM circuit, it is necessary to create a direct structure table. A DST is an expansion of an STT by the columns with codes of current and next states (K(a m ) and K(a s ), respectively). Furthermore, a DST includes a column Φ h with symbols D r ∈ Φ corresponding to 1's in the code K(a s ) from the row h of a DST (h ∈ {1, . . . , H}). The following SBFs are derived from a DST: The systems (2) and (3) determine a structural diagram of Mealy FSM U 1 (Figure 1 from [35]). In Figure 1, the symbol LUTer denotes a logic block consisting of LUTs.

LUTerF
LUTerY T X Y Start Clock In the FSM U 1 , the LUTerΦ implements the system (2), the LUTerY the system (3). If a function D r is generated by a particular LUT, then the LUT's output is connected with a flip-flop [9]. The flip-flops form the state register distributed among the LUTs of LUTerΦ. It explains the existence of pulses Start and Clock as inputs of LUTerΦ.
The main specific of Mealy FSMs is the dependence of input memory functions and outputs on inputs and state variables. So, these functions have the same nature. This specific can be used to minimize hardware in LUT-based Mealy FSM circuits [35]. In Section 4, we will explain how to use this specific.

State of the Art
The process of technology mapping is associated with necessity of the solution of some optimization problems [9,35]. When designing FPGA-based FSMs, four optimization problems arise [35]: (1) the reduction of hardware amount, (2) the improvement of performance, (3) the reduction of power consumption, and (4) the improvement of testability. In this article, we propose a way for solution of the first problem.
takes place, then it is enough a single LUT to implement a circuit for any function f i ∈ Φ ∪ Y. If the condition (4) is violated for some function f i ∈ Φ ∪ Y, then the corresponding circuit is multi-level. In multi-level circuits, it is quite possible that the same inputs x l ∈ X appear on several logic levels. It results in FSM circuits with the spaghetti-type interconnections.
The functional decomposition is a very powerful tool used in the process of technology mapping [19,53]. If the condition (4) is violated, then a function is broken down into smaller and smaller components. The process is terminated when any component has no more than S L arguments.
If the condition (4) takes place, then a Mealy FSM logic circuit has exactly R + N LUTs. Otherwise, an FSM circuit is represented by R + N + |Ψ| functions, where Ψ is a set of additional functions different from (2) and (3). New functions correspond to components of initial functions obtained in the process of decomposition.
A huge number of methods of functional decomposition are known. Some of them can be found, for example, in [19,20,23]. We do not discuss them in our article. All modern FPGA-based CAD systems include program tools for functional decomposition. These tools can be found in academic systems [33,34,54,55], as well as in industrial packages [56][57][58]. The open system DEMAIN [54] includes powerful methods of functional decomposition. Due to this, we chose this system for comparison with our proposed approach.
The optimal state assignment [9] is a process of obtaining state codes optimizing systems of Boolean functions (2) and (3). One of the best academic optimal state assignment algorithms is JEDI distributed with the system SIS [34]. The JEDI is aimed at reducing the numbers of arguments in functions representing a Mealy FSM logic circuit. In this article, we compare JEDI-based FSMs with FSMs based on our proposed approach Different state assignment strategies can be found in modern industrial CAD tools. For example, the design tool Vivado [57] uses the following approaches: the one-hot (R = M); compact; Gray codes; Johnson codes; speed encoding; automatic state assignment (auto). The same methods can be found in the package XST by Xilinx [56].
Because modern FPGAs include a lot of flip-flops, the one-hot state assignment is very popular in LUT-based design [41]. This approach allows producing less complicated combinational parts of FSM circuits than their counterparts based on the binary state encoding where R = log 2 M [35]. As shown in [41], if M ≤ 8, then FSMs based on binary state codes have better characteristics than their counterparts based on one-hot codes. The one-hot codes are more preferable if there is M > 16. However, the characteristics of LUT-based FSM circuits significantly depend on the number of inputs [35]. As it is shown in [42], if L ≤ 10, then it is better to use one-hot state codes. Otherwise, binary state encoding allows producing better FSM circuits. So, both approaches should be compared with our proposed method. We chose the method Auto of Vivado as a method of binary state encoding. This method allows choosing codes producing FSM circuits with the best possible characteristics.
The main goal of both Gray and Johnson state encoding approaches is the reducing switching activity of an FSM circuit. It allows reducing the dynamic power consumption [35]. We do not discuss these methods in detail. Such an analysis can be found, for example, in [42].
So, a large number of state assignment methods are currently known. They are usually focused on optimizing one or more characteristics of FSM circuits. Some of them mostly focus on area reduction. It is very difficult to say which method is the best for a particular FSM. It depends on both the features of FSM and FPGA, as well as on the accepted criteria of FSM circuit optimality.
Each literal of SOP representing a function f i corresponds to a wire in the FSM circuit. So, to diminish the number of interconnections, it is necessary to diminish the numbers of literals in Boolean functions (2) and (3). The fewer interconnections, the less power is consumed [28]. Therefore, the optimal state assignment must be performed regardless of whether the condition (4) is met or not.
Modern FPGAs include a lot of configurable embedded memory blocks [10][11][12]. Replacement of LUTs by EMB allows significantly improve the characteristics of resulting FSM circuits [41]. Because of it, there are a lot of design methods for EMB-based FSMs [43,44,[46][47][48][49]59]. The survey of different methods of EMB-based design can be found in [60]. Unfortunately, these methods can be used only if there are "free" EMBs, which are not used to implement other parts of a digital system.
To optimize a LUT-based FSM circuit, it is necessary to eliminate a direct dependence of functions y n ∈ Y and D r ∈ Φ on inputs x l ∈ X. It is a main goal of different methods of a structural decomposition [35]. To eliminate this dependence, new functions f i ∈ Ψ are introduced to eliminate this dependence. These new functions depend on inputs and/or state variables. To optimize an FSM circuit, the following condition should take place: Each system of new functions determines a separate block LUTer with its unique input and output variables. These blocks can be viewed as "hardware subroutines" by analogy with subroutines in programming [61,62]. If the relation (5) takes place, then the total number of LUTs implementing functions f i ∈ Ψ is significantly less than their total number in blocks LUTerΦ and LUTerY of an equivalent FSM U 1 . Using hardware subroutines allows structuring an FSM circuit. The functions f i ∈ Ψ are used as arguments of functions (2) and (3). If the condition is true, then the total number of LUTs in an FSM circuit is significantly less than it is for an equivalent FSM U 1 . If (6) takes place, then the structural decomposition leads to reduced number of literals in SOPs of functions f i ∈ Φ ∪ Y as compared to initial functions (2) and (3). In turn, it reduces the total number of LUTs in blocks LUTerΦ and LUTerY (as compared to U 1 ). If condition (4) is violated for some functions f i ∈ Φ ∪ Y ∪ Ψ, then the methods of functional and structural decomposition should be used together in the process of technology mapping. A survey of different methods of structural decomposition can be found in [35].
In this article, we discuss two methods of structural decomposition. They are the methods of replacement of inputs and encoding of outputs. They have been proposed to minimize the control memory size in microprogram control units (MCU) [63]. Next, they were applied in PLA-based FSMs [64]. Each of these methods was used separately in EMB-based FSM design [44,45,48,60]. However, they have never been used in LUT-based FSM design. In this article, we propose to combine these methods together to optimize characteristics of LUT-based Mealy FSMs.
The first method is a replacement of inputs x l ∈ X by additional variables p g ∈ P = {p 1 , . . . , p G } where G L [64]. To do it, it is necessary to create an SBF In MCUs, SBF (7) is implemented using a multiplexer. The additional variables are used as arguments of functions f i ∈ Φ ∪ Y . These functions are represented as The functions (8) and (9) have a regular nature [35]. So, they can be implemented as a memory block having G + R address inputs and N + R outputs.
Using this approach leads to FSM U 2 shown in Figure 2. It includes a multiplexer implementing SBF (7) and a memory block implementing systems (8)  In the classical MCU [63], only a single input is checked in each cycle of operation (G = 1). This results in rather slow control units. To decrease the number of cycles required for implementing a control algorithm, it is necessary to increase the value of G. To optimize an MCU performance, the value of G is determined as [64]: In (10), the symbol X(a m ) stands for the set of inputs determining transitions from the state a m ∈ A.
The model U 2 was used in the FPGA-based design. Different U 2 -based approaches are discussed, for example, in [60]. In all discussed cases, EMBs implement systems (8) and (9). The system (7) is implemented with LUTs.
Collections of outputs (COs) Y q ⊆ Y(q ∈ {1, . . . , Q}) are generated during interstate transitions. The minimum number of bits in the code K(Y q ) is determined as To encode COs by codes K(Y q ), some additional variables z r ∈ Z = {z 1 , . . . , z R Q } are used. If COs are encoded, then the system of outputs is represented as In the case of MCU, the system (12) is implemented using two blocks, namely, a decoder and a coder [35].
To generate the additional variables z r ∈ Z, it is necessary to find an SBF In the case of MCU, both systems (13) and (2) are implemented by a memory block. In the case of FPGA-based design, a memory block is represented as a network of EMBs.
Using the encoding of COs in FPGA-based design leads to Mealy FSM U 3 shown in Figure 3.
So far, these methods have been used separately to improve characteristics of circuits of FPGA-based FSMs. Moreover, some parts of FSM circuits have been implemented using EMBs [45,47]. In this article, we propose to use these methods together. Moreover, all functions are implemented by LUTs. This approach leads to Mealy FSM logic circuits having three levels of logic. The circuit for each level of logic can be viewed as a hardware subroutine. This approach allows structuring a resulting FSM circuit and makes the system of interconnections more regular. We denote the proposed Mealy FSM by the symbol U 4 .

Main Idea of the Proposed Method
Consider some Mealy FSM S i represented by an STT. We assume that the following procedures have been executed: (1) the replacement of inputs; (2) the encoding of COs; (3) the encoding of states and (4) the transformation of initial STT into the DST of FSM U 1 . To get SBFs representing U 4 , we should transform the DST of FSM U 1 into a DST of Mealy FSM U 4 .
To obtain the arguments of functions (8) and Z(T, P), it is necessary to replace the column X h of the DST of FSM U 1 by the column P h . It is executed in the following way: if an additional variable p g ∈ P replaces an input x l ∈ X for a state a m ∈ A, then the variable x l (or its negation) from the column X h is replaced by the variable p g (or its negation) in the column P h for all transitions from the state a m ∈ A.
To obtain functions Z(T, P), it is necessary to replace the column Y h of the DST of FSM U 1 by the column Z h . The filling of the column Z h is executed in the following manner. If the h-th row of DST includes a CO Y q ⊆ Y such that the r-th bit of K(Y q ) is equal to 1, then the symbol z r should be written in the h-th row of the column Z h of DST of FSM U 4 .
Using a DST of FSM U 4 , we can derive the systems (8) and Using the table of replacement of inputs, we can get the system (7). Next, using the content of collections of outputs, we can obtain the system (12).
Until now, the methods of replacement of inputs and encoding of the collections of outputs were used separately in EMB-based Mealy FSM design. In this article, we propose to use them together in LUT-based Mealy FSMs. There are three levels of logic blocks in the proposed Mealy FSM U 4 . Its structural diagram is shown in Figure 4.  In FSM U 4 , the first level of logic is represented by a block LUTerP, the second level includes blocks LUTerZ and LUTerT, the third level includes a block LUTerY. The blocks implement the following SBFs: the LUTerP implements the system (7), the LUTerZ the system (14), the LUTerT the system (8), and the LUTerY the system (12).
takes place, then the LUTerZ consists of R Q LUTs and LUTerT of R LUTs. It is the best possible case. If the condition (15) is violated, then it is necessary to apply the methods of functional decomposition for some functions from SBFs (8) and (14).
takes place, then there are exactly N LUTs in the circuit of the LUTerY. If this condition is violated, then it is necessary to apply the methods of functional decomposition for some functions from SBF (12).
In this article, we propose a design method for Mealy FSM U 4 . We assume that an FSM is represented by an STT. The method includes the following steps: 1. Executing the replacement of inputs by additional variables p g ∈ P.
2. Executing the state assignment in a way optimizing the SBF P = P(X, T). 3. Deriving the collections of outputs Y q ⊆ Y from the STT. 4. Executing the encoding of COs in a way optimizing the SBF Y = Y(Z). 5. Creating the DST of FSM U 4 on the base of initial STT. 6. Deriving the SBFs (7), (8), (12) and (14) from the DST. 7. Implementing circuit of FSM using particular LUTs.
Some steps of the proposed method are connected with solution of optimization problems. We discuss these problems in the following Section.

Example of Synthesis
If a Mealy FSM S j is synthesized using a model U i , then we denote it by the symbol U i (S j ). Consider an example of synthesis for Mealy FSM U 4 (S 1 ). An FSM circuit will be implemented using LUTs with S L = 6.
We should construct a table of replacement of inputs [35]. This table has M columns marked by states a m ∈ A and G rows marked by variables p g ∈ P. If an input x l ∈ X is replaced by a variable p g ∈ P in the state a m ∈ A, then there is the symbol x l written at the intersection of the column a m and the row p g [64].
Inputs x l ∈ X written in a row p g form a set X(p g ) ⊆ X. If |X(p g )| ≤ S L − R, then the circuit generating p g ∈ P is implemented as a single LUT. In the discussed case, there is S L − R = 3. To optimize the circuit of LUTerP, we should distribute inputs x l ∈ X in a way providing the relation |X(p g )| ≤ 3 (g ∈ {1, . . . , G}). It could be done using the approach from [64]. One of the possible solutions is shown in Table 2.  1 a 2 a 3 a 4 a 5 a 6 p 1 Executing the state assignment. To optimize the circuit of LUTerP, it is necessary to diminish the number of literals in functions (7) [64]. It can be done due to a proper state assignment. These methods are based on results of the work [64].
Using (1) gives R = 3. So, there are the sets T = {T 1 , T 2 , T 3 } and Φ = {D 1 , D 2 , D 3 }. One of the possible outcomes of the state assignment is shown in Figure 5. Deriving the collections of outputs. This step is executed in the trivial way. The collections Y q ⊆ Y are written in the column Y h of an STT. Using Table 1, the following COs can be found: To optimize the circuit of LUTerY, it is necessary to minimize the number of literals in functions (12). Furthermore, it allows minimizing the number of interconnections between the blocks LUTerZ and LUTerY.
Executing the encoding of COs. We start this process from a system representing outputs y n ∈ Y. as functions of collections Y q ⊆ Y. It is the following system in the discussed case: There are Q = 10 collections of outputs in the discussed case. Using (11) gives R Q = 4 and Z = {z 1 , . . . , z 4 }. Using the method [64] allows obtaining codes of COs shown in Figure 6.  Creating the DST of FSM U 4 (S 1 ). Having codes of states and COs, we can transform the initial STT (Table 1) into a DST of Mealy FSM U 4 (S 1 ) (Table 3).
Consider the row h = 1 of Table 3. There is a m = a 1 and a s = a 2 . As follows from Figure 5, the code of a 2 is equal to 010. Due to it, there is the symbol D 2 in the column Φ h . There is the symbol x 1 in the row 1 of STT. As follows from Table 2, the input x 1 is replaced by the variable p 1 for the state a 1 ∈ A. Due to it, there is the symbol p 1 in the first row of DST (Table 3). There is the collection of outputs Y 2 = {y 1 , y 7 } in the first row of Table 1. As follows from Figure 6, there is K(Y 2 ) = 0100. Due to it, there is the symbol z 2 in the row 1 of DST (Table 3). All other rows of Table 3 are filled in the same way.
Deriving SBFs representing the circuit of U 4 (S 1 ). During this step, the functions (7), (8), (12) and (14) should be found. It can be done using Tables 2 and 3, as well as codes from Karnaugh maps shown in Figures 5 and 6.
We start from the SBF (7). We use the symbol A m to denote a conjunction of state variables (or their complements) corresponding to the code K(a m ).
The following system can be derived from Table 2: Using codes from Figure 5, we can get the following minimized functions: In the discussed case, the system (19) represents LUTerP. Each equation of (19) includes not more than six literals. Because S L = 6, there are only G = 3 LUTs in the circuit of LUTerP.
Each row of DST of FSM U 4 corresponds to the product term In (20), the symbol B h denotes a conjuction of variables p g (or their compliments) written in the column P h of DST.
The functions (8) and (14) depend on terms (20). For example, the following equations can be derived from Table 3: All other functions D r ∈ Φ and z r ∈ Z are constructed in the same manner.
In the discussed case, there is R + G = 6. Because S L = 6, the condition NL( f i ) ≤ S L takes place for any function f i ∈ Φ ∪ Z. It means that there are R=3 LUTs in the circuit of LUTerT and R Q = 4 LUTs in the circuit of LUTerZ.
Using system (17) and codes from Figure 6, we can get the following system: The analysis of (23) shows that there is no need in a LUT to implement the function y 2 . Because R Q = 4 is less than S L = 6, the condition (16) takes place. So, it is necessary N − 1 = 6 LUTs to implement LUTerY.
In general case, each function from (12) has R Q literals. For N functions, it gives R Q · N literals. In the discussed case, there is R Q · N = 4 · 7 = 28 literals. Each literal corresponds to the interconnection between blocks LUTerZ and LUTerY. As follows from (23), there are 16 literals in this system. It gives a 42% savings in the number of interconnections compared to the general case. This economy is achieved due to chosen encoding of COs Y q ⊆ Y. It should give economy in the power consumption.
The last step of design is connected with the placement and routing procedures [16]. It is executed using industrial CAD tools such as, for example, Vivado by Xilinx [57]. We do not discuss this step for a given example.
It is known that any sequential block can be represented using either model of Mealy FSM or Moore FSM [3]. There is the following specific of Moore FSM: its outputs depend only on states. It means that, for Moore FSMs, state codes can be viewed as the codes of collections of outputs. So, there is no sense in using additional variables encoding the collections of outputs. It means that the proposed approach can be used only in the case of LUT-based Mealy FSMs.

Experimental Results
To investigate the efficiency of proposed method, we use standard benchmarks from the library [29]. The library includes 48 benchmarks taken from the design practice. The benchmarks are rather simple, but they are very often used by different researches to compare new and known results [9,43]. The benchmarks are represented in KISS2 format. These benchmarks are Mealy FSMs, so we can directly use them in our research. The characteristics of these benchmark FSMs are shown in Table 4.
The process of obtaining synthesis research results in Vivado [57] has been divided into two stages. The first stage was a generation of the VHDL code based on benchmarks saved in the KISS2 format. Each benchmark was generated by the tool K2F [35,45] according to the given FSM model. It should be noted that generated code uses a specific Vivado code style [65] in order to provide the proper FSM extraction and fully synthesizable code. Then, in the next stage, the VHDL code was imported into Vivado (ver. 2019.1). The target device was the Xilinx Virtex 7 (XC7VX690TFFG1761) [66]. The chip includes LUTs with six inputs. The synthesis and optimization options were set to: max_bram 0, opt_design -retarget -propconst -bram_power_opt and the selected FSM state encoding method one of the following: auto, one_hot, sequential, johnson or gray. The final results presented in the tables are taken after the post-implementation. As we have found, our method can give economy in area if R + L > S L . We have divided the benchmarks into categories using the values of L + R and S L . If L + R ≤ 6, then benchmarks belong to category 0 (trivial FSMs); if L + R ≤ 12, then to category 1 (simple FSMs); if L + R ≤ 18, then to category 2 (average FSMs); if L + R ≤ 24, then to category 3 (big FSMs); otherwise, they belong to category 4 (very big FSMs). Obviously, there is no sense to apply our approach to FSMs belonging to category 0. As our researches show, the higher the category, the more saving the proposed approach gives.  Table 5 (the number of LUTs) and Table 6 (the operating frequency).  43  61  40  42  37  1  kirkman  42  58  39  41  33  2  lion  2  5  2  2  6  0  lion9  6  11  5  5  8  0  mark1  23  23  20  21  19  1  mc  4  7  4  5  6  0  modulo12  7  7  7  7  9  0  opus  28  28  22  26  21  1  planet  131  131  88  94  78  2  planet1  131  131  88  94  78  2  pma  94  94  86  91  72  2  s1  65  99  61  64  54  2  s1488  124  131  108  112  89  2  s1494  126  132  110  117  90  2  s1a  49  81  43  54  38  2  s208  12  31  10  11  9  2  s27  6  18  6  6  6  1  s386  26  39  22  25  20  1  s420  10  31  9  10  8  4  s510  48  48  32  39  22  4  s8  9  9  9  9  9  1  s820  88  82  68  76  52  4  s832  80  79  62  70  50  4  sand  132  132  114  121  99  3  shiftreg  2  6  2  2  4  0  sse  33  37  30  32  26  1  styr  93  120  81  88  70  2  tma  45  39  39  41  30  2   Total  1792  2104  1480  1601 Tables 5 and 6 are organized in the same order. The rows are marked by the names of benchmarks, the columns by design methods. The rows "Total" include results of summation for corresponding values. The summarized characteristics of our approach (U 4 -based FSMs) are taken as 100%. The rows "Percentage" show the percentage of summarized characteristics of FSM circuits implemented by other methods respectively to benchmarks based on our approach. Let us point out that the model U 1 is used for designs with Auto, One-hot, JEDI and DEMAIN. Furthermore, for better visualization, summary data are presented in the Figures 7-9.  As follows from Table 5 and Figure 7, the U 4 -based FSMs required fewer LUTs than it is for other investigated methods. There is the following economy: (1) 35.65% regarding Auto; (2) 59.27% regarding One-hot; (3) 12.04% regarding JEDI-based FSMs and (4) 21.20% regarding DEMAIN-based FSMs. The higher is the category, the greater is the gain in LUTs. For trivial and simple FSMs, the better results are produced by either JEDI or DEMAIN. The gain are becoming more and more noticeable, starting from the average FSMs.
As follows from Table 6 and Figure 8, the U 4 -based FSMs have a lower operating frequency than it is for other investigated methods. There is the following loss: (1) 2.65% regarding Auto; (2) 1.82% regarding One-hot; (3) 10.13% regarding JEDI-based FSMs and (4) 6.87% regarding DEMAIN-based FSMs. However, starting from big FSMs, the losses are getting smaller. It is connected with the fact that U 4 --based FSMs always have three levels of logic and more regular system of interconnections. The main goal of the proposed approach is to reduce the LUT count in circuits of FPGA-based Mealy FSMs. As follows from Table 5, the degree of reduction in the number of LUTs depends on the category of an FSM. To clarify this dependence, we have created Table 7 (experimental results for category 0), Table 8 (experimental results for category 1) and Table 9 (experimental results for categories 2-94). Furthermore, we present these results by graphs on Figures 9-11, respectively. As follows from Table 7 and Figure 9, the proposed method produces FSM circuits having more LUTs than it is for other investigated methods. Our method has the following loss: (1) 30.34% regarding Auto; (2) 3.37% regarding One-hot; (3) 31.46% regarding JEDI-based FSMs and (4) 28.09% regarding DEMAIN-based FSMs. So, there is no sense in using our approach for designing trivial FSMs. However, it gives an economy in LUTs starting from simple FSMs (category 1).
Till now, we compared our approach with U 1 -based FSMs. However, we also compared the U 4 -based FSMs with FSMs having two levels of logic. The structural diagrams of these FSMs are shown in Figure 12. The FSM U 5 is based on the replacement of inputs (Figure 12a). There is no such an FSM in the known literature. We have got its structural diagram by transformation the FSM U 2 (Figure 2). We replaced the multiplexer by the block LUTerP; the memory block is replaced by LUTerTY. The LUTerP implements the system (5), the LUTerTY the systems (6)    The FSM U 6 is based on the encoding of collections of outputs (Figure 12b). There is no such an FSM in the known literature. We have got its structural diagram by transformation the FSM U 3 (Figure 3). We replaced the block EMBer by the block LUTerTZ generating functions (2) and (11). As it is for FSM U 3 , the LUTerY implements the system (10).
The FSM U 7 is based on the transformation of state codes into outputs (Figure 12c) [35]. In this FSM, additional variables from the set V replace inputs for output functions. The FSM U 8 is based on the transformation of collections of outputs into state codes (Figure 12d) [35]. In this FSM, additional variables from the set V replace inputs for input memory functions. Both methods belong to the group of object transformation methods [35]. We do not discuss these approaches in this article. We just use them as examples of FSMs having two levels of logic. We compared the FSMs ( Figure 12) with our approach for the most complex benchmarks (categories 2-4). The results of experiments are shown in Table 10 and Figure 13. As follows from Table 10, our method produces better results for FSMs than it is for FSMs U 5 -U 8 . There is the following economy: (1) 17.11% regarding U 5 ; (2) 11.95% U 6 (3) 20.18% regarding U 7 and 4) 9.1% regarding U 8 . So, our approach produces FSM circuits with better amount than two-level Mealy FSMs having L + R ≥ 12. However, the gain is noticeably less than for U 1 -based FSMs from these categories. So, the results of our experiments show that the proposed approach can reduce the LUT counts respectively to single-and two-level Mealy FSMs having L + R ≥ 12. Of course, this conclusion is true only for benchmarks [27] and the device XC7VX690tffg1761-2 by Virtex-7, where LUTs have 6 inputs. It is almost impossible to make a similar conclusion for the general case. However, we hope that our approach rather good potential and can be used in CAD systems targeting FPGA-based Mealy FSMs.

Conclusions
Contemporary FPGA devices include a lot of look-up table elements. This allows implementing a very complex digital system using only a single chip. However, LUTs have rather small amount of inputs (for the vast majority of devices the value of S L does not exceeds 6). This value is considered as optimal [26,28]. To design rather complex FSMs, the methods of functional decomposition are used. As a rule, this leads to multi-level FSM circuits with complex systems of spaghetti-type interconnections.
To optimize the LUT counts in FPGA-based FSM circuits, different methods of structural decomposition could be applied. As our researches [35] show, the structural decomposition can lead to FSM circuits having better characteristics than their counterparts based on the functional decomposition. They have regular system of interconnections and predicted number of logic levels.
The current article is devoted to a novel approach aimed at optimization of LUT-based Mealy FSMs. The proposed approach is based on simultaneous use of such methods of structural decomposition as the replacement of inputs and encoding of collections of outputs. Till now, the methods of replacement of inputs and encoding of the collections of outputs were used separately in EMB-based Mealy FSM design. In this article, we propose to use them together in LUT-based Mealy FSMs. Furthermore, we encode the collections in a way minimizing the number of interconnections between other blocks and the block generating FSM outputs. The proposed approach leads to three-level Mealy FSM circuits with regular systems of interconnections.
We compared the proposed approach with FSM circuits obtained using the Xilinx CAD tool Vivado 2019.1. These circuits were obtained using four different approaches: Auto by Vivado, One-hot by Vivado, JEDI and DEMAIN. The experiments clearly show that the proposed approach leads to reducing the number of LUTs in comparison with FSM circuits produced by other investigated methods. The results of experiments show that the proposed approach leads to reducing the LUT counts from 12% to 59% in average compared with known methods of synthesis of single-level FSMs. Furthermore, our approach provides better LUT counts as compared to methods of synthesis of two-level FSMs (from 9% to 20%). However, our approach leads to slower FSM circuits as compared to other investigated methods. Thus, our approach reduces the overall performance of a digital system including U 4 -based FSMs. So, the proposed method can be used if the LUT count is the dominant characteristic of a digital system.
There are two directions in our future research. The first is connected with development of design methods targeting FPGA chips of Intel (Altera). The second direction targets at EMB-based Mealy FSMs.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations are used in this manuscript: