Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

: Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (V DD ) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large V DD ( > 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate ﬁeld e ﬀ ect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower V DD .


Introduction
Tunneling-based ternary complementary metal-oxide-semiconductor (TCMOS) technology has been reported recently [1][2][3]. Instead of the binary systems of the existing complementary metal-oxide-semiconductor (CMOS) technology, the third output voltage (V out ) state is formed in the ternary systems, and it has been spotlighted in terms of scaling and energy-efficiency [4,5]. In the TCMOS, the off-current (I OFF ) levels of NMOS (n-type MOS) and PMOS (p-type MOS), which are generated by band-to-band tunneling (BTBT), should be matched to form the third V out state during inverter operations. In contrast to conventional ternary devices that utilize multithreshold voltage (Multi-V t ) transistors [6][7][8][9][10][11][12], the TCMOS can perform ternary operations using a pair of NMOS/PMOS with a single voltage (V t ); the fabrication process is also comparable to the conventional CMOS process, because it can be fabricated only by introducing one additional doping process. However, the TCMOS has the disadvantage of slow switching speed caused by low on-state current (I ON ). In general CMOS, the time required for V out state transition is sub-nsec, while it takes~µsec for the TCMOS to be switched [1].
In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS), consisting of ferroelectric-gate field effect transistor (FeFET), is proposed to improve switching speed and supply voltage (V DD ) scaling since it is well-known that the FeFET boosts I ON and steepens

Experiments and Simulation Methods
To embody the ferroelectricity in FE-TCMOS (Figure 1a,b), a metal-ferroelectric-metal (MFM) capacitor was first fabricated using hafnium zirconium oxide (HZO) as ferroelectric material, and polarization-electric field (P-E) characteristics were obtained. Then, the simulation parameters of the ferroelectric material were achieved by fitting the simulation data to the measurement P-E data (Figure 1c) using the Sentaurus 2-D TCAD simulations where Preisach model was used for the calibration [18]. The equation for the model is as follows: where E is electric field, P aux is auxiliary polarization, and where P s is saturation polarization, P r is remanent polarization, E c is coercive field, and τ p is relaxation time for polarization in ferroelectric material. Figure 1c indicates that the measured and the calibrated P-E curves are well-matched [15]. Here, the relaxation time τ p is set to 250 ns. These ferroelectric material parameters are reflected to the gate dielectric of FE-TCMOS for the simulations, whereas high-k dielectric (ε b = 25) is applied instead of the ferroelectric material for TCMOS simulations. Figure 1a shows the schematic diagram of the FE-TCMOS implemented in the simulations. A P-N junction is formed by introducing an additional doped layer between the source and the drain under the channel. When a drain voltage (V D ) is applied, the band-to-band tunneling (BTBT) is generated at the drain-side P-N junction of the layer, and thus the P-N junctions formed by adding the doped layer can be modeled as a drain-side tunnel junction diode. Figure 1b is the circuit schematic diagram of the FE-TCMOS, which shows that the tunnel junction diode is connected to the V out node as contrast to a conventional CMOS. Specific simulation parameters are listed in Table 1.

Experiments and Simulation Methods
To embody the ferroelectricity in FE-TCMOS (Figure 1a,b), a metal-ferroelectric-metal (MFM) capacitor was first fabricated using hafnium zirconium oxide (HZO) as ferroelectric material, and polarization-electric field (P-E) characteristics were obtained. Then, the simulation parameters of the ferroelectric material were achieved by fitting the simulation data to the measurement P-E data ( Figure 1c) using the Sentaurus 2-D TCAD simulations where Preisach model was used for the calibration [18]. The equation for the model is as follows: where E is electric field, Paux is auxiliary polarization, and = where Ps is saturation polarization, Pr is remanent polarization, Ec is coercive field, and τp is relaxation time for polarization in ferroelectric material. Figure 1c indicates that the measured and the calibrated P-E curves are well-matched [15]. Here, the relaxation time τp is set to 250 ns. These ferroelectric material parameters are reflected to the gate dielectric of FE-TCMOS for the simulations, whereas high-k dielectric (εb = 25) is applied instead of the ferroelectric material for TCMOS simulations. Figure 1a shows the schematic diagram of the FE-TCMOS implemented in the simulations. A P-N junction is formed by introducing an additional doped layer between the source and the drain under the channel. When a drain voltage (VD) is applied, the band-to-band tunneling (BTBT) is generated at the drain-side P-N junction of the layer, and thus the P-N junctions formed by adding the doped layer can be modeled as a drain-side tunnel junction diode. Figure 1b is the circuit schematic diagram of the FE-TCMOS, which shows that the tunnel junction diode is connected to the Vout node as contrast to a conventional CMOS. Specific simulation parameters are listed in Table 1.

Tunneling-Based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor
Before identifying the operations of TCMOS, the electrical characteristics of TNMOS (tunneling-based ternary NMOS) and TPMOS (tunneling-based ternary PMOS) were first verified ( Figure 2). Compared to conventional N/PMOS for CMOS, TNMOS/TPMOS have the larger V t (close to V DD ) and the constant I OFF regardless of gate voltage (V G ). As aforementioned, the I OFF is generated by the BTBT at the drain-side tunnel junction and hence the I OFF increases with the larger V D (Figure 3). For the stable TCMOS operations, the I OFF of TNMOS /TPMOS needs to be almost the same at V D =~half V DD because the third V out state between V out = 0 V and V out = V DD is formed using V DD divided by the resistance difference (namely, the I OFF difference) between them [2], if the TNMOS /TPMOS are simplified as variable resistors with respect to V D . Thus, the doping concentration modulation for the tunneling layer is essential to adjust the I OFF in the TCMOS fabrication process.

Tunneling-based ternary CMOS with Ferroelectric-Gate Field effect transistor
Before identifying the operations of TCMOS, the electrical characteristics of TNMOS (tunnelingbased ternary NMOS) and TPMOS (tunneling-based ternary PMOS) were first verified ( Figure 2). Compared to conventional N/PMOS for CMOS, TNMOS/TPMOS have the larger Vt (close to VDD) and the constant IOFF regardless of gate voltage (VG). As aforementioned, the IOFF is generated by the BTBT at the drain-side tunnel junction and hence the IOFF increases with the larger VD ( Figure 3). For the stable TCMOS operations, the IOFF of TNMOS /TPMOS needs to be almost the same at VD = ~ half VDD because the third Vout state between Vout = 0 V and Vout = VDD is formed using VDD divided by the resistance difference (namely, the IOFF difference) between them [2], if the TNMOS /TPMOS are simplified as variable resistors with respect to VD. Thus, the doping concentration modulation for the tunneling layer is essential to adjust the IOFF in the TCMOS fabrication process. The ferroelectric material (e.g., doped HfO 2 ) can have the larger permittivity by a polarization switching than the general high-k dielectric material (e.g., HfO 2 ). The slope of the P-E curve refers to the permittivity of the dielectric, and the slope of the P-E curve in the ferroelectric material is larger than that of the high-k dielectric. Therefore, when the high-k dielectric is replaced with the ferroelectric layer in the gate stack of a MOSFET, the larger I ON and the steeper SS are achievable. Figure 4a shows the comparison of the transfer characteristics between conventional TNMOS/TPMOS and FE-TNMOS (ferroelectric-gate field effect transistors-TNMOS)/TPMOS. As expected, the larger I ON and the improved SS are observed in the FE-TNMOS/FE-TPMOS (ferroelectric-gate field effect transistors-TPMOS) (Figure 4a). Considering that the high V t is inevitable for TCMOS operations, it is expected that FE-TCMOS can be operated at the more scaled V DD . In other words, at a specific V DD , FE-TCMOS might have a faster operation speed and a larger static noise margin than conventional TCMOS. The ferroelectric material (e.g., doped HfO2) can have the larger permittivity by a polarization switching than the general high-k dielectric material (e.g., HfO2). The slope of the P-E curve refers to the permittivity of the dielectric, and the slope of the P-E curve in the ferroelectric material is larger than that of the high-k dielectric. Therefore, when the high-k dielectric is replaced with the ferroelectric layer in the gate stack of a MOSFET, the larger ION and the steeper SS are achievable. Figure 4a shows the comparison of the transfer characteristics between conventional TNMOS/TPMOS and FE-TNMOS (ferroelectric-gate field effect transistors-TNMOS)/TPMOS. As expected, the larger ION and the improved SS are observed in the FE-TNMOS/FE-TPMOS (ferroelectric-gate field effect transistors-TPMOS) (Figure 4a). Considering that the high Vt is inevitable for TCMOS operations, it is expected that FE-TCMOS can be operated at the more scaled VDD. In other words, at a specific VDD, FE-TCMOS might have a faster operation speed and a larger static noise margin than conventional TCMOS.  The ferroelectric material (e.g., doped HfO2) can have the larger permittivity by a polarization switching than the general high-k dielectric material (e.g., HfO2). The slope of the P-E curve refers to the permittivity of the dielectric, and the slope of the P-E curve in the ferroelectric material is larger than that of the high-k dielectric. Therefore, when the high-k dielectric is replaced with the ferroelectric layer in the gate stack of a MOSFET, the larger ION and the steeper SS are achievable. Figure 4a shows the comparison of the transfer characteristics between conventional TNMOS/TPMOS and FE-TNMOS (ferroelectric-gate field effect transistors-TNMOS)/TPMOS. As expected, the larger ION and the improved SS are observed in the FE-TNMOS/FE-TPMOS (ferroelectric-gate field effect transistors-TPMOS) (Figure 4a). Considering that the high Vt is inevitable for TCMOS operations, it is expected that FE-TCMOS can be operated at the more scaled VDD. In other words, at a specific VDD, FE-TCMOS might have a faster operation speed and a larger static noise margin than conventional TCMOS.

Operation Characteristics of FE-TCMOS
Prior to the evaluation of FE-TCMOS, the voltage transfer characteristics (VTC) of conventional TCMOS and CMOS were first verified. Figure 5a shows the VTC of TCMOS and CMOS where it can be confirmed that TCMOS is stably operated with V DD = 1 V as a ternary CMOS with the third V out state. Then, FE-TCMOS and FE-CMOS were embodied by reflecting the calibrated ferroelectric material parameters to the gate stack. To evaluate the electrical characteristics of FE-TCMOS and FE-CMOS, a 7-stage inverter chain was configured in mixed-mode device and circuit simulations as shown in Figure 5b. The input pulse, which has the transition from 0 V to V DD (1 V) with 1 ms rising time, was applied, and the average propagation delay of V out was extracted as the switching time from each inverter stage. Figure 5c demonstrates the switching time as a function of the number of inverter stages. It is found that the FE-TCMOS has the slower switching speed than the FE-CMOS. It has been reported that the tunneling-based TCMOS has the slower (µsec order) switching speed compared to that (psec order) of the CMOS [1], because the switching delay of an inverter is proportional to the driving current of n/p-type transistors. That is, TNMOS/TPMOS not only have the low I ON due to the high V t , but 0 V to half V DD and V DD to half V DD transitions are formed by the I OFF .
Considering the 250 ns ferroelectric relaxation time (namely, polarization switching time) obtained in the previous study [15], if the ferroelectric layer is introduced to the CMOS, the boosted I ON and the steeper SS cannot be achieved since the switching speed of the CMOS inverter is much faster than the polarization switching. This means that a ferroelectric material having a faster switching speed (sub-psec polarization switching) than the CMOS switching is required to apply the ferroelectric layer to conventional CMOS. In contrast, the operating speed of the tunneling-based TCMOS is slower than the polarization switching of the ferroelectric material. Therefore, the ferroelectric layer can effectively play a role as a current booster in the TCMOS.
faster than the polarization switching. This means that a ferroelectric material having a faster switching speed (sub-psec polarization switching) than the CMOS switching is required to apply the ferroelectric layer to conventional CMOS. In contrast, the operating speed of the tunneling-based TCMOS is slower than the polarization switching of the ferroelectric material. Therefore, the ferroelectric layer can effectively play a role as a current booster in the TCMOS.
Subsequently, the switching speed is compared between FE-TCMOS and TCMOS with respect to the number of inverter stages. Figure 6a shows that the switching delay difference between them is negligible, because the switching speed is determined by the IOFF and both devices have almost the same IOFF. The static noise margin (SNM) of FE-TCMOS was investigated from the butterfly curves with various VDDs (0.5 V, 0.7 V, and 1.0 V), and the SNMs were compared with those of TCMOS. Figure 6b indicates that the FE-TCMOS has the sufficient SNM even at low VDD. Additionally, Figure  6c shows the SNM comparison between FE-TCMOS and TCMOS. The improvement of the SNM is extracted as the increase of the SNM in percentage with respect to VDD. It is observed that the FE-TCMOS has the larger SNM and the SNM becomes improved further at the lower VDD, implying that the FE-TCMOS is more advantageous as VDD decreases. These results can be understood better by the steeper SS and the larger ION of FE-TNMOS/TPMOS than by conventional TNMOS/TPMOS.  Subsequently, the switching speed is compared between FE-TCMOS and TCMOS with respect to the number of inverter stages. Figure 6a shows that the switching delay difference between them is negligible, because the switching speed is determined by the I OFF and both devices have almost the same I OFF . The static noise margin (SNM) of FE-TCMOS was investigated from the butterfly curves with various V DD s (0.5 V, 0.7 V, and 1.0 V), and the SNMs were compared with those of TCMOS. Figure 6b indicates that the FE-TCMOS has the sufficient SNM even at low V DD . Additionally, Figure 6c shows the SNM comparison between FE-TCMOS and TCMOS. The improvement of the SNM is extracted as the increase of the SNM in percentage with respect to V DD . It is observed that the FE-TCMOS has the larger SNM and the SNM becomes improved further at the lower V DD , implying that the FE-TCMOS is more advantageous as V DD decreases. These results can be understood better by the steeper SS and the larger I ON of FE-TNMOS/TPMOS than by conventional TNMOS/TPMOS.

Conclusions
In this study, we investigated the ternary CMOS with the ferroelectric layer as a gate oxide. By utilizing the higher capacitance of the ferroelectric layer instead of the conventional high-k dielectric,

Conclusions
In this study, we investigated the ternary CMOS with the ferroelectric layer as a gate oxide. By utilizing the higher capacitance of the ferroelectric layer instead of the conventional high-k dielectric, the larger I ON and the steeper SS were obtained, compared to conventional MOSFETs with high-k gate oxide, which leads to the more stable (larger SNM) ternary inverter operations at the lower V DD . It has the advantage of being completely compatible with existing processes [19]; moreover, through the switching speed comparison between TCMOS and CMOS, it is confirmed that the ferroelectric polarization switching is faster than the tunneling-based ternary inverter switching and thus the ferroelectric layer can play a role as a current booster in TCMOS.