Two-Phase Interleaved Boost Converter with ZVT Turn-On for Main Switches and ZCS Turn-O ﬀ for Auxiliary Switches Based on One Resonant Loop

: A two-phase interleaved boost converter with soft switching is proposed herein. By means of only one auxiliary circuit with two auxiliary switches having zero-current switching (ZCS) turn-on, two main switches are switched on with zero-voltage transition (ZVT) to enhance the overall e ﬃ ciency. Moreover, a current-balancing circuit with a no current-balancing bus is utilized to render the load current extracted from the two phases as even as possible, so that the system stability is upgraded. In such a study, this converter, having the input of 24V ± 10% and the rated output of 36V / 6A, was employed to demonstrate the e ﬀ ectiveness of such a converter by experiment.


Introduction
As well known, the switching power supply is widely used today. This is because of its small volume, high efficiency, etc. However, it has some disadvantages due to its hard switching, such as high switching loss, large voltage/current stress and strong electromagnetic interference.
To overcome the demerits mentioned above, the quasi-resonant converter (QRC) [1][2][3][4][5][6] has been investigated since 1980, mainly on the condition that the voltage/current waveform is sinusoidal. This converter contains the resonant inductor in a series with the switch or the diode, and hence resonates with the switch parasitic capacitor or the diode parasitic capacitor so that the zero-voltage switching (ZVS) during the turn-on period or the zero-current switching (ZCS) during the turn-off period can be realized. However, this inductor locates on the path of the main power stage such that the high voltage/current on/in the switch or diode will occur and hence the circulation current is unavoidable, thereby creating a large conduction loss. Moreover, the resonant energy comes from the input and the load such that the soft switching can be achieved only for some input voltage range as well as some load range.
To overcome the demerits of QRCs, a resonant network paralleled with the main power stage path was developed. Some derived structures were presented, such as active clamp [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21], zero-voltage transition (ZVT) and zero-current transition (ZCT) [22][23][24][25][26][27][28][29][30][31][32][33]. The last two structures use resonant networks, which will make the main switch have ZVS and ZCS according to the auxiliary switch. Furthermore, the voltage on the switch and the current in the switch are of sinusoidal form. By doing so, the voltage stress and current stress for the switch are effectively alleviated, causing the circulation current to be small and hence the unavoidable conduction loss to be reduced. Moreover, the required resonant energy is not all determined by the input voltage and output load. Accordingly, in design of the resonant parameters for soft switching all over the range of input voltage and output load, only the minimum input voltage and the maximum output load were considered.
On the other hand, to increase the output current as well as to upgrade the corresponding overall efficiency, the multiphase converter along with interleaved control are commonly utilized. Since the AC components of the inductor currents for multiple phases are cancelled with each other to some extent, not only is the output current ripple thereby decreased but also the frequency of the output current ripple is increased. Accordingly, not only will the design of the required filter be easier, but the corresponding size will also be smaller. Generally, the total loss generated from multiple phases will be smaller than that generated from one phase. Furthermore, the soft switching multiphase converter is proposed so that the overall efficiency is further upgraded. The literature [34][35][36][37] takes multiple phases with the accompanying number of auxiliary resonance circuits, thereby resulting in increasing the number of components and hence increasing not only the conduction loss but also the cost. In the literature [36], the two-phase converter utilizes the same auxiliary resonant circuit. However, only the ZVS is employed so that the improvement in efficiency is restricted. In the literature [37], a two-phase converter adopts one snubber circuit to force the main switches to realize soft switching. Nevertheless, the resonant inductor is put on the power path, thus increasing the conduction loss. In addition, since there are differences in component features and line impedance between the two phases, the current-balancing control will be required. Regarding current balance, there are two types of current-balancing control strategies. One method is passive; the other method is active. The former adopts differential-mode transformers or capacitors or both to do current balance [38][39][40][41], while the latter consists of current regulators and sensors to do current balance [42][43][44][45][46].
Accordingly, only one resonant circuit, which is comprised of relatively few elements as compared with [47] is presented and imposed on a two-phase interleaved boost converter to force two main switches to have ZVT turn-on and two auxiliary switches to have ZCS turn-off. Moreover, as the switches operate under soft switching, the output current ripple is not affected such that the life of the capacitor can be prolonged. As for the current balance, a simple method, based on digital control with no current-balancing bus, is proposed to render the load current evenly distributed between the two phases. Figure 1 shows the proposed converter containing a traditional two-phase boost converter with the parasitic diodes D S1 and D S2 and parasitic capacitors C S1 and C S2 for the main switches S 1 and S 2 , respectively, the output didoes D 1 and D 2 , and one output capacitor C o , along with a resonant circuit, which is composed of only one resonant inductor L r , only one resonant capacitor C r , one resonant diode D r , and two auxiliary switches S a and S b with parasitic diodes D Sa and D Sb and parasitic capacitors C Sa and C Sb , respectively. Moreover, the output resistor is indicated by R.

Proposed Converter
Appl. Sci. 2019, 9, x FOR PEER REVIEW 2 of 21 By doing so, the voltage stress and current stress for the switch are effectively alleviated, causing the circulation current to be small and hence the unavoidable conduction loss to be reduced. Moreover, the required resonant energy is not all determined by the input voltage and output load. Accordingly, in design of the resonant parameters for soft switching all over the range of input voltage and output load, only the minimum input voltage and the maximum output load were considered. On the other hand, to increase the output current as well as to upgrade the corresponding overall efficiency, the multiphase converter along with interleaved control are commonly utilized. Since the AC components of the inductor currents for multiple phases are cancelled with each other to some extent, not only is the output current ripple thereby decreased but also the frequency of the output current ripple is increased. Accordingly, not only will the design of the required filter be easier, but the corresponding size will also be smaller. Generally, the total loss generated from multiple phases will be smaller than that generated from one phase. Furthermore, the soft switching multiphase converter is proposed so that the overall efficiency is further upgraded. The literature [34][35][36][37] takes multiple phases with the accompanying number of auxiliary resonance circuits, thereby resulting in increasing the number of components and hence increasing not only the conduction loss but also the cost. In the literature [36], the two-phase converter utilizes the same auxiliary resonant circuit. However, only the ZVS is employed so that the improvement in efficiency is restricted. In the literature [37], a two-phase converter adopts one snubber circuit to force the main switches to realize soft switching. Nevertheless, the resonant inductor is put on the power path, thus increasing the conduction loss. In addition, since there are differences in component features and line impedance between the two phases, the current-balancing control will be required. Regarding current balance, there are two types of current-balancing control strategies. One method is passive; the other method is active. The former adopts differential-mode transformers or capacitors or both to do current balance [38][39][40][41], while the latter consists of current regulators and sensors to do current balance [42][43][44][45][46]. Accordingly, only one resonant circuit, which is comprised of relatively few elements as compared with [47] is presented and imposed on a two-phase interleaved boost converter to force two main switches to have ZVT turn-on and two auxiliary switches to have ZCS turn-off. Moreover, as the switches operate under soft switching, the output current ripple is not affected such that the life of the capacitor can be prolonged. As for the current balance, a simple method, based on digital control with no current-balancing bus, is proposed to render the load current evenly distributed between the two phases. Figure 1 shows the proposed converter containing a traditional two-phase boost converter with the parasitic diodes DS1 and DS2 and parasitic capacitors CS1 and CS2 for the main switches S1 and S2, respectively, the output didoes D1 and D2, and one output capacitor Co, along with a resonant circuit, which is composed of only one resonant inductor Lr, only one resonant capacitor Cr, one resonant diode Dr, and two auxiliary switches Sa and Sb with parasitic diodes DSa and DSb and parasitic capacitors CSa and CSb, respectively. Moreover, the output resistor is indicated by R.

Operation Behavior
Before tackling this section, there are some assumptions and symbols to be given as below: (i) all the elements are viewed as ideal except the parasitic diodes and capacitors for the main switches and auxiliary switches; (ii) the input inductors can be regarded as current sources represented by I L1 and I L2 ; (iii) the output capacitor can be viewed as a voltage source V o ; (iv) this converter operates in the continuous current mode (CCM); (v) the gate-driving signals for the switches S 1 , S 2 , S a and S b are denoted by v g1 , v g2 , v ga and v gb , respectively; (vi) the voltages across the switches S 1 , S 2 , S a and S b are signified by v S1 , v S2 , v Sa and v Sb , respectively; (vii) the currents flowing through the switches S 1 , S 2 , S a and S b are represented by i S1 , i S2 , i Sa and i Sb , respectively; (viii) the currents flowing through D 1 , D 2 and D r are indicated by i D1 , i D2 and i Dr , respectively; (ix) the current flowing through L r and the voltage across C r are denoted by i Lr and v Cr , respectively.
According to the aforementioned assumptions and symbols, the converter in Figure 2 is an equivalent for that in Figure 1. In Figure 3, there are sixteen operation modes in this circuit. Since such a converter is controlled by interleave, namely, the gate-driving signal v g2 shifted by 180 degrees from the gate-driving signal v g1 , the behavior of the first eight operation modes is identical to that of the last eight operation modes. Hence, only the first eight operation modes are illustrated.

Operation Behavior
Before tackling this section, there are some assumptions and symbols to be given as below: (i) all the elements are viewed as ideal except the parasitic diodes and capacitors for the main switches and auxiliary switches; (ii) the input inductors can be regarded as current sources represented by IL1 and IL2; (iii) the output capacitor can be viewed as a voltage source Vo; (iv) this converter operates in the continuous current mode (CCM); (v) the gate-driving signals for the switches S1, S2, Sa and Sb are denoted by vg1, vg2, vga and vgb, respectively; (vi) the voltages across the switches S1, S2, Sa and Sb are signified by vS1, vS2, vSa and vSb, respectively; (vii) the currents flowing through the switches S1, S2, Sa and Sb are represented by iS1, iS2, iSa and iSb, respectively; (viii) the currents flowing through D1, D2 and Dr are indicated by iD1, iD2 and iDr, respectively; (ix) the current flowing through Lr and the voltage across Cr are denoted by iLr and vCr, respectively.
According to the aforementioned assumptions and symbols, the converter in Figure 2 is an equivalent for that in Figure 1. In Figure 3, there are sixteen operation modes in this circuit. Since such a converter is controlled by interleave, namely, the gate-driving signal vg2 shifted by 180 degrees from the gate-driving signal vg1, the behavior of the first eight operation modes is identical to that of the last eight operation modes. Hence, only the first eight operation modes are illustrated.  . As in Figure 4, the auxiliary switch Sa is switched on at the instant t0. Since the output diodes D1 and D2 are also switched on, thereby making the parasitic capacitor of Sb, called Csb, abruptly discharged to zero. Meanwhile, the output voltage Vo was imposed on the resonant inductor Lr and the resonant capacitor Cr, thereby making Lr and Cr resonate. Moreover, the current iSa is equal to iLr and both are increasing, but the current iD1 begins to fall. As soon as iLr is equal to IL1, namely iLr(t1) = IL1, this mode ends. During such a mode, the accompanying equations are described as below: Mode 1: [t 0 ≤ t ≤ t 1 ]. As in Figure 4, the auxiliary switch S a is switched on at the instant t 0 . Since the output diodes D 1 and D 2 are also switched on, thereby making the parasitic capacitor of S b , called Cs b , abruptly discharged to zero. Meanwhile, the output voltage V o was imposed on the resonant inductor L r and the resonant capacitor C r , thereby making L r and C r resonate. Moreover, the current i Sa is equal to i Lr and both are increasing, but the current i D1 begins to fall. As soon as i Lr is equal to I L1 , namely i Lr (t 1 ) = I L1 , this mode ends. During such a mode, the accompanying equations are described as below: where At the instant t 0 , i Lr (t 0 ) is close to zero and v Cr (t 0 ) is much smaller than V o , so the expression of the current i Lr from Equation (1) can be approximately represented by From Equation (3), the elapsed time for this mode can be obtained to be . As in Figure 5, the output diode D1 is switched off. Meanwhile, the current IL2 charges the parasitic capacitor of the auxiliary switch Sb, called CSb, to the output voltage Vo abruptly, while the resonant inductor Lr resonates with the resonant capacitor Cr in series with the parasitic capacitor of the main switch S1, called CS1. Since the current iSa is equal to iLr, the current IL1 is the sum of the currents of iLr and iS1. Therefore, ILr will force CS1 to discharge, thereby causing the voltage across S1, called vS1, to be dropped. As soon as vS1 is zero, this mode ends. During such a mode, the accompanying equations are described as below:  Figure 5, the output diode D 1 is switched off. Meanwhile, the current I L2 charges the parasitic capacitor of the auxiliary switch S b , called C Sb , to the output voltage V o abruptly, while the resonant inductor L r resonates with the resonant capacitor C r in series with the parasitic capacitor of the main switch S 1 , called C S1 . Since the current i Sa is equal to i Lr , the current I L1 is the sum of the currents of i Lr and i S1 . Therefore, I Lr will force C S1 to discharge, thereby causing the voltage across S 1 , called v S1 , to be dropped. As soon as v S1 is zero, this mode ends. During such a mode, the accompanying equations are described as below: Appl. Sci. 2020, 10, 3881 5 of 18 where C = C r C S1 C r +C S1 , ω 2 = 1 L r C = C r +C S1 L r C r C S1 As the voltage v S1 is identical to the voltage v Cr , the resonant current i Lr , which flows through the auxiliary switch S a , will be a maximum value, called I Lr-peak , which can be expressed as Appl. Sci. 2019, 9, x FOR PEER REVIEW 6 of 21 As the voltage vS1 is identical to the voltage vCr, the resonant current iLr, which flows through the auxiliary switch Sa, will be a maximum value, called ILr-peak, which can be expressed as Figure 5. Current path in mode 2.
. As in Figure 6, the voltage across S1, called vS1, is zero due to the parasitic diode of the switch S1, called DS1, conducting the current. Therefore, as S1 is switched on during this mode, S1 has ZVT turn-on without conduction. Since Lr resonates with Cr, the voltage on Lr is identical to the minus voltage across Cr, thereby causing iLr to begin to drop. Moreover, the current IL1 is the sum of the currents of iLr, iS1 and iDr. As soon as iLr drops to IL1, this mode ends. During such a mode, the accompanying equations are described as below: Figure 6. Current path in mode 3. Mode 3: [t 2 ≤ t ≤ t 3 ]. As in Figure 6, the voltage across S 1 , called v S1 , is zero due to the parasitic diode of the switch S 1 , called D S1 , conducting the current. Therefore, as S 1 is switched on during this mode, S 1 has ZVT turn-on without conduction. Since L r resonates with C r , the voltage on L r is identical to the minus voltage across C r , thereby causing i Lr to begin to drop. Moreover, the current I L1 is the sum of the currents of i Lr , i S1 and i Dr . As soon as i Lr drops to I L1 , this mode ends. During such a mode, the accompanying equations are described as below: As the voltage vS1 is identical to the voltage vCr, the resonant current iLr, which flows through the auxiliary switch Sa, will be a maximum value, called ILr-peak, which can be expressed as Figure 5. Current path in mode 2.
. As in Figure 6, the voltage across S1, called vS1, is zero due to the parasitic diode of the switch S1, called DS1, conducting the current. Therefore, as S1 is switched on during this mode, S1 has ZVT turn-on without conduction. Since Lr resonates with Cr, the voltage on Lr is identical to the minus voltage across Cr, thereby causing iLr to begin to drop. Moreover, the current IL1 is the sum of the currents of iLr, iS1 and iDr. As soon as iLr drops to IL1, this mode ends. During such a mode, the accompanying equations are described as below:   Figure 7, the current i Lr is equal to the current I L1 at the instant t 3 , and hence both the currents i S1 and i Dr are zero, thereby causing the diodes D S1 and D r to be switched off. During this mode, the main switch S 1 is switched on with conduction. Meanwhile, the resonant inductor L r still resonates with the resonant capacitor C r , and i Lr is still reduced, but i S1 increases from zero gradually. Moreover, the current I L1 is the sum of the currents i S1 and i Sa , and i Sa is identical to i Lr . As i Lr drops to zero, the auxiliary switch S a is switched off, thereby causing S a to operate under ZCS turn-off. As soon as i Lr is identical to zero, this mode ends.
. As in Figure 7, the current iLr is equal to the current IL1 at the instant t3, and hence both the currents iS1 and iDr are zero, thereby causing the diodes DS1 and Dr to be switched off. During this mode, the main switch S1 is switched on with conduction. Meanwhile, the resonant inductor Lr still resonates with the resonant capacitor Cr, and iLr is still reduced, but iS1 increases from zero gradually. Moreover, the current IL1 is the sum of the currents iS1 and iSa, and iSa is identical to iLr.
As iLr drops to zero, the auxiliary switch Sa is switched off, thereby causing Sa to operate under ZCS turn-off. As soon as iLr is identical to zero, this mode ends.
. As in Figure 8, the main switch S1 remains switched on. During this mode, the resonant inductor Lr still keeps resonating with the resonant capacitor Cr, and the current iLr increases in the negative direction and flows through S1, thereby making the parasitic diode of the auxiliary switch Sa, called DSa, switched on. Moreover, as soon as iLr goes from the minimum value to zero, this mode ends. Figure 8. Current path in mode 5.
. As in Figure 9, the main switch S1 still remains switched on. During this mode, the resonant inductor Lr, with its current in the positive direction, resonates with the resonant capacitor Cr, thereby making the resonant diode Dr switched on and hence a resonant loop is generated. Moreover, the current in the main switch S1, called iS1, is identical to the current IL1. As soon as S1 is switched off, this mode ends. Mode 5: [t 4 ≤ t ≤ t 5 ]. As in Figure 8, the main switch S 1 remains switched on. During this mode, the resonant inductor L r still keeps resonating with the resonant capacitor C r , and the current i Lr increases in the negative direction and flows through S 1 , thereby making the parasitic diode of the auxiliary switch S a , called D Sa , switched on. Moreover, as soon as i Lr goes from the minimum value to zero, this mode ends.
. As in Figure 7, the current iLr is equal to the current IL1 at the instant t3, and hence both the currents iS1 and iDr are zero, thereby causing the diodes DS1 and Dr to be switched off. During this mode, the main switch S1 is switched on with conduction. Meanwhile, the resonant inductor Lr still resonates with the resonant capacitor Cr, and iLr is still reduced, but iS1 increases from zero gradually. Moreover, the current IL1 is the sum of the currents iS1 and iSa, and iSa is identical to iLr.
As iLr drops to zero, the auxiliary switch Sa is switched off, thereby causing Sa to operate under ZCS turn-off. As soon as iLr is identical to zero, this mode ends. . As in Figure 8, the main switch S1 remains switched on. During this mode, the resonant inductor Lr still keeps resonating with the resonant capacitor Cr, and the current iLr increases in the negative direction and flows through S1, thereby making the parasitic diode of the auxiliary switch Sa, called DSa, switched on. Moreover, as soon as iLr goes from the minimum value to zero, this mode ends. . As in Figure 9, the main switch S1 still remains switched on. During this mode, the resonant inductor Lr, with its current in the positive direction, resonates with the resonant capacitor Cr, thereby making the resonant diode Dr switched on and hence a resonant loop is generated. Moreover, the current in the main switch S1, called iS1, is identical to the current IL1. As soon as S1 is switched off, this mode ends. Mode 6: [t 5 ≤ t ≤ t 6 ]. As in Figure 9, the main switch S 1 still remains switched on. During this mode, the resonant inductor L r , with its current in the positive direction, resonates with the resonant capacitor C r , thereby making the resonant diode D r switched on and hence a resonant loop is generated. Moreover, the current in the main switch S 1 , called i S1 , is identical to the current I L1 . As soon as S 1 is switched off, this mode ends.
Mode 7: [t 6 ≤ t ≤ t 7 ]. As in Figure 10, the main switch S 1 is switched off at the instant t 6 . During this mode, the current I L1 charges the parasitic capacitor of the main switch S 1 , called C S1 , and the parasitic capacitor of the auxiliary switch S a , called C Sa , causing the voltage across S 1 to be increased. Moreover, the resonant loop is the same as that displayed in mode 6. As soon as the voltage v S1 is identical to the output voltage V o , this mode ends. . As in Figure 10, the main switch S1 is switched off at the instant t6. During this mode, the current IL1 charges the parasitic capacitor of the main switch S1, called CS1, and the parasitic capacitor of the auxiliary switch Sa, called CSa, causing the voltage across S1 to be increased. Moreover, the resonant loop is the same as that displayed in mode 6. As soon as the voltage vS1 is identical to the output voltage Vo, this mode ends.
. As in Figure 11, during this mode, all the switches are switched off, but only the output diode D1 conducts with the current iD1 identical to the current IL1. Moreover, the resonant loop is the same as that displayed in mode 7. As soon as the main switch Sb is switched on, this mode ends, and hence the other phase begins to work, coming back to state 1 until this cycle is finished. After this, the next period will be repeated.  . As in Figure 10, the main switch S1 is switched off at the instant t6. During this mode, the current IL1 charges the parasitic capacitor of the main switch S1, called CS1, and the parasitic capacitor of the auxiliary switch Sa, called CSa, causing the voltage across S1 to be increased. Moreover, the resonant loop is the same as that displayed in mode 6. As soon as the voltage vS1 is identical to the output voltage Vo, this mode ends.
. As in Figure 11, during this mode, all the switches are switched off, but only the output diode D1 conducts with the current iD1 identical to the current IL1. Moreover, the resonant loop is the same as that displayed in mode 7. As soon as the main switch Sb is switched on, this mode ends, and hence the other phase begins to work, coming back to state 1 until this cycle is finished. After this, the next period will be repeated.  Mode 8: [t 7 ≤ t ≤ t 8 ]. As in Figure 11, during this mode, all the switches are switched off, but only the output diode D 1 conducts with the current i D1 identical to the current I L1 . Moreover, the resonant loop is the same as that displayed in mode 7. As soon as the main switch S b is switched on, this mode ends, and hence the other phase begins to work, coming back to state 1 until this cycle is finished. After this, the next period will be repeated.  i , after ADC3, so that the duty cycle of the gate-driving signal vg2 for the second phase after the second PWM generator is automatically tuned to force the input current to be evenly distributed between the two phases and hence the load current balancing between the two phases can be realized.  Figure 12 displays the proposed current-balancing control strategy. The duty cycle of the gate-driving signal v g1 for the first phase after the first pulse-width modulation (PWM) generator is tuned to get the wanted output voltage V o , based on the voltage loop with the controller G c1 (z) having the voltage command reference V ref and the digital sensed voltage V o , which is obtained from the sensed voltage v o by the voltage divider with a gain k and the first analog-to-digital converter (ADC1). Meanwhile, the sensed current of the first phase, named i L1 , is sent to ADC2, to get the digital sensed current I L1 , which will be used as the current command reference for the current-balancing loop with the controller G c2 (z) having the digital sensed current I L2 from the sensed current of the second phase, named i L2 , after ADC3, so that the duty cycle of the gate-driving signal v g2 for the second phase after the second PWM generator is automatically tuned to force the input current to be evenly distributed between the two phases and hence the load current balancing between the two phases can be realized.

Current Control Strategy
Afterwards, the current-balancing behavior is described below. First, by assuming that the output power (P o ) is identical to the input power (P i ), the output current (I o ) is identical to the product of the DC inductor current (I L ) and one minus duty cycle (1-D). Therefore, if I L = I L1 + I L2 and I o = I o1 + I o2 , then under I L1 = I L2 = 0.5I L , where D a is the duty cycle of v g1 generated from the controller G c1 (z) and D b is the duty cycle of v g2 generated from the controller G c2 (z). For example, if I o1 is larger than I o2 , then D a will be increased and D b will be decreased, thereby causing I o1 to go down and I o2 to go up. Eventually, both I o1 and I o2 are equal to 0.5 I o , making the current balancing realized.  Figure 12. Proposed current-balancing control strategy (ADC: analog-to-digital converter; PWM: pulse-width modulation).

Design Considerations
Prior to designing the key parameters of this converter, the associated specifications of the system are shown in Table 1.

Design of L1 and L2
Since this converter is a two-phase structure, the values of the input inductors can be approximately decided by a single phase with the rated output power/current reduced by a factor of 2. Moreover, the converter operates in the CCM, so the minimum value of L1, called L1, min, can be represented by where R is the output resistor, whose value is located between 12 Ω and 120 Ω. Based on (9), the maximum duty cycle is obtained to be 0.33, which corresponds to the input voltage of 24 V and the output voltage of 36 V. Therefore, L1, min=178 μH after some calculations, and eventually the value of L1 is chosen to be 200 μH, which is also for the value of L2.

Design of Co
Regarding the output capacitor design, Equation (11) is used on condition that the maximum output voltage ripple is equal to 20% of the output voltage Vo, the value of R is 12Ω, Ts is 20 μs, D = 0.33, and Vo = 36 V. After some calculations, the value of Co is larger than 275 μF. Eventually, a 470 μF

Design Considerations
Prior to designing the key parameters of this converter, the associated specifications of the system are shown in Table 1.

Design of L 1 and L 2
Since this converter is a two-phase structure, the values of the input inductors can be approximately decided by a single phase with the rated output power/current reduced by a factor of 2. Moreover, the converter operates in the CCM, so the minimum value of L 1 , called L 1, min , can be represented by where R is the output resistor, whose value is located between 12 Ω and 120 Ω. Based on (9), the maximum duty cycle is obtained to be 0.33, which corresponds to the input voltage of 24 V and the output voltage of 36 V. Therefore, L 1, min = 178 µH after some calculations, and eventually the value of L 1 is chosen to be 200 µH, which is also for the value of L 2 .

Design of C o
Regarding the output capacitor design, Equation (11) is used on condition that the maximum output voltage ripple is equal to 20% of the output voltage V o , the value of R is 12Ω, T s is 20 µs, D = 0.33, and V o = 36 V. After some calculations, the value of C o is larger than 275 µF. Eventually, a 470 µF capacitor is chosen, and this is because the value of the electrolytic capacitor will be decreased if the frequency is increased:

Design of L r and C r
The proposed soft switching structure is based on the turn-on of the auxiliary switch S a/ prior to the turn-on of the main switch S 1 , so that the resonant inductor L r resonates with the resonant capacitor C r and the parasitic capacitor of S 1 , called C S1 . As the current i Lr is larger than the current I L1 , the voltage across S 1 , called v S1 , drops to zero abruptly, the parasitic diode of S 1 , called D S1 , is switched on, and afterwards S 1 is switched on with ZVT. To avoid the converter operating abnormally, the time interval, used to execute resonance, is not too long. Therefore, the turn-on time interval of the auxiliary switch S a is chosen to be one tenth of the switching period T s , about 2 µs. Meanwhile, to reduce the effect of i Lr on S 1 , the turn-on instant of S a is prior to the turn-on instant of S 1 by one fifth of the turn-on time interval of S a , namely 0.4 µs. Hence, to obtain the soft switching of S 1 , the time interval for v S1 to drop to zero is chosen to be 0.5 µs or less as shown in (11): where during the time interval between t 1 and t 0 , the resonant current i Lr rises from zero to the current I L1 , whereas during the time interval between t 2 and t 1 , the voltage across S 1 drops from the output voltage V o to zero. In Equation (11), the former time interval was quite significantly larger than the latter time interval, so the former time interval at a rated load is set at half of the time interval between the turn-on instant of S a and the turn-on instant of S 1 , namely 0.2 µs, so as to make sure that S 1 can operate under ZVT turn-on within the time interval of 0.5 µs. Therefore, the following equation can be obtained to be: To make sure that the resonant period of the auxiliary circuit, called T 1 , can make the ZVS turn-on of the main switches S 1 and S 2 happen within the switching period T s , T 1 is set at 0.75 T s , equal to 7.5 µs, and afterwards, based on (12), the values of L r and C r can be determined to be 1.25 µH and 1.14 µF.

Experimental Results
To verify the performance of the proposed soft switching control strategy, the waveforms of the converter operating at minimum and rated loads are given. Figures 13-23 are for the converter operating at a minimum load, whereas Figures 24-34 are for the converter operating at a rated load. Figure 13 displays v g1 and v g2 for S 1 and S 2 , respectively. Figure 14 displays v g1 and v ga for S 1 and S a , respectively, whereas Figure 15 shows v g2 and v gb for S 2 and S b , respectively. Figure 16 displays i Lr and v Cr . Figure 17 shows v S1 , i L1 and i Lr . Figure 18 displays v S2 , i L2 and i Lr . Figure 19 shows v g1 , v S1 and i S1 . Figure 20 displays v g2 , v S2 and i S2 . Figure 21 displays v ga , v Sa and i Sa . Figure 22 displays v gb , v Sb and i Sb . Figure 23 shows the current balancing between the two phases. As for Figures 24-34, the measured items are the same as those for Figures 13-23. 26, we can see that Sb is switched on before S2 is switched on. In Figure 16 and Figure 27, we can see that Lr resonates with Cr. From Figure 17 and Figure 28, we can see that as Sa is switched on prior to S1, iLr is rising abruptly and then is larger than iL1, causing the voltage across CS1 to be dropped to zero and then S1 to be switched on with ZVT, whereas from Figure 18 and Figure 29, we can see that as Sb is switched on prior to S2, iLr is rising abruptly and then is larger than iL2, causing the voltage across CS2 to be dropped to zero and then S2 to be switched on with ZVT. From Figures 19 and 30, we can see that S1 has ZVT turn-on, whereas from Figure 20 and Figure 31, we can see that S2 has ZVT turnon. From Figure 21 and Figure 32, we can see that due to resonance, iSa is dropped to zero and then clamped at zero, thereby making Sa switched off with ZCS, whereas from Figure 22 and Figure 33, we can see that due to resonance, iSb is dropped to zero and then clamped at zero, thereby making Sb switched off with ZCS. From Figure 23 and Figure 34, we can see that the current balancing between the two phases performs well for any load.
From Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure  21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35, we can know that all over the load range, both the main switches have ZVT turn-on and both the auxiliary switches have ZCS turn-off.  Figure 13. Waveforms pertaining to S1 and Sa at the minimum load: (1) vg1; and (2) vg2.  26, we can see that Sb is switched on before S2 is switched on. In Figure 16 and Figure 27, we can see that Lr resonates with Cr. From Figure 17 and Figure 28, we can see that as Sa is switched on prior to S1, iLr is rising abruptly and then is larger than iL1, causing the voltage across CS1 to be dropped to zero and then S1 to be switched on with ZVT, whereas from Figure 18 and Figure 29, we can see that as Sb is switched on prior to S2, iLr is rising abruptly and then is larger than iL2, causing the voltage across CS2 to be dropped to zero and then S2 to be switched on with ZVT. From Figures 19 and 30, we can see that S1 has ZVT turn-on, whereas from Figure 20 and Figure 31, we can see that S2 has ZVT turnon. From Figure 21 and Figure 32, we can see that due to resonance, iSa is dropped to zero and then clamped at zero, thereby making Sa switched off with ZCS, whereas from Figure 22 and Figure 33, we can see that due to resonance, iSb is dropped to zero and then clamped at zero, thereby making Sb switched off with ZCS. From Figure 23 and Figure 34, we can see that the current balancing between the two phases performs well for any load.
From Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure  21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35, we can know that all over the load range, both the main switches have ZVT turn-on and both the auxiliary switches have ZCS turn-off.  Figure 13. Waveforms pertaining to S1 and Sa at the minimum load: (1) vg1; and (2) vg2.   Figure 19. Waveforms pertaining to S1 at the minimum load: (1) vg1; (2) vS1; and (3) iS1.   Figure 19. Waveforms pertaining to S1 at the minimum load: (1) vg1; (2) vS1; and (3) iS1.  Figure 19. Waveforms pertaining to S1 at the minimum load: (1) vg1; (2) vS1; and (3) iS1.  Figure 19. Waveforms pertaining to S1 at the minimum load: (1) vg1; (2) vS1; and (3) iS1. From Figures 13-24, we can see that v g2 is shifted from v g1 by 180 degrees. From Figures 14  and 25, S a is switched on before S 1 is switched on, whereas from Figures 15 and 26, we can see that S b is switched on before S 2 is switched on. In Figures 16 and 27, we can see that L r resonates with C r . From Figures 17 and 28, we can see that as S a is switched on prior to S 1 , i Lr is rising abruptly and then is larger than i L1 , causing the voltage across C S1 to be dropped to zero and then S 1 to be switched on with ZVT, whereas from Figures 18 and 29, we can see that as S b is switched on prior to S 2 , i Lr is rising abruptly and then is larger than i L2 , causing the voltage across C S2 to be dropped to zero and then S 2 to be switched on with ZVT. From Figures 19 and 30, we can see that S 1 has ZVT turn-on, whereas from Figures 20 and 31, we can see that S 2 has ZVT turn-on. From Figures 21 and 32, we can see that due to resonance, i Sa is dropped to zero and then clamped at zero, thereby making S a switched off with ZCS, whereas from Figures 22 and 33, we can see that due to resonance, i Sb is dropped to zero and then clamped at zero, thereby making S b switched off with ZCS. From Figures 23 and 34, we can see that the current balancing between the two phases performs well for any load.  Figure 19. Waveforms pertaining to S1 at the minimum load: (1) vg1; (2) vS1; and (3) iS1.   Figure 19. Waveforms pertaining to S1 at the minimum load: (1) vg1; (2) vS1; and (3) iS1.   Figure 24. Waveforms pertaining to S1 and Sa at the rated load: (1) vg1; and (2) vg2. and (4) iL2. Figure 24. Waveforms pertaining to S1 and Sa at the rated load: (1) vg1; and (2) vg2.  and (4) iL2. Figure 24. Waveforms pertaining to S1 and Sa at the rated load: (1) vg1; and (2) vg2.

Comparisons
In Table 2, the numbers of resonant components are five, seven and five for the circuits from [37] and [47], and the proposed circuits, respectively. The circuit shown in [37] has ZCT turn-on and ZVT turn-off. The circuit displayed in [47] has ZVT turn-on and ZCT turn-off. The proposed circuit has ZVT turn-on. The minimum values of the overall efficiency are 84%, 91% and 94% for the circuits [37] and [47], and the proposed, respectively. The circuit [47] has ZVT turn-on and ZCT turn-off but the number of resonant components is seven, whereas the proposed circuit only has ZVT turn-on, but

Comparisons
In Table 2, the numbers of resonant components are five, seven and five for the circuits from [37] and [47], and the proposed circuits, respectively. The circuit shown in [37] has ZCT turn-on and ZVT turn-off. The circuit displayed in [47] has ZVT turn-on and ZCT turn-off. The proposed circuit has ZVT turn-on. The minimum values of the overall efficiency are 84%, 91% and 94% for the circuits [37] and [47], and the proposed, respectively. The circuit [47] has ZVT turn-on and ZCT turn-off but the number of resonant components is seven, whereas the proposed circuit only has ZVT turn-on, but the number of resonant components is five. In general, the ZVS turn-on or ZVT turn-on is quite important for reducing the switching loss of the metal-oxide-semiconductor field-effect transistor (MOSFET) [48]. Accordingly, the proposed circuit has the best performance among the three.

Comparisons
In Table 2, the numbers of resonant components are five, seven and five for the circuits from [37] and [47], and the proposed circuits, respectively. The circuit shown in [37] has ZCT turn-on and ZVT turn-off. The circuit displayed in [47] has ZVT turn-on and ZCT turn-off. The proposed circuit has ZVT turn-on. The minimum values of the overall efficiency are 84%, 91% and 94% for the circuits [37] and [47], and the proposed, respectively. The circuit [47] has ZVT turn-on and ZCT turn-off but the number of resonant components is seven, whereas the proposed circuit only has ZVT turn-on, but the number of resonant components is five. In general, the ZVS turn-on or ZVT turn-on is quite important for reducing the switching loss of the metal-oxide-semiconductor field-effect transistor (MOSFET) [48]. Accordingly, the proposed circuit has the best performance among the three. Table 2. Comparisons between the circuits from [37], [47] and the proposed circuits (ZVS: zero-voltage switching; ZVT: zero-voltage transition; ZCS: zero-current switching; ZCT: zero-current transition). The sign * means that the converter possesses this soft switching type.

Conclusions
In this paper, to reduce the switching loss as well as to upgrade the overall efficiency, the proposed converter with the main switches S 1 and S 2 had ZVT turn-on as well as the auxiliary switches S a and S b having ZCS turn-off. All the soft switching operations are achieved based on only one resonant loop. The ZVT behavior is realized by switching on the auxiliary switch S a (or S b ) before the main switch S 1 (or S 2 ) is switched on, so that the voltage across S 1 (or S 2 ) is dropped to zero and hence S 1 (or S 2 ) has an ZVT turn-on. On the other hand, the ZCS behavior was achieved based on the characteristics of the auxiliary circuit, so that S a and S b have a ZCS turn-off. From the experimental results, we can know that soft switching can be realized all over the load range. In addition, the current balancing between the two phases is performed well for any load.