Rigorous Study on Hump Phenomena in Surrounding Channel Nanowire (SCNW) Tunnel Field-E ﬀ ect Transistor (TFET)

: In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel ﬁeld-e ﬀ ect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on -current ( I ON ). In spite of the high electrical performance, the SCNW TFET su ﬀ ers from hump e ﬀ ect which deteriorates subthreshold swing ( S ). In order to solve the issue, an origin of hump e ﬀ ect is analyzed ﬁrstly. Based on the simulation, the transfer curve in SCNW TFET is decoupled into vertical- and lateral-BTBTs. In addition, the lateral-BTBT causes the hump e ﬀ ect due to low turn- on voltage ( V ON ) and low I ON . Therefore, the device design parameter is optimized to suppress the hump e ﬀ ect by adjusting thickness of the ultra-thin tunnel layer. Finally, we compared the electrical properties of the planar, nanowire and SCNW TFET. As a result, the optimized SCNW TFET shows better electrical performance compared with other TFETs.


Introduction
A reduction of power density in complementary metal-oxide-semiconductor (CMOS) technology becomes one of the major concerns as the CMOS devices have been scaled down [1], [2]. A tunnel FET (TFET) has been attracted as a substitutable device for an ultra-low power logic circuit since it can achieve subthreshold swing (S) less than 60 mV/decade at room temperature which allows TFET to be operated with the lower supply voltage (<0.5 V) maintaining a high on-off current ratio (I ON /I OFF ) [3][4][5][6]. However, experimental results have demonstrated that the TFET suffers from some critical issues such as low-level I ON , ambipolar current and poor S [7,8]. There are several studies to address them with the help of narrow band gap materials [9][10][11], abrupt doping profile [12] and novel geometrical structures [13][14][15]. Among these studies, many papers propose a TFET with an ultra-thin tunnel layer at source sidewall which enables band-to-band tunneling (BTBT) perpendicular to the channel direction (vertical-BTBT) [16][17][18][19][20][21][22][23]. It can improve I ON as well as S with the help of a large BTBT junction area and a short tunnel barrier width. However, it only considers a vertical-BTBT and ignores the other BTBT component including a BTBT parallel to the channel direction (lateral-BTBT), [24,25]. Since BTBT at sharp source corner is deeply related to the hump effect which degrades average S and I ON , it should be examined rigorously for a device design optimization [26]. Therefore, more precise analysis are required considering both vertical-and lateral-BTBTs in technology computer-aided design (TCAD) simulation [27][28][29][30].
This paper is composed as follow. First of all, device design parameters and TCAD simulation conditions for a gate-all-around (GAA)-NW TFET with an ultra-thin tunnel layer at source sidewall are explained. Second, after examining the basic operation of studied TFET, a fundamental origin of hump effect is analyzed by two-dimensional (2D) contour plots. Third, the influences of geometrical parameters on hump effect are investigated and analyzed to minimize undesired effect which degrades switching performance. Last of all, the optimized structure is compared with the control devices.

Device Fabrication
The device structure used in this work is similar to that in [16], except a lateral channel direction considering the compatibility with the state-of-the-art CMOS technology for a sub-5 nm-technology nodes [31] (Figure 1). It is named as a surrounding channel nanowire (SCNW) TFET, since its intrinsic (or lightly doped) channel which is named as tunnel region surrounds conventional nanowire structure. All the materials except for gate oxide are Si. The gate oxide is SiO 2 . In TCAD simulation, a channel length (L CH ) is set by 30 nm to exclude short-channel effect. Considering the latest CMOS technology, a nanowire radius except surrounding channel (i.e., tunnel region) (T B ) and a gate oxide thickness (T OX ) are set by 7 nm and 1 nm, respectively. The other important design parameters are summarized in Figure 1 and Table 1. All the parameter variations in this simulation are set in consideration of the fabrication processes [32,33]. The following models are used for an accurate simulation result: Shockey-Read-Hall recombination, doping and field dependent mobility, and dynamic non-local BTBT after calibration by referring [17]. Since the thickness of tunnel region (T TUN ) is less than 8 nm, modified local density approximation is also used to consider quantum effect. In addition, the physical characteristics for BTBT is reflected by the calibrated current model based on the fabricated device [34][35][36][37]. For the calculation of BTBT generation rate (G) per unit volume in uniform electric field, Kane's model is use as follows: where F0 = 1 V/m, P = 2.5 for indirect BTBT, A = 4.0 × 1014 cm −1 ·s −1 , and B = 1.9 × 107 V·cm −1 are the Kane's model parameters and F is the electric field [34]. The pre-factor A and the exponential factor B parameter are calibrated by referring [17].
Appl. Sci. 2020, 10, x FOR PEER REVIEW 2 of 9 ignores the other BTBT component including a BTBT parallel to the channel direction (lateral-BTBT), [24,25]. Since BTBT at sharp source corner is deeply related to the hump effect which degrades average S and ION, it should be examined rigorously for a device design optimization [26]. Therefore, more precise analysis are required considering both vertical-and lateral-BTBTs in technology computer-aided design (TCAD) simulation [27][28][29][30]. This paper is composed as follow. First of all, device design parameters and TCAD simulation conditions for a gate-all-around (GAA)-NW TFET with an ultra-thin tunnel layer at source sidewall are explained. Second, after examining the basic operation of studied TFET, a fundamental origin of hump effect is analyzed by two-dimensional (2D) contour plots. Third, the influences of geometrical parameters on hump effect are investigated and analyzed to minimize undesired effect which degrades switching performance. Last of all, the optimized structure is compared with the control devices.

Device Fabrication
The device structure used in this work is similar to that in [16], except a lateral channel direction considering the compatibility with the state-of-the-art CMOS technology for a sub-5 nm-technology nodes [31] (Figure 1). It is named as a surrounding channel nanowire (SCNW) TFET, since its intrinsic (or lightly doped) channel which is named as tunnel region surrounds conventional nanowire structure. All the materials except for gate oxide are Si. The gate oxide is SiO2. In TCAD simulation,   The I ON increases linearly proportional to the L TUN which confirms that the BTBT junction area of SCNW TFET is determined by the L TUN . Generally, the FETs based on a NW channel have a disadvantage for enhancing current drivability, which can be achieved by increasing a NW radius or using a multi-channel structure [38]. On the other hand, SCNW TFET can easily adjust I ON by controlling a L TUN . However, as shown in Figure 3a, there is a hump in the subthreshold region of SCNW TFET. The transfer curves are simulated with various V DS values. At all the V DS values, the hump current appears. In addition to this, with the higher the doping concentration, the better the ON-current is shown however, the hump effect is noticeable from 5×10 19 -N S cm -3 as shown in Figure 3b. The hump effect should be addressed for TFET's low-power application since it deteriorates average S which results in the degradation of I ON /I OFF and/or supply power (V DD )-scaling. Therefore, optimization for other parameters is needed to achieve high ON-current and hump-less transfer curve. In order to analyze the cause of hump effect, the electron BTBT generation rates (e BTBT ) are examined by 2D contour plots with different V GS conditions ( Figure 4). When V GS is applied near a turn-ON voltage (V ON ), defined as V GS when BTBT starts to occur, a lateral-BTBT is predominant. As V GS increases, a vertical-BTBT starts to occur at 0.4 V-V GS and finally surpasses the lateral-BTBT at 1.2 V-V GS . Therefore, the current of SCNW TFET can be decoupled into two different BTBTs. In addition, transfer curves with various L TUN are plotted in Figure 5. The I D at low V GS (< 0.9 V) is unchanged regardless of L TUN , while I D increases with longer L TUN at high V GS (> 0.9 V). The V GS at this point is defined as hump voltage (V HUMP ). Since the tunnel junction area of vertical-BTBT component is only affected by L TUN .

Device Optimization
In Section 3, we confirmed that the hump behavior in SCNW TFET is mainly attributed to the two BTBT paths (i.e., vertical and lateral) which have different V ON and BTBT rates. Therefore, a design optimization is needed to achieve maximum electrical performance (low S and high I ON ). In this Section, the influences of L TUN and T TUN on SCNW TFET's electrical characteristic are investigated since the vertical-BTBT mostly occurs in the tunnel region. Figure 6a shows transfer curves with 50, 80, 100 nm of L TUN and 2, 3, 4, 5 nm of T TUN . As shown in the inset of Figure 6a, the V HUMP is clearly decreased as T TUN increases. The results can be quantitatively analyzed and calculated by voltage division model in which the gate oxide and depletion capacitors (C ox and C Si ) are connected in series (Figure 6b) [13]. Since T TUN is ultra-thin (< 10 nm) and source is highly doped, it can be assumed that the tunnel region is entirely depleted; the C Si is constant. Therefore, surface potential (ψ S ) is expressed as (2), where ε Si and ε ox are permittivity of Si and SiO 2 , respectively. If T TUN increases, ψ S becomes large and vertical-BTBT occurs with the smaller V GS which results in the decrease of V HUMP as discussed in Figure 6a. Figure 7 shows transfer curves with various T TUN from 2 to 8 nm, where L TUN and V DS are fixed at 20 nm and 0.5 V, respectively. According to the results, the I D is clearly increased, and S is deteriorated as T TUN becomes thinner. It is attributed to the enhanced vertical-BTBT rate with the smaller T TUN , because the tunnel resistance (i.e., tunnel barrier width) of SCNW TFET is geometrically determined by the T TUN [39]. However, an aggressive scaling-down of T TUN is contradictory to the process capability and the S which gets worse as the T TUN decreases due to an increased V HUMP . Consequently, an optimization of T TUN can be a strategy for SCNW TFET to compensate its weakness (i.e., low I ON and hump effect) and/or enhance its strength (i.e., under 60 mV/dec-S at room temperature). Finally, T TUN is optimized as 4 nm. Then, the performances of planar TFET, SCNW TFETs and nanowire TFET are compared. Figure 8a shows the average subthreshold swing (S avg ) and point-to-point minimum subthreshold swing (S min ) of SCNW, nanowire and planar TFETs. The S avg is defined as the average inverse slope of the transfer curve while I D changes from 10 −12 µA/ µm to 10 −2 µA/ µm. For S min , the planar TFET, SCNW TFETs and nanowire TFET show similar values, all of which are less than 60 mV/dec. For S avg , SCNW TFET shows the lowest value. Figure 8b shows transfer curve of planar TFET, SCNW TFETs and nanowire TFET. For fair comparison, the I OFF of these devices should be adjusted to the same level. The above adjustment is achieved by changing the work function and channel doping concentration. The adjusted I OFF is 10 −7 µA/µm, referring to actual I OFF in nanowire TFET [40]. The Figure 8b shows that the SCNW TFET has a larger I ON than that of the planar and nanowire TFETs. In detail, its I ON is enhanced 2.4 times more than that of nanowire TFET and 4.7 times more than that of planar TFET. In addition, the SCNW TFET shows higher I ON than other devices at 0.53 V-V GS and fully operates within 0.7 V-V GS .  (2) Figure 7 shows transfer curves with various TTUN from 2 to 8 nm, where LTUN and VDS are fixed at 20 nm and 0.5 V, respectively. According to the results, the ID is clearly increased, and S is deteriorated as TTUN becomes thinner. It is attributed to the enhanced vertical-BTBT rate with the smaller TTUN, because the tunnel resistance (i.e., tunnel barrier width) of SCNW TFET is geometrically determined by the TTUN [39]. However, an aggressive scaling-down of TTUN is contradictory to the process capability and the S which gets worse as the TTUN decreases due to an increased VHUMP. Consequently, an optimization of TTUN can be a strategy for SCNW TFET to compensate its weakness (i.e., low ION and hump effect) and/or enhance its strength (i.e., under 60 mV/dec-S at room temperature). Finally, TTUN is optimized as 4 nm. Then, the performances of planar TFET, SCNW TFETs and nanowire TFET are compared. Figure 8(a) shows the average subthreshold swing (Savg) and point-to-point minimum subthreshold swing (Smin) of SCNW, nanowire and planar TFETs. The Savg is defined as the average inverse slope of the transfer curve while ID changes from 10 -12 μA/ μm to 10 -2 μA/ μm. For Smin, the planar TFET, SCNW TFETs and nanowire TFET show similar values, all of which are less than 60 mV/dec. For Savg, SCNW TFET shows the lowest value. Figure 8(b) shows transfer curve of planar TFET, SCNW TFETs and nanowire TFET. For fair comparison, the IOFF of these devices should be adjusted to the same level. The above adjustment is achieved by changing the work function and channel doping concentration. The adjusted IOFF is 10 -7 μA/μm, referring to actual IOFF in nanowire TFET [40]. The Figure 8(b) shows that the SCNW TFET has a larger ION than that of the planar and nanowire TFETs. In detail, its ION is enhanced 2.4 times more than that of nanowire TFET and 4.7 times more than that of planar TFET. In addition, the SCNW TFET shows higher ION than other devices at 0.53 V-VGS and fully operates within 0.7 V-VGS.

173
The SCNW TFET has been studied for high electrical performance. It features nanowire TFET 174 with a thin tunnel layer at source region. Based on the simulation, the transfer curve in SCNW TFET is analyzed and decoupled into vertical-and lateral-BTBTs. The vertical-BTBT is attributed to

Conclusions
The SCNW TFET has been studied for high electrical performance. It features nanowire TFET with a thin tunnel layer at source region. Based on the simulation, the transfer curve in SCNW TFET is analyzed and decoupled into vertical-and lateral-BTBTs. The vertical-BTBT is attributed to excellent I ON rate and S. However, the lateral-BTBT causes the hump effect due to low V ON and low I ON . Therefore, the design optimization is suggested to reduce the hump effect and achieve maximum electrical performance (low S and high I ON ). Finally, the electrical performance without hump effect is optimized by adjusting the thin tunnel layer. In future work, novel design strategy to reduce lateral-BTBT will be suggested to eliminate the hump effect.