Grid Harmonics Suppression for Three Phase Dual-Frequency Grid-Connected Inverter Based on Feedforward Compensation

: Using a low pulse ratio, the electromagnetic interference and switching loss of an inverter can be effectively reduced, particularly in high-power applications. However, due to variations in grid impedance


Introduction
In recent years, photovoltaics has become one of the most promising energy sources due to its ease of installation, environmental friendliness and low maintenance costs [1][2][3][4]. As a result, solar photovoltaic power generation systems have attracted a lot of attention. As an interface between generation systems and the grid, the grid-connected inverter (GCI) can inject high quality power into the grid.
To improve the quality of grid current, the inverter is connected to the grid through various filters, such as L, LC and LCL filters [5]. The L filter has the simplest structure and high reliability but only −20 dB/dec attenuation. As a result, using an L filter, a high switching frequency is needed by the inverter, or the inductance must have a large value to comply with grid standards such as IEEE929-2000 and IEEE 519 [6,7]. It is not helpful for improving system efficiency and power density [8,9]. The LC filter is used to increase the harmonic attenuation which has −40 dB/dec attenuation rate, but it is not usually used in GCIs, because the resonance frequency varies with the change in the grid inductance. Compared with the previous two, the LCL filter is advantageous with a harmonic attenuation rate of −60 dB/dec [10]. Therefore, the LCL filter is an attractive solution in practical applications.
In [11], an algorithm for LCL filter design was implemented by analyzing the interrelationships between parameters. Nevertheless, various constraints must be considered to calculate the range of each parameter, such as the reactive power, grid-connected current harmonics, and inductor current ripple [12][13][14]. Inevitably, the design of the three-order LCL filter is extremely complex. It is worth noting that, even if the LCL filter is designed with various constraints, there are stability problems in the GCI due to the inherent resonance phenomenon of the LCL filter [15][16][17]. Generally, active damping solutions are used to suppress the resonance of the LCL filter, which only change the control loops without damping resistance. In [18], a filter-based damping method was proposed to prevent the resonance without additional sensors. Nevertheless, the variation in LCL filter resonance frequency had a significant influence on the stability. To increase the robustness, an additional state variable could be fed back. However, the digital control delay is generated by algorithm execution, which affects the characteristics of the virtual resistor. In addition, for high-power voltage source inverters (VSIs) with a low switching frequency, the ratio of switching to fundamental frequency is generally small [19,20]. To improve stability, the crossover frequency of the filters was supposed to be much lower than the switching harmonics, but higher than the current control bandwidth [14,[21][22][23]. It brings great challenges for the design of LCL filters [24].
To solve the above-mentioned problems, a novel single-phase inverter was proposed in [25][26][27], which included two converters operating at different switching frequencies.
One converter operated at low pulse ratio to inject current into the grid, while the other converter eliminated the grid current ripple with a high pulse ratio, using the feedforward compensation method. Thus, compared to the LCL inverter, the proposed inverter was highly robust concerning changes in grid impedance and grid voltage harmonics without the need for high current sampling accuracy. Furthermore, the power loss generated by the converter operating at a low switching frequency was significantly reduced. Accordingly, the efficiency of the inverter near the rated power was improved. However, the above research was aimed at single-phase GCI. Since three-phase systems have lower current per phase and lower hardware requirements than single-phase systems at the same power level, in high-power applications, three-phase GCIs are more appropriate. It is expected that the idea of the dual-frequency inverter is more suitable for the application of a three-phase inverter due to its lower switching losses.
In this paper, the topology of the three-phase GCI is proposed, the harmonic elimination principle is analyzed, and the control scheme based on feedforward compensation is proposed. In addition, the inverter parameter design method is proposed, including the inductance of the power inverter unit (PIU), the dc-link voltage of the auxiliary harmonic elimination unit (AHEU) and the inductance of the AHEU. The main contributions of this paper are given as follows: 1.
The feedforward compensation method is used to control the AHEU to generate the output current which is symmetric with the current ripple of the PIU. Compared with an active power filter, it avoids extracting harmonics as current reference, which reduces the requirements for sampling accuracy and current control bandwidth.

2.
A parameter design method for switching frequency and filter inductance is proposed considering system efficiency, and the influence of switching frequency and inductance changes on power loss is discussed. The experimental results verify that the proposed inverter has a significant improvement in efficiency.

3.
A three-phase dual-frequency GCI topology is presented which consists of PIU and AHEU. The PIU operates at a low pulse ratio to reduce the switching loss, and electric energy is transmitted to the power grid by PIU. The AHEU operates at high switching frequency to improve power quality. Furthermore, the stability of the system under a weak grid is analyzed; the proposed inverter can address the stability issue of the LCL filter in low pulse-ratio VSIs with high power in weak grid. The remainder of the paper is organized as follows. The topology and harmonic elimination principle is introduced in Section 2. In Section 3, a detailed introduction is given to the design method of the proposed inverter parameters. In Section 4, the analysis of stability under weak grid conditions is presented. In Section 5, the control scheme of the PIU and AHEU is presented, based on feedforward compensation. Section 6 presents the experiment and simulation results and verifies the effectiveness of the theory and prototype. In the final section, the conclusion is given.

Proposed Topology
As shown in Figure 1, the main circuit topology of the proposed inverter is presented, which consists of a PIU and an AHEU. Here, V dc1 and V dc2 are the dc-links of the PIU and AHEU, v gn is the grid voltage of phase n, n = a, b, c. The filters of PIU and AHEU are L Pn and L An , respectively. To reduce the switching loss and improve the inverter efficiency, the switching frequency of the PIU is relatively low, injecting current into the grid. The AHEU generates the output current which is symmetric with the current ripple of the PIU. In addition, it operates at high switching frequency; hence, its current ripple is very low. As shown in Figure 1, the grid current is the sum of the AHEU current i An and the PIU current i Pn in each phase. So, the grid current does not include the current ripple generated by the PIU current, which guarantees the quality of the grid current. a weak grid is analyzed; the proposed inverter can address the stability issue of the LCL filter in low pulse-ratio VSIs with high power in weak grid.
The remainder of the paper is organized as follows. The topology and harmonic elimination principle is introduced in Section 2. In Section 3, a detailed introduction is given to the design method of the proposed inverter parameters. In Section 4, the analysis of stability under weak grid conditions is presented. In Section 5, the control scheme of the PIU and AHEU is presented, based on feedforward compensation. Sections 6 presents the experiment and simulation results and verifies the effectiveness of the theory and prototype. In the final section, the conclusion is given.

Proposed Topology
As shown in Figure 1, the main circuit topology of the proposed inverter is presented, which consists of a PIU and an AHEU. Here, Vdc1 and Vdc2 are the dc-links of the PIU and AHEU, vgn is the grid voltage of phase n, n = a, b, c. The filters of PIU and AHEU are LPn and LAn, respectively. To reduce the switching loss and improve the inverter efficiency, the switching frequency of the PIU is relatively low, injecting current into the grid. The AHEU generates the output current which is symmetric with the current ripple of the PIU. In addition, it operates at high switching frequency; hence, its current ripple is very low. As shown in Figure 1, the grid current is the sum of the AHEU current iAn and the PIU current iPn in each phase. So, the grid current does not include the current ripple generated by the PIU current, which guarantees the quality of the grid current. Since the operating current of the AHEU is relatively low, the cost of switching elements and inductors is much lower than that of the PIU. Moreover, the proposed inverter does not primarily rely on filters to suppress ripple, indicating the total inductance can be reduced. Although the output voltage of the power inverter unit is used in the control Since the operating current of the AHEU is relatively low, the cost of switching elements and inductors is much lower than that of the PIU. Moreover, the proposed inverter does not primarily rely on filters to suppress ripple, indicating the total inductance can be reduced. Although the output voltage of the power inverter unit is used in the control loop of the AHEU, it can be estimated by drive signals without an additional voltage sampling circuit. The topology of the proposed inverter is similar to an active power filter [28]; thus, there has not been a significant increase in hardware costs, compared with existing solutions. In addition, for the proposed inverter, extracting harmonics as current reference is avoided, which reduces the requirements for sampling accuracy. Therefore, although more devices are used in the proposed inverter, the cost will not significantly increase.
If the common dc-link is shared by the PIU and the AHEU, the circulating current is generated due to the differences in the two units of the switching frequency and other parameters [29]. The circulating current can increase power loss, distort the harmonics of the output current and reduce the useful life of inverters [30,31]. According to [30], circulating current problems are more severe in space-vector modulation-controlled inverters. However, the circulating current is blocked with an isolated dc-link for the proposed inverter, so there is no circulating current with the traditional space-vector modulation. In order to maintain the dc-link voltage of the AHEU V dc2 , the voltage loop is used in the control strategy.
L filters are used in the proposed inverter, as shown in Figure 1. Compared with an LCL filter, there is no inherent filter resonance for an L filter. As a result, the system stability is greatly enhanced. Additionally, the system parameter design and the current control strategy can be simplified significantly.

Proposed Inverter's Principle of Harmonic Elimination
In Figure 2, for the proposed inverter, neglecting the series resistances, the voltages u P and u A can be expressed as where u P = u Pa u Pb u Pc T and u A = u Aa u Ab u Ac T are the output voltages of PIU and AHEU, u PL = u PLa u PLb u PLc T and u AL = u ALa u ALb u ALc T are the voltages across the L P and L A , v g = v ga v gb v gc T are the grid voltages. The grid currents can be expressed as where i g = i ga i gb i gc T , i P = i Pa i Pb i Pc T and i A = i Aa i Ab i Ac T are the output currents of inverter in PIU and AHEU, respectively.
loop of the AHEU, it can be estimated by drive signals without an additional voltage sampling circuit. The topology of the proposed inverter is similar to an active power filter [28]; thus, there has not been a significant increase in hardware costs, compared with existing solutions. In addition, for the proposed inverter, extracting harmonics as current reference is avoided, which reduces the requirements for sampling accuracy. Therefore, although more devices are used in the proposed inverter, the cost will not significantly increase. If the common dc-link is shared by the PIU and the AHEU, the circulating current is generated due to the differences in the two units of the switching frequency and other parameters [29]. The circulating current can increase power loss, distort the harmonics of the output current and reduce the useful life of inverters [30,31]. According to [30], circulating current problems are more severe in space-vector modulation-controlled inverters. However, the circulating current is blocked with an isolated dc-link for the proposed inverter, so there is no circulating current with the traditional space-vector modulation. In order to maintain the dc-link voltage of the AHEU Vdc2, the voltage loop is used in the control strategy.
L filters are used in the proposed inverter, as shown in Figure 1. Compared with an LCL filter, there is no inherent filter resonance for an L filter. As a result, the system stability is greatly enhanced. Additionally, the system parameter design and the current control strategy can be simplified significantly.

Proposed Inverter's Principle of Harmonic Elimination
In Figure 2, for the proposed inverter, neglecting the series resistances, the voltages uP and uA can be expressed as are the grid voltages. The grid currents can be expressed as are the output currents of inverter in PIU and AHEU, respectively. Since the PIU operates at a low pulse ratio, the output currents i P contain obvious current ripples. Then, i P can be resolved into fundamental component i Pf and current ripple component i Ps , so i P can be expressed as Similarly, u PL can be resolved into fundamental component u Pf and switching harmonic component u Ps , i.e., In the steady state, i Pf can be expressed as Correspondingly, i Ps can be derived using (1), (4), (5) and (6), as follows Then, from (3) and (7), the expression of grid current i g can be obtained as Since the switching frequency of the AHEU is far above than that of the PIU, the influence of high-frequency voltage harmonics on the output currents of the proposed inverter can be ignored.
To suppress current ripple, the ripple compensation voltage u E is designed as From Figure 2, the i A can be expressed as Substitute (10) and (9) into (8), the grid current i g is From (11), the current ripple component in i Ps is completely eliminated by i A . Obviously, the resonance phenomenon of the LCL-type GCI can be eliminated by the proposed inverter. In consequence, the system stability can be improved, and the control algorithm is simplified significantly.

Design of the PIU Filter Inductance L P
Due to low switching frequency of the PIU, its current ripple is significant compared with rated current. When the current ripple increases, it leads to an increase in the switching stress of the power semiconductor devices and the inductor loss, which can reduce the efficiency of the inverter [32]. Accordingly, it is essential to limit the current ripple. In general, the current ripple is limited to no more than 20% of the grid current amplitude I gm . However, the amplitude of the current ripple is subjected to the filter inductance of the PIU. Therefore, the lower limit of the filter inductance L P can be determined as follows where the f P is the switching frequency of the PIU.

Design of the AHEU Filter Inductance L A
The series resistances of the filter inductor L A can be neglected. For the AHEU, the transfer function from iA to u A is given as In this paper, the magnitude of 1/(L A S) <−50 dB at the switching frequency of the AHEU must be satisfied. Consequently, LA can be obtained as

Design of the DC-Link Voltage of the AHEU
In order that the current ripple can be eliminated by the output current of the AHEU completely, the dc-side voltage V dc2 of the AHEU should be larger than a certain voltage. In this paper, V dc2 is maintained at its reference V dc2 * by the voltage control loop. v g and i g can be expressed as where V gm and I gm are the grid voltage and current amplitude, respectively, ω g is the angular frequency of the grid. According to (9) and (11), the ripple compensation voltage u E can be expressed as where Considering the different switch states of the PIU, the peak value of u E can be expressed as According to the space vector pulse width modulation (SVPWM) technique, the dc-link voltage of the AHEU V dc2 should satisfy

Design of the Switching Frequency
The switching frequency of the two units is selected by combining the power loss and dead time of the inverter. The switching loss of the power electronic devices is increased with increasing the switching frequency, but the inductance of the filter decreases correspondingly with increasing the switching frequency, which may reduce the power loss on the inductance. Therefore, it is necessary to comprehensively consider the impact of switching frequency on switch loss and filter loss.
In Figure 3, the power loss at different switching frequencies of the PIU when the switching frequency of AHEU f A is 60 kHz is shown. It can be seen that the power loss of the system is the lowest at about 6 kHz. However, the switching frequency of the GCI is usually set below 3 kHz in high-power applications. In order to simulate a high-power GCI and analyze the stability under low switching frequency, combined with the loss analysis results, a switching frequency of the PIU f P of 2.5 kHz was chosen in this paper.

Design of the Switching Frequency
The switching frequency of the two units is selected by combining the power loss and dead time of the inverter. The switching loss of the power electronic devices is increased with increasing the switching frequency, but the inductance of the filter decreases correspondingly with increasing the switching frequency, which may reduce the power loss on the inductance. Therefore, it is necessary to comprehensively consider the impact of switching frequency on switch loss and filter loss.
In Figure 3, the power loss at different switching frequencies of the PIU when the switching frequency of AHEU fA is 60 kHz is shown. It can be seen that the power loss of the system is the lowest at about 6 kHz. However, the switching frequency of the GCI is usually set below 3 kHz in high-power applications. In order to simulate a high-power GCI and analyze the stability under low switching frequency, combined with the loss analysis results, a switching frequency of the PIU fP of 2.5 kHz was chosen in this paper. Figure 4 shows the loss curve of the system at different switching frequencies of AHEU when the fP was 2.5 kHz. From Figure 4, it can be seen that the change in fA had no significant impact on the system loss, because the output currents of the AHEU were small. With increasing the fA, the loss of the system was gradually decreased. When the switching frequency was higher than 60 kHz, the total loss of system hardly changed. Considering the dead time effect of the power switching device, the fA is 60 kHz.
Loss Power/W  Figure 4 shows the loss curve of the system at different switching frequencies of AHEU when the f P was 2.5 kHz. From Figure 4, it can be seen that the change in f A had no significant impact on the system loss, because the output currents of the AHEU were small. With increasing the f A , the loss of the system was gradually decreased. When the switching frequency was higher than 60 kHz, the total loss of system hardly changed. Considering the dead time effect of the power switching device, the f A is 60 kHz.

Stability Analysis of Proposed Inverter
The current control block diagram of the PIU is shown in Figure 5. From Figure 5, iPref is the current reference. GIP(s) is the current controller. The ∆ is the error between iPref and iP. GDP(s) is the system delay. KPWM is the gain of the inverter, which is equal to Vdc1/√3, Loss Power/W

Stability Analysis of Proposed Inverter
The current control block diagram of the PIU is shown in Figure 5. From Figure 5, i Pref is the current reference. G IP (s) is the current controller. The ∆i P is the error between i Pref and i P . G DP (s) is the system delay. K PWM is the gain of the inverter, which is equal to V dc1 / √ 3, G FP (s) is the grid voltage feedforward coefficient, which is equal to 1/ K PWM . Z g is the grid impedance. u PCC is the voltage at the point of common coupling (PCC). The grid equivalent resistance can provide certain damping, which can improve the stability of the system. In order to discuss the most unstable conditions, only the influence of the grid inductance L g is considered here; that is, Z g = L g s.

Stability Analysis of Proposed Inverter
The current control block diagram of the PIU is shown in Figure 5. From Figure 5, iPref is the current reference. GIP(s) is the current controller. The ∆ is the error between iPref and iP. GDP(s) is the system delay. KPWM is the gain of the inverter, which is equal to Vdc1/√3, GFP(s) is the grid voltage feedforward coefficient, which is equal to 1/ KPWM. Zg is the grid impedance. uPCC is the voltage at the point of common coupling (PCC). The grid equivalent resistance can provide certain damping, which can improve the stability of the system. In order to discuss the most unstable conditions, only the influence of the grid inductance Lg is considered here; that is, Zg = Lgs. The open-loop transfer function in Figure 5 from ∆ to iP can be expressed as The Bode plots of ∆ _ under different grid conditions is shown in Figure 6. When Lg = 0 mH, the PIU operates with an ideal grid, the phase margin (PM) of ∆ _ is 51.3°. As Lg increases, the PM of ∆ _ decreases slightly. When Lg = 1 mH, the PM of ∆ _ The open-loop transfer function in Figure 5 from ∆i P to i P can be expressed as The Bode plots of G ∆iP_iP under different grid conditions is shown in Figure 6. When L g = 0 mH, the PIU operates with an ideal grid, the phase margin (PM) of G ∆iP_iP is 51.3 • . As L g increases, the PM of G ∆iP_iP decreases slightly. When L g = 1 mH, the PM of G ∆iP_iP is 47.1 • , and when L g = 2 mH, the PM of G ∆iP_iP is 43.6 • , indicating the PIU has good stability under weak grid conditions.  The current control block diagram of AHEU is the same as the PIU; the open-loop transfer function of the AHEU from ∆i A to i A can be expressed as The Bode plots of G ∆iA_iA under different grid conditions is shown in Figure 7. When L g = 0 mH, the PM of G ∆iA_iA is 78.6 • . When L g = 1 mH, the PM is 67.5 • , and when L g = 2 mH, the PM is 59.2 • . According to Figures 6 and 7, the proposed inverter improved the stability.
The Bode plots of ∆ _ under different grid conditions is shown in Figure 7. When Lg = 0 mH, the PM of ∆ _ is 78.6°. When Lg = 1 mH, the PM is 67.5°, and when Lg = 2 mH, the PM is 59.2°. According to Figures 6 and 7, the proposed inverter improved the stability.

Proposed Inverter's Control Scheme
A reference-frame transformation-based control scheme is used for dual-frequency three-phase GCI as shown in Figure 8. The control structure consists of two independent control loops which are the power control loop and the auxiliary control loop, respectively. The synchronous reference frame phase-locked loop is used to extract the phase angle θ g of the grid. The SVPWM is used to drive power electronic devices. Although the SVPWM algorithm has large amplitude harmonics near the switching frequency and its doubling frequency [33], the SVPWM method has a higher DC voltage utilization and lower THD [34]. And there is significant flexibility in switching state selection [35]. In this paper, the SVPWM used can suppress the low-order harmonics significantly and decrease the requirement for a dc-link voltage. The lower capacitance of AHEU is available, reducing the system cost.
The power control loop is used to control the output currents i P to transfer active power to the grid. The output currents i P are transformed into the dq-reference frame. In Figure 8, i * gd and i * gq are the grid current references in the dq-reference frame. In the power control loop, the current references i * gd and i * gq are compared with i Pd and i Pq , respectively. The power current controller block consists of two proportional resonant (PR) regulators [36,37]. u Pd and u Pq are the sum of the grid compensation voltages, outputs of the current controller and the coupling components, as shown in Figure 8.  (24 where I * gm is the reference amplitude of the grid current.  The auxiliary control loop generates i A to eliminate the current ripple generated by the PIU. Similarly, the auxiliary current controller block consists of two PR regulators. In addition, the dc-link voltage V dc2 is controlled by the auxiliary control loop to track its reference V * dc2 . From Figure 8, the output of the voltage regulator AVR is i * Ad which is compared with i Ad . The q-axis reference current i * Aq is equal to zero. It was noted that i Pf can be approximated as i * g in steady state. In (9), the differential item di Pf /dt can be substituted as: where I * gm is the reference amplitude of the grid current. According to (9), the ripple compensation voltages u E can be determined by where theû P is the estimation of u P . Since the control scheme of the proposed inverter is realized by one micro controller, theû P can be obtained by the drive signals of the PIU. The modulation signals of auxiliary control loop can be expressed as where u ACCd and u ACCq are the output of auxiliary current controllers, u Ed and u Eq represent the ripple compensation voltages in dq-reference frame, ωLi Ad , ωLi Aq and v gd and v gq are coupling components and grid compensation voltages, respectively.
For the above ripple elimination method, it is not necessary to sample the output voltage of the PIU. As a result, the hardware complexity of the control system can be reduced. i * g are current references rather than the measured values, thus, the differential item di * g /dt is a dc component which can eliminate the amplification effect of differential items on the measurement of noise. It can improve the inverter performance. Consequently, compared with other methods extracting the harmonics as the reference, the proposed method is not necessary for the requirements of current sampling accuracy, pulse ratio of the PIU or current control bandwidth.

Experiment Results
A laboratory prototype of a 10 kW three-phase dual-frequency GCI was developed to verify the performance of the proposed inverter. The laboratory prototype is shown in Figure 9. The IGBTs (IKW40N120T2) and the SiC-MOSFET (IMW120R220M1H) were used in the PIU and the AHEU respectively. The controller of the proposed inverter is based on a digital controller (STM32F407ZET6) and CPLD (EPM1270T144C5N). The control algorithm shown in Figure 8 was implemented by digital controller, and CPLD was used to generate PWM signals to drive the power electronic devices. According to the modulated signal generated from the ARM, the CPLD generated 12 gate pulses, which were fed to the respective eight switches of the proposed topology. The system parameters are listed in Table 1. The phase grid voltage (RMS) was 220 V, and the grid frequency was 50 Hz.
the ripple compensation voltages in dq-reference frame, ωLiAd, ωLiAq and vgd coupling components and grid compensation voltages, respectively.
For the above ripple elimination method, it is not necessary to sample voltage of the PIU. As a result, the hardware complexity of the control system duced. i * g are current references rather than the measured values, thus, the item di * g/dt is a dc component which can eliminate the amplification effect of items on the measurement of noise. It can improve the inverter performan quently, compared with other methods extracting the harmonics as the referen posed method is not necessary for the requirements of current sampling accu ratio of the PIU or current control bandwidth.

Experiment Results
A laboratory prototype of a 10 kW three-phase dual-frequency GCI was to verify the performance of the proposed inverter. The laboratory prototype Figure 9. The IGBTs (IKW40N120T2) and the SiC-MOSFET (IMW120R220M1H in the PIU and the AHEU respectively. The controller of the proposed inverter a digital controller (STM32F407ZET6) and CPLD (EPM1270T144C5N). The co rithm shown in Figure 8 was implemented by digital controller, and CPLD w generate PWM signals to drive the power electronic devices. According to the signal generated from the ARM, the CPLD generated 12 gate pulses, which the respective eight switches of the proposed topology. The system paramete in Table 1. The phase grid voltage (RMS) was 220 V, and the grid frequency w

Parameters
Power Inverter Unit (PIU) Auxiliary Harmo nation Unit (A Switching frequency 2.5 kHz 60 kHz Dc-link voltage 700 V 700 V Figure 9. Photograph of the laboratory prototype.

Suppression Effect of Current Ripple
The simulation results of the PIU output currents i P , grid currents i g and phase-a AHEU output current i Aa are shown in Figure 10a,b,c, respectively. Figure 11 shows the FFT analysis of the output current of the PIU and the grid current. From Figure 10a, it can be observed that the output current ripple by the PIU was large, especially at the zero crossing. The THDs of i Pa was 12.18%, and did not satisfy the grid standards, as shown in Figure 11. The peak-to-peak values of the AHEU output current in Figure 10b were relatively large near 0.205 s and 0.215 s, corresponding to the zero crossing of the phase-a PIU output current i Pa . It indicates that the power quality was improved by the AEHU output current, according to the amplitude of the ripple component. It can be seen that the current ripple was suppressed effectively compared with i P , as shown in Figure 10c, particularly at the zero crossing. The improvement effect of the grid current could also be proven, as shown in Figure 11. The THD of i ga was 3.91%, satisfying grid standards.
FFT analysis of the output current of the PIU and the grid current. From Figure 10a, it can be observed that the output current ripple by the PIU was large, especially at the zero crossing. The THDs of iPa was 12.18%, and did not satisfy the grid standards, as shown in Figure 11. The peak-to-peak values of the AHEU output current in Figure 10b were relatively large near 0.205 s and 0.215 s, corresponding to the zero crossing of the phase-a PIU output current iPa. It indicates that the power quality was improved by the AEHU output current, according to the amplitude of the ripple component. It can be seen that the current ripple was suppressed effectively compared with iP, as shown in Figure 10c, particularly at the zero crossing. The improvement effect of the grid current could also be proven, as shown in Figure 11. The THD of iga was 3.91%, satisfying grid standards. The PIU output currents iP, AHEU output currents iA and grid currents ig, are shown in Figure 12a,b,c,d, respectively. In Figure 12a, the RMS value of iP was about 15 A. The current ripples in the output currents of the PIU were significant. The three phase output currents of AHEU iA are shown in Figure 12b. The average value of iA was approximately 0, indicating that the power consumed by the AHEU is very small. Figure 12c shows the three phase grid currents ig. In Figure 12d, it can be observed that iAa was opposite to iPa. As a consequence, compared with iP, the current ripples of ig were reduced significantly. Meanwhile, the peak value of iAa was about 2 A, indicating that it was far less than the rated current. This shows that the conduction loss and cost of the AHEU are much lower than the PIU. The FFT analysis of iPa and iga are shown in Figure 13. The THDs of iPa and iga were 7.33 and 3.01%, respectively. Compared to iPa, the THD of iga was significantly reduced, less than 5%, complying with grid standards.  The PIU output currents i P , AHEU output currents i A and grid currents i g , are shown in Figure 12a,b,c,d, respectively. In Figure 12a, the RMS value of i P was about 15 A. The current ripples in the output currents of the PIU were significant. The three phase output currents of AHEU i A are shown in Figure 12b. The average value of i A was approximately 0, indicating that the power consumed by the AHEU is very small. Figure 12c shows the three phase grid currents i g . In Figure 12d, it can be observed that i Aa was opposite to i Pa . As a consequence, compared with i P , the current ripples of i g were reduced significantly. Meanwhile, the peak value of i Aa was about 2 A, indicating that it was far less than the rated current. This shows that the conduction loss and cost of the AHEU are much lower than the PIU. The PIU output currents iP, AHEU output currents iA and grid currents ig, are shown in Figure 12a,b,c,d, respectively. In Figure 12a, the RMS value of iP was about 15 A. The current ripples in the output currents of the PIU were significant. The three phase output currents of AHEU iA are shown in Figure 12b. The average value of iA was approximately 0, indicating that the power consumed by the AHEU is very small. Figure 12c shows the three phase grid currents ig. In Figure 12d, it can be observed that iAa was opposite to iPa. As a consequence, compared with iP, the current ripples of ig were reduced significantly. Meanwhile, the peak value of iAa was about 2 A, indicating that it was far less than the rated current. This shows that the conduction loss and cost of the AHEU are much lower than the PIU. The FFT analysis of iPa and iga are shown in Figure 13. The THDs of iPa and iga were 7.33 and 3.01%, respectively. Compared to iPa, the THD of iga was significantly reduced, less than 5%, complying with grid standards.  The FFT analysis of i Pa and i ga are shown in Figure 13. The THDs of i Pa and i ga were 7.33 and 3.01%, respectively. Compared to i Pa , the THD of i ga was significantly reduced, less than 5%, complying with grid standards.
From Figure 13, the harmonics around the switching frequency fP were reduced from about 3.7 to 0%. Furthermore, the harmonics around the integral multiple of the switching frequency fA could also be eliminated by the AHEU. The fundamental component of iPa was same as that of iga. This means that the active power is transmitted to the grid by the PIU.

Performance of the Proposed Inverter under Dynamic Changing Load Conditions
When the grid current reference was changed, the responses of iga, iAa and iPa are shown in Figure 14. From Figure 14, it can be seen that when the grid current reference changed, iPa responded quickly, without a large current overshoot and oscillation, and tracked the current reference value again within three cycles. Compared with iPa, iga had a decrease in ripple content and changed synchronously with iPa as the grid current reference changed, indicating that the dynamic process had no significant impact on the harmonic suppression effect.  From Figure 13, the harmonics around the switching frequency f P were reduced from about 3.7 to 0%. Furthermore, the harmonics around the integral multiple of the switching frequency f A could also be eliminated by the AHEU. The fundamental component of i Pa was same as that of i ga . This means that the active power is transmitted to the grid by the PIU.

Performance of the Proposed Inverter under Dynamic Changing Load Conditions
When the grid current reference was changed, the responses of i ga , i Aa and i Pa are shown in Figure 14. From Figure 14, it can be seen that when the grid current reference changed, i Pa responded quickly, without a large current overshoot and oscillation, and tracked the current reference value again within three cycles. Compared with i Pa , i ga had a decrease in ripple content and changed synchronously with i Pa as the grid current reference changed, indicating that the dynamic process had no significant impact on the harmonic suppression effect. From Figure 13, the harmonics around the switching frequency fP were reduced from about 3.7 to 0%. Furthermore, the harmonics around the integral multiple of the switching frequency fA could also be eliminated by the AHEU. The fundamental component of iPa was same as that of iga. This means that the active power is transmitted to the grid by the PIU.

Performance of the Proposed Inverter under Dynamic Changing Load Conditions
When the grid current reference was changed, the responses of iga, iAa and iPa are shown in Figure 14. From Figure 14, it can be seen that when the grid current reference changed, iPa responded quickly, without a large current overshoot and oscillation, and tracked the current reference value again within three cycles. Compared with iPa, iga had a decrease in ripple content and changed synchronously with iPa as the grid current reference changed, indicating that the dynamic process had no significant impact on the harmonic suppression effect.

Performance of the Proposed Inverter under a Weak Grid
To simulate the grid impedance, the inductors were added into the grid, as shown in Figure 15. The inductance of Lg was 2 mH. Figure 16 shows the a-phase u PCC and output currents of the proposed inverter under a weak grid. In Figure 16a, the harmonic component in u PCC was obviously affected by Lg. In Figure 16b, the harmonic component of i Pa was also eliminated effectively by i Aa . The THD of the grid current i ga was 4.83%, lower than 5%, which satisfies the grid standard. The proposed inverter still had good performance and stability under weak grid conditions. To simulate the grid impedance, the inductors were added into the grid, as shown in Figure 15. The inductance of Lg was 2 mH. Figure 16 shows the a-phase uPCC and output currents of the proposed inverter under a weak grid. In Figure 16a, the harmonic component in uPCC was obviously affected by Lg. In Figure 16b, the harmonic component of iPa was also eliminated effectively by iAa. The THD of the grid current iga was 4.83%, lower than 5%, which satisfies the grid standard. The proposed inverter still had good performance and stability under weak grid conditions.

Circulating Current Analysis
The circulating current is generated among the parallel inverters owing to the inconsistency of system impedance and the switching action. However, regardless of the switching state of the power electronic devices, the circulating currents need to pass through a common dc-link to form a circulating current path, and the two units of the proposed inverter do not share a common dc-link. The experimental results are shown in Figure 17. It can be seen that for the waveforms of the filter inductance currents iPa1, iPa2, iAa1 and iAa2, as shown in Figure 17a,b, that iPa1 is equal to iPa2, and iAa1 is equal to iAa2. This means that the inverter proposed in this paper does not have circulation problems. To simulate the grid impedance, the inductors were added into the grid, as shown in Figure 15. The inductance of Lg was 2 mH. Figure 16 shows the a-phase uPCC and output currents of the proposed inverter under a weak grid. In Figure 16a, the harmonic component in uPCC was obviously affected by Lg. In Figure 16b, the harmonic component of iPa was also eliminated effectively by iAa. The THD of the grid current iga was 4.83%, lower than 5%, which satisfies the grid standard. The proposed inverter still had good performance and stability under weak grid conditions.

Circulating Current Analysis
The circulating current is generated among the parallel inverters owing to the inconsistency of system impedance and the switching action. However, regardless of the switching state of the power electronic devices, the circulating currents need to pass through a common dc-link to form a circulating current path, and the two units of the proposed inverter do not share a common dc-link. The experimental results are shown in Figure 17. It can be seen that for the waveforms of the filter inductance currents iPa1, iPa2, iAa1 and iAa2, as shown in Figure 17a,b, that iPa1 is equal to iPa2, and iAa1 is equal to iAa2. This means that the inverter proposed in this paper does not have circulation problems.

Circulating Current Analysis
The circulating current is generated among the parallel inverters owing to the inconsistency of system impedance and the switching action. However, regardless of the switching state of the power electronic devices, the circulating currents need to pass through a common dc-link to form a circulating current path, and the two units of the proposed inverter do not share a common dc-link. The experimental results are shown in Figure 17. It can be seen that for the waveforms of the filter inductance currents i Pa1 , i Pa2 , i Aa1 and i Aa2 , as shown in Figure 17a,b, that i Pa1 is equal to i Pa2 , and i Aa1 is equal to i Aa2 . This means that the inverter proposed in this paper does not have circulation problems.

Efficiency Analysis
The efficiency curves of the three-phase dual-frequency GCI and the traditional GCI are shown in Figure 18, reflecting the efficiency advantages of the three-phase dual-frequency GCI. The switching frequency of the traditional GCI operates at approximately 9 kHz to comply with grid code requirements. To decrease the switching loss, the PIU operates at 2.5 kHz switching frequency. Due to the relatively low switching frequency of the proposed inverter in this paper, when the same switching frequency is used by traditional inverters, such as the PIU, the filter needs to use more inductance to satisfy the grid standards. Figure 18 shows the efficiency curves of the traditional inverter and the proposed inverter at different currents. When the amplitude of the grid current was 21 A (rated current), the efficiency of the three-phase dual-frequency GCI was 95.99%, which is approximately 0.82% higher than the traditional GCI. Figure 18. Efficiency of the three-phase dual-frequency GCI and the traditional three phase GCI for different grid current amplitudes.
According to [38], the power losses of two inverters can be evaluated at rated current, as shown in Table 2. It can be seen that although the traditional inverter reduces switching losses, the power loss generated on the passive filter is too large, resulting in a much greater power consumption on the filter than on the AHEU. Therefore, under different currents, the efficiency of traditional inverters is lower than that of the proposed inverters.

Efficiency Analysis
The efficiency curves of the three-phase dual-frequency GCI and the traditional GCI are shown in Figure 18, reflecting the efficiency advantages of the three-phase dual-frequency GCI. The switching frequency of the traditional GCI operates at approximately 9 kHz to comply with grid code requirements. To decrease the switching loss, the PIU operates at 2.5 kHz switching frequency. Due to the relatively low switching frequency of the proposed inverter in this paper, when the same switching frequency is used by traditional inverters, such as the PIU, the filter needs to use more inductance to satisfy the grid standards.

Efficiency Analysis
The efficiency curves of the three-phase dual-frequency GCI and the traditional GCI are shown in Figure 18, reflecting the efficiency advantages of the three-phase dual-frequency GCI. The switching frequency of the traditional GCI operates at approximately 9 kHz to comply with grid code requirements. To decrease the switching loss, the PIU operates at 2.5 kHz switching frequency. Due to the relatively low switching frequency of the proposed inverter in this paper, when the same switching frequency is used by traditional inverters, such as the PIU, the filter needs to use more inductance to satisfy the grid standards. Figure 18 shows the efficiency curves of the traditional inverter and the proposed inverter at different currents. When the amplitude of the grid current was 21 A (rated current), the efficiency of the three-phase dual-frequency GCI was 95.99%, which is approximately 0.82% higher than the traditional GCI. Figure 18. Efficiency of the three-phase dual-frequency GCI and the traditional three phase GCI for different grid current amplitudes.
According to [38], the power losses of two inverters can be evaluated at rated current, as shown in Table 2. It can be seen that although the traditional inverter reduces switching losses, the power loss generated on the passive filter is too large, resulting in a much greater power consumption on the filter than on the AHEU. Therefore, under different currents, the efficiency of traditional inverters is lower than that of the proposed inverters.  Figure 18. Efficiency of the three-phase dual-frequency GCI and the traditional three phase GCI for different grid current amplitudes. Figure 18 shows the efficiency curves of the traditional inverter and the proposed inverter at different currents. When the amplitude of the grid current was 21 A (rated current), the efficiency of the three-phase dual-frequency GCI was 95.99%, which is approximately 0.82% higher than the traditional GCI.
According to [38], the power losses of two inverters can be evaluated at rated current, as shown in Table 2. It can be seen that although the traditional inverter reduces switching losses, the power loss generated on the passive filter is too large, resulting in a much greater power consumption on the filter than on the AHEU. Therefore, under different currents, the efficiency of traditional inverters is lower than that of the proposed inverters.

Conclusions
In this paper, a novel three-phase dual-frequency GCI was proposed. The active power is supplied to the grid by the PIU at a low switching frequency. Based on a simple feedforward compensation method, the AHEU operates at a high switching frequency to eliminate the grid current ripple. The circulating current between the two units can be blocked by isolated dc-links. As the switching frequency of PIU is low, the efficiency of the inverter can be improved. Moreover, the proposed GCI addresses the stability issues arising from the inherent resonance of the LCL filter by using an L filter. The efficiency of the proposed inverter was more than 0.82% higher than the traditional GCI at rated current.