Stabilization of Constant Power Loads in DC Microgrid Systems Using an Adaptive Continuous Control Set Model Predictive Control

: This paper represents an adaptive continuous control set model predictive control (CCS-MPC) to solve the disturbance-caused instability problems in a DC microgrid consisting of symmetrical parallel buck converters, constant voltage loads (CVL), and constant power loads (CPL). The symmetric model of the system is founded at ﬁrst to describe and analyze the disturbance-caused instability problem. To mitigate the instability by taking the disturbances into consideration, the proposed adaptive controller is made from a double loop feedback controller and a feedforward estimation algorithm. In the voltage loop of the double loop controller, a capacitor dynamic-based voltage controller is developed, while in the current loop, a CCS-MPC algorithm is modiﬁed and applied. Meanwhile, a feedforward algorithm is developed to estimate the disturbance information and send it to the double loop controller to improve its robustness, so the composite controller can maintain the bus voltage ﬁxed at its reference and the symmetrical equal current sharing. Finally, comparative MATLAB simulations and OPAL-RT hardware-in-the-loop experiments are conducted to verify the effectiveness and dynamic performance of the proposed algorithm towards other previous nonlinear controllers.


Introduction
As a natural platform for distributed renewable energy generation, DC microgrids have attracted a great amount of focus from scholars worldwide [1][2][3][4]. A typical DC microgrid structure consisting of parallel buck converters and different loads is shown in Figure 1. As can be seen, parallel converters have been applied to increase the system stability and flexibility and reduce the power stress on each single converter. However, with the application of multiple converters, the suitable operation of the parallel converters needs to be solved [5]. In the DC microgrid, many converter-linked loads are used, and they often operate in a tightly regulated point of load mode, which makes it so they can be redeemed as the constant power load (CPL). As opposed to the constant voltage load (CVL), which can usually be represented by a resistor, CPL always consumes a fixed amount of power regardless of the value of the input voltage. Therefore, the input current decreases while the input voltage increases, and vice-versa [6,7]. Although the high efficiency and controllability of the load can be ensured by tight regulation, this unwanted phenomenon creates negative incremental impedance, which makes the system poorly damped, introduces voltage oscillation, or even leads to instability issues [8,9]. In order to mitigate the instability problem caused by the CPLs in the DC microgrid, much research has been conducted by scholars. In the beginning, passive damping and linear-based active damping algorithms were proposed. In [8,10], the necessary capacitors, resistors, and LC filters are designed and added into the circuit to improve the damping of the system. Even though the oscillation of the system can be dissipated, the weight, cost, and power loss of the system also increase with the addition of those passive damping elements. For the linear-based active damping algorithm, the instability of the system can also be mitigated by reshaping the impedance of the source and load [7,11]. However, due to the adoption of small-signal-model-based linear techniques, these approaches can only ensure system stability around the operating points; a typical system behavior away from this point cannot be obtained [7].
In order to guarantee the stability of the system in the large signal region, many nonlinear control methods are applied to mitigate the instability problem. In [12], the instability problem caused by the CPL in the buck converter is solved by a boundary controller, even without knowing all the detailed parameters of the system. However, this control algorithm is designed on the hysteresis band; problems such as the variable switching frequency and degraded ripple effect are also introduced. In [13], a wide operation range sliding mode controller with fixed switching frequency is proposed to ensure the stability of the system, but this algorithm needs to obtain the value of the capacitor current, and the measurement used leads to the degraded ripple filtering effect and the introduction of equivalent series resistance (ESR) of the capacitor. Moreover, this controller needs to operate in a very high frequency, which introduces the chattering problem. In [14], a synergetic control method is applied to stabilize parallel DC-DC buck converters with CPL; the experiment shows that this method has good dynamics and fast response performance. However, this paper lacks a detailed analysis for CPL. In [15], an adaptive passivity-based control (PBC) is proposed; in order to mitigate the instability caused by disturbance, PBC is combined with a nonlinear disturbance observer (NDO). However, the performance of this algorithm's tuning relies on the parameters R 1d , R 2d , λ 1 , and λ 2 .
As a promising controller, more and more scholars use the model predictive control (MPC) to solve problems in power electronics [16]. In general, MPC defines the control actions by minimizing a cost function that describes the desired system behavior. This cost function compares the reference with the predicted system output, which is computed from the system model [17]. Therefore, an accurate predictive model and proper cost function are the corner stone of an effective MPC. However, the predictive model is usually impacted by disturbance, model uncertainty, and model mismatch. In order to overcome these defects, many modified MPC controllers have been proposed. In [18], a PI-MPC is combined with a Luenberger observer to mitigate the static error caused by the model mismatch of the ignorance of the equivalent serial resistance (ESR). In this paper, a PI-MPC controller is used to track the reference, while the Luenberger observer is designed and set in the feedforward loop to compensate for the error caused by the model mismatch.
In [19], in order to eliminate the offset caused by the change of resistive load and the model mismatch of inductance, a continuous control set model predictive control (CCS-MPC) is combined with the Luenberger observer. The MPC methods proposed above have done a good job of eliminating the static error in output; however, they do not take into consideration the NIR caused by CPL, which has a much larger negative impact on stability. In [20], a high-order sliding mode observer (HOSMO) is designed and combined with MPC to eliminate the output offset of a buck converter suppling CPL. With the help of HOSMO, the proposed method can track the reference both accurately and rapidly, regardless of the disturbance, as the variation of the input voltage, resistive load, and CPL. In [21], an explicit model predictive control (eMPC) is used to ensure the stable operation of a boost converter supplying the CPL. By solving a multiparametric nonlinear problem over a simplex partition of state space, the optimal control law can be obtained. However, in order to mitigate the instability caused by CPL, both the output voltage and the output current of the converter are needed. A decentralized model predictive control (DMPC) is proposed to ensure the power sharing and stability of a multiboost converter system supplying the CPL [22]. Supplied by the value of the power of the CPL, the proposed DMPC can correctly regulate the DC bus voltage. In [23], the MPC is combined with an extended Kalman Filter to ensure the stability of a shipboard DC microgrid consisting of a time-varying CPL from the perspective of the secondary control.
In this paper, the instability problem caused by the disturbances (such as variation of input voltage, CVL, and CPL) will be addressed and mitigated. During this process of making the DC microgrid system more robust under disturbances, a composite adaptive CCS-MPC algorithm is proposed. In the controller, a CCS-MPC and capacitor dynamicbased voltage controller are designed and combined as a united double loop controller. Moreover, based on the dynamic characteristics of the circuit, a feedforward-based estimation algorithm is developed and set in the feedforward loop to compensate for the error made by disturbance. With the increment of the robustness by the proposed estimation algorithm, the proposed controller can track the reference both rapidly and accurately regardless of the disturbance. This paper is organized as follows: Section 2 presents the establishment of the symmetrical model of the circuit and the description of the problem. Section 3 introduces the design of proposed adaptive CCS-MPC with the parallel feedforward estimation algorithm. The MATLAB simulation and hardware-in-the-loop (HIL) experiment results are presented in Sections 4 and 5, respectively, while the conclusion is written in Section 6.

System Equation Modeling and Problem Description
The system described in Figure 1 can be represented by two symmetrical parallel source converters supplying composite loads (CVLs and CPLs) by a common load bus, which is depicted in Figure 2 shown below. It is worth mentioning that the system is symmetrical which is beneficial for sharing the load of converter. In this figure, the parameters (E 1 , E 2 ), (L 1 , L 2 ), and (C 1 , C 2 ) represent the input voltage, inductance, and capacitance of the two buck converters, respectively. Meanwhile, the (i L1 , i L2 ) and (v C1 , v C2 ) are the inductor current and the capacitor voltage of two source converters. Assuming the system works in continuous current mode (CCM) and the output voltages for each converter here are equal, the dynamic model can then be derived as where the C eq is the equivalent capacitance, v C is the voltage of DC load bus, and (µ 1 , µ 2 ) are the duty ratio of the converters. According to the dynamic equations of the system, it can be known that the model mismatch of inductance, capacitance, and the equivalent serial resistance (ESR) of the inductor can lead to a static error of the output if their variations cannot be taken into consideration. The disturbances, such as the variation of the input voltage and resistance of the CVL and CPL, can also impact the stability of the system negatively. However, among all the destabilizing factors mentioned above, the last three have a more negative impact on the stability of system [15,18], and if these variations are involved, Equation (1) can be modified as follows: where (∆E 1 , ∆E 2 ) represent the variation of input voltage, ∆R represents the variation of resistance of the CVL, and ∆P represents the variation of the CPL power. As can be seen from the equations above, if these disturbances cannot be taken into consideration by the controller, the stability of the system will be impacted, and the static error shown in the bracket will be introduced.

Design of the Proposed Method
In this section, the proposed adaptive CCS-MPC with feedforward estimation algorithm is constructed. The double loop structure is chosen as the basic form of the controller. In the voltage loop, a voltage controller which is based on the dynamic character of the capacitor is established. Meanwhile, a CCS-MPC is designed and applied as the current loop controller. Even though this double loop controller can track the reference in a nominal condition, a static error will be introduced when disturbances occur. In order to make this controller robust enough even when disturbances exist, a feedforward estimation algorithm derived from the dynamic equation of the circuit is developed. During the operation of the controller, the estimation algorithm works in parallel to supply the disturbance information to the double loop controller. Additionally, the load information estimated by the feedforward estimator can also ensure the load allocation between the parallel converters. Moreover, at the end of this section, in order to protect the system from the circulating current problem, the proposed controller is combined with the droop method to ensure that the output voltage of each converter is equal.

Design of Voltage Loop
For each buck converter, the change of capacitor voltage is directly related to the current flowing through it, as in the equation shown below: According to the Euler Forward method, the above equation can be modified as the equation shown below. By doing so, the current flowing through the capacitor can be calculated from the change of the capacitor voltage, and Ts in the equation below represents the switching period of the converter: assuming the change of v C follows a linear route during the period approaching the voltage reference v ref . Furthermore, the value of i C cannot be arbitrarily large, since it is decided by the error between v C and v ref , and a reference prediction horizon N is introduced [24][25][26]. As shown in Figure 3, v C arrives at its reference v ref after N switching cycles. As shown in Figure 3, the voltage at moment k v C (k) a (or v C (k) b ) is higher (or lower) than the reference voltage v ref , so it needs to follow the av (or bv) route to approach its final reference voltage v ref . Accordingly, this process also leads to the current step down to i C (k + 1) from i C (k) a (or step up to i C (k + 1) from i C (k) b ). Therefore, Equation (4) can be modified as After the value of v C is obtained, the future inductor current can be also calculated with the help of the basic Kirchhoff's current law: the inductor current at the next instant equals the current flowing through the capacitors, CVL and CPL. Assuming that the resistance of CVL and the power of CPL will not change suddenly, the inductor current at the next k + 1 moment can be calculated by the equation below: where i L (k + 1) is the inductor current in the next switching period and will be treated as the inductor current reference in the current loop. Therefore, for the parallel converters in this paper, the voltage loop controllers can be derived as where [i L1 (k + 1), i L2 (k + 1)] and [C 1 , C 2 ] are the inductor current at k + 1 instant (reference inductor current) and the capacitor of each buck converter, respectively, and a is the parameter concerning the power allocation between two buck converters. In order to realize the symmetrically equal current sharing, a is set to 2.

Construction of Current Loop
In the inner current loop, a one-step horizon is selected as the current control method for both of the buck converters. Compared with other multistep horizon CCS-MPC methods, the mentioned method does not have the requirement of high computation ability [19]. According to Equation (1), the change of the inductor current is directly related to the switch state, and its variation trend in one switching period can be depicted as Figure 4. Therefore, the current slope of i L1 and i L2 in one switching period can be represented by the following equation: where f i1 , f i2 , and f i3 are the current slope during the first turn-on period t 1 , first turn-off period t 2 , and second turn-on period t 3 in one switching period, respectively, and L n represents the inductance for the corresponding buck converter. As depicted in Figure 4, the inductor currents at the kT S + t 1 , kT S + t 1 + t 2 and kT S + t 1 + t 2 + t 3 are i S1 , i S2 , and i S3 , and they can be calculated through the equation given below. It is worth mentioning that in order to reduce the calculation burden, t 1 and t 3 are forced to be equal: where i S0 is the inductor current at the beginning of kT S , which can also be represented as i L (k). As one of the most important parts of the MPC method, cost function reflects the targets and constrains of the controller. Here, since the CCS-MPC works as the inner current loop, the only target of the cost function is to track the reference current as accurately as possible. Moreover, in order to make the inductor current as close as possible to the reference current, all of i S1 , i S2 , and i S3 are formulated into the cost function and further compared with the reference current by calculating the error between them.
By substituting Equation (9) into Equation (10), the latter can be modified as Replacing t 2 , t 3 with t 1 , T S , calculate the derivation of Equation (11), and its extreme point, the optimal value of t 1 which allows the cost function obtain its minimum value, can be obtained: After the optimal value t 1 is calculated, the related optimal duty ratio can also be obtained through the relationships between t 1 , t 2 , t 3 , and Ts. Due to similar topology, the above procedure is applicable for both parallel converters.

Foundation of Feedforward Estimation Algorithm
During the construction of the double loop control algorithm shown above, the value of input voltage and load are regarded as constant. However, disturbances, such as the variation of input voltage, resistance, and CPL, significantly impact the stability of the DC microgrid. If the controller wishes to become robust, it must take those negative factors into consideration. From Equation (2), it can be seen that these disturbances can affect the derivatives of inductor current and capacitor voltage. Therefore, when the time-varying load is not involved, such as in Equations (13) and (14), it is clear that the Equations (6) and (8) cannot behave as planned. As can be seen from Equation (13), the variation of the load (CVL and CPL) can impact the voltage loop controller by creating a static error which is shown at the end of the equation: where ∆R and ∆P CPL represent the variation of CVL and CPL, respectively, and C n stands for the capacitance of two buck converters. Similarly, when the change of the input voltage has been introduced from Equation (8), the current slope equations can be modified as where ∆E is the variation of the input voltage. In order to take these disturbances into consideration, an LC dynamic-based feedforward estimation algorithm is developed. Based on Kirchhoff's first law and Equation (4), the load current can be estimated by In the equation above, C eq is the equivalent capacitance of the microgrid system, and B is an estimation parameter and needs to be tuned. Similarly, based on the dynamic characteristics of the inductor and the Euler forward method, the input voltage can be obtained as follows for each buck converter: Combine Equations (15) and (7), and the current loops for the buck converters are listed as Similarly, substituting Equation (16) into Equation (8), the current slope during one switching period can be calculated as Therefore, the load current which has taken the disturbance into consideration can be calculated by the feedforward estimation algorithm in Equation (15); then, the reference current for each buck converter subsystem is produced by the voltage loop controller as Equation (17). In this process, the load current is also allocated. Additionally, based on the other part of the estimation algorithm shown in Equation (16) and the CCS-MPC current control method proposed in Equations (18) and (12), the reference current can be tracked accurately, and the optimal duty ratio is calculated. However, all the controllers mentioned above assume that the output voltage of the converters is equal. The condition of unbalanced output voltage will be considered in the following.

I-V Droop Control
In order to reduce the load pressure of a single converter, to improve the reliability of the power supply, and to improve the load supplying capacity, the structure of two parallel buck converters and the symmetrical equal current sharing are adopted in this paper. However, if the two converters operate unbalanced, even 1% of the mismatch between their output voltages can significantly negatively impact the symmetrically equal current allocation [27]. In the section above, we assumed that the output voltage of two converters is equal; when their output voltages are different, Equation (17) can be rewritten as where v C1 and v C2 are the output voltage for the two buck converters, respectively. In order to fulfill equal current sharing, the proposed controller is combined with the I-V droop control which can eliminate the error between the output voltage from two converters without output deviation [28]. By reversing the reference output from the traditional droop characteristic, the current reference produced by the I-V droop control can be given as In Equation (20), i Drefn (n = 1, 2) is the current reference produced by the I-V droop control, r n is the droop factor, which is derived by the virtual resistance method, and v Cn (n = 1, 2) is the output voltage for the two converters, respectively. According to [28], the product of the inductance current and virtual resistance of two systems should be equal.
Since the equal current allocation is chosen, the droop factor of the two buck converters is equal. Then, the current produced by the droop control is introduced into the voltage control algorithm in Equation (19), as shown below: Therefore, the diagram of the proposed control algorithm can be described as Figure 5. As it depicts, the voltage loop controller can be used to track the reference voltage and produce the reference current. Then, a CCS-MPC method is developed to track the reference current and calculate the optimal duty ratio, which will be sent to the buck converter later. Moreover, in the parallel feedforward loop, an estimation algorithm is used to calculate the disturbance information which will be sent to the controller mentioned above to ensure the fast and nonstatic-error operation of the system.

Simulation Results and Discussions
In this section, the dynamic performance of the proposed controller has been verified using the MATLAB Simulink platform. In order to ensure large signal stability and to realize offset-free tracking under disturbances, the simulations model is presented during the variation of the input voltage and loads (CVL and CPL). For both the MATLAB simulation and the hardware-in-the-loop experiment, the reference prediction horizon N of the voltage loop controller for parallel DC-DC power buck converters is set at 2, whereas the estimate factor B is set at 5. Likewise, the i L , v C , and µ used in Equations (15) and (16) are their average values. The circuit parameters used in the system (DC-DC buck power converters with CPL and CVL) are listed in Table 1 below.

Input Voltage Disturbances
Here, the performance of the proposed control method under the variation of input voltage is obtained by the corresponding MATLAB simulation, and its simulation results are shown in Figure 6. In this simulation, the input voltage variation for buck power converter 1 (red line) and buck converter 2 (blue line) are shown in the third subfigure of Figure 6. As can be seen, during the variation of the input voltage, the overshoots of the load bus voltage are quite slight, and it recovers to the reference voltage in a very short time. Therefore, the proposed method provides accurate tracking control during the input voltage variation. Due to the scale of this figure, more detailed information of dynamic performance will be shown in the later contrast simulation towards nominal CCS-MPC and PBC + NDO.

CVL Disturbances
In order to obtain the performance of the proposed method during the CVL disturbance, the corresponding simulation is conducted, and its results are shown in Figure 7. The nominal resistance of the CVL is set at 50 Ω; in this simulation, it decreases to 33.3 Ω at time 0.04 s, and it recovered to 50 Ω again at time 0.02 s. As can be seen from Figure 7, during the fall in the resistance, the output voltage decreases to 749.3 V, and after 1.3 ms it recovers to its reference value. We can notice that an excellent dynamic performance is also obtained: when the resistance increased at 0.04 s, the capacitor voltage increased to around 750.7 V, and it quickly returned to 750 V within 1.2 ms. In this test, the proposed method is robust enough, and no steady-state error is created during the disturbance of the CVL.

CPL Disturbances
In this section, we aim to examine the performance of the proposed control strategy against the disturbances caused by the CPL variations, and the detailed performance information is shown in Figure 8. During the simulation, the power of the CPL steps up from 43.2 kW to 65.1 kW in three steps, and it recovers to 43.2 kW later, step by step. As can be observed, during the variation of the CPL, the maximum variation of the load bus voltage is around 749.2 V, and it returns to the nominal value in 1.5 ms. According to the dynamic performance shown in Figure 8, we can conclude that the proposed method is valid under the disturbance of CPL. Even though the equal current sharing is adopted by the proposed control algorithm, as can be observed in Figures 7 and 8, the inductor current in the instant of the CPL variation is not equal. This phenomenon is mainly caused by the inconsistency of two converter parameters. With all the simulation results shown from Figure 6 to Figure 8, the conclusion can be drawn that the proposed method can ensure large signal stability during the existence of disturbances.

Comparison between the Proposed Method and Previous Literature
In this section, the dynamic performance of the proposed control method will be compared with the PBC + NDO in [29] and the nominal CCS-MPC method. For both comparisons, the simulations under the disturbance of input voltage and load (CVL and CPL) are conducted. Aside from the absence of the estimation algorithm, when compared with the proposed MPC controller, the rest of the parts of the nominal CCS-MPC are entirely the same. Figure 9 shows the performance between the proposed algorithm and the nominal CCS-MPC during the disturbance of input voltage. In this simulation, the change of the input voltage is the same as that shown in Figure 6. As can be observed, even though the nominal CCS-MPC can ensure stability, there exists a slight steady-state error during the variation input voltage. However, the proposed controller can fulfill the accurate tracking of the reference, and the maximum overshoot during the variation of input voltage is only less than 0.2 V, which will also be mitigated around 1 ms.  Figure 10 shows the comparison between the proposed method and the nominal CCS-MPC under the variation of CVL load, and the change of the CVL is the same as that in Figure 7. As can be observed, the nominal CCS-MPC cannot track the reference accurately during the CVL variation, and the offset is 0.5 V. However, the proposed method regulates the output voltage accurately at 750 V. Figure 11 depicts the comparison between the proposed method and the nominal CCS-MPC, and it can be observed that the proposed method can track the reference voltage without steady-state error, while offset is created by the nominal CCS-MPC.  This section demonstrates a comparison simulation between the proposed controller and an adaptive nonlinear disturbance observer-based passivity-based (PBC + NDO) controller, which is proposed in [29]. In Figure 12, the performance of the proposed method and the PBC + NDO during the variation of input voltage has been depicted. As can be observed, both methods offer good performance.  Figure 13 presents the comparison between the proposed method and the PBC + NDO during the disturbance of CVL variation. As it depicts, not only is the overshoot created by the PBC + NDO larger than the proposed method, but the settling time is also longer. In Figure 14, the dynamic performance of both the PBC + NDO and the proposed controller during the change of CPL is depicted. Likewise, the output voltage of the proposed method has lower overshoot and a faster settling time than the PBC + NDO.

Hardware-in-the-Loop Experiment
In this section, an OPAL-RT-based hardware-in-the-loop (HIL) experimental platform is built and used later for the further HIL experimental verification of the proposed algorithm. The HIL experiment is a common method to further verify the control algorithm; in this system, the circuit model in simulation is modified and embedded into the For the results shown from Figure 6 to Figure 14, we can conclude that the proposed controller not only ensures large signal stability during system disturbances (input voltage and load variation), but it also provides fast recovery performance. However, a very slight static error can be observed in the output voltage of the PBC + NDO during the input voltage variations.

Hardware-in-the-Loop Experiment
In this section, an OPAL-RT-based hardware-in-the-loop (HIL) experimental platform is built and used later for the further HIL experimental verification of the proposed algorithm. The HIL experiment is a common method to further verify the control algorithm; in this system, the circuit model in simulation is modified and embedded into the OPAL-RT devices, while the former controller part of the simulation model is planted into the digital signal processor (DSP). The HIL setup allows for the combination of the MATLAB Simulink model which is embedded into OPAL-RT and DSP works in a real-time mode. The OPAL-RT can act as the circuit to calculate the variable states according to the input control input, while the DSP simply obtains the variable states and offers the PWM signal to the equivalent circuit system according to the proposed algorithm. The diagram of the whole HIL setup mentioned above is depicted in Figure 15. In this setup, the DSP TMS320F28335 is used to control the MATLAB Simulink model which is planted in the OPAL-RT, whereas the OPAL-RT is used to run the MATLAB Simulink model in real time. In this HIL system, the signal of the inductor current i L and capacitor voltage v C are sent to the DSP via the analog output port of the OPAL-RT device. The signal is then transformed from analog to digital form inside the DSP and applied by the proposed algorithm, which produces the controlled PWM signal. This PWM signal is sent back to the Simulink DC-DC buck power converters model through the OPAL-RT digital input port. After the operation of the cyber model, a new set of output states will be sent to the DSP for the next cycle. During the HIL experiment, in order to satisfy the output voltage range limits of the OPAL-RT (±16), the output voltage is subtracted by 750, while the inductor current is also subtracted by 35 A. Since the minimum step size of the OPAL-RT is 10 µs, the switching frequency used in the HIL is set at 10 kHz, and the step size is changed to 10 −5 s.  Figure 16 shows the HIL experimental comparison between the proposed method and the nominal CCS-MPC under the variation of input voltage; during this experiment, the change trend of the input voltage is similar with that shown in Figure 6. As can be observed in Figure 16, the nominal CCS-MPC cannot track the reference voltage, and a static error is produced whose value relates to the variation of the input voltage. However, the proposed method can track the reference tightly, and no offset can be observed during the change of the input voltage. Figure 17 depicts the HIL experimental comparison between the nominal CCS-MPC and the proposed method under the variation of CVL. As depicted in Figure 17, the proposed method can fix its output voltage at 750 only, with some slight overshoots which are quickly mitigated. Meanwhile, the nominal CCS-MPC creates a steady-state error during the CVL changes from its rated value. Figure 18 depicts the HIL experimental comparison between the proposed algorithm and the nominal CCS-MPC during the step variations of CPL. As can be seen from the figure, for the nominal CCS-MPC, the larger the CPL changes, the larger the voltage static error will become. However, the proposed algorithm can realize the accurate tracking of the reference voltage.

Comparison between the Proposed Method and NDO Based PBC
Here, comparisons will be made between the proposed method and the PBC + NDO during the variation of input voltage, CVL, and CPL. In Figure 19, the comparison during the variation of input voltage is conducted. As can be seen from this figure, the proposed method can track the reference voltage accurately without static error; however, the output voltage of the PBC + NDO cannot be regulated at 750 V, and a static error which varies from the change of the input voltage has been produced by it. In Figure 20, the comparison during the variation of the CVL is performed. As can be seen from this figure, although overshoot can be observed for both algorithms in the transient process, the proposed method has advantages in both settling time and the value of overshoot. The last HIL experiment result under the variation of CPL for the proposed method and the PBC + NDO is shown in Figure 21. As can be observed, although the PBC + NDO can fulfill offset-free tracking during the step variations of CPL, the proposed controller has a faster response speed and less overshoot in this comparison.

Conclusions
In this paper, the instability problem caused by disturbances, such as the variation of input voltage, CVL, and CPL, are addressed, and a symmetrical model of the system is created. In order to mitigate the negative impact to the parallel buck converters in the DC microgrid, an adaptive CCS-MPC is developed. In this controller, the CCS-MPC algorithm is combined with a capacitor dynamic-based method to track the reference, whereas a feedforward estimation algorithm is designed to improve its robustness by compensating the disability caused by disturbance. Furthermore, an I-V droop control method is also incorporated to perform the regulation of the voltage and symmetrically equal current sharing. Finally, the MATLAB simulation and HIL experiment are conducted to verify the performance of the proposed method. Furthermore, the proposed controller is compared with previous literature on the MATLAB simulation and HIL experiment. According to the results, the proposed method has better dynamic performance with regard to the previous controllers. However, the CCS-MPC places a large burden on the CPU since it has a high computation requirement. Future research interests will involve the stable control of the boost converter and the simplified CCS-MPC controller.