Efﬁcient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q

: Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.


Introduction
Reversible logic [1,2] is an essential part of building a reversible circuit. A circuit is called reversible if the circuit maps each input to an exclusive output, and the output contains enough information to retrieve the input, i.e., there is a one-to-one consistency among the input/output [3]. Many applications have been proposed for reversible circuits in many technologies [3], e.g., nano-technologies, low-power CMOS [4,5], quantum-dot cellular automata [6,7].
Quantum computers [8][9][10] are constructed of reversible circuits, which have demonstrated capabilities for solving certain problems faster than classical counterparts [11], e.g., Grover presented a quantum algorithm for searching in an unstructured database with quadratic speed-up over classical computers [12]. Shor provided a polynomial-time quantum algorithm for factoring integers into their prime factors [13]. The reversible nature of quantum computers and quantum logic gates [14] demands the need to construct efficient reversible circuits, taking into consideration certain parameters [15], e.g., number of garbage output, quantum cost, number of constant inputs, gate count and delay.
Arithmetic and logic unit (ALU) [16] is an essential part of any computational device. It works as a multi-function circuit capable of performing a predefined set of logical and arithmetic operations. Two of the fundamental functions of ALU are arithmetic addition and subtraction. Several designs have been proposed for full adder and full subtractor reversible circuits. For instance, Thapliyal and Ranganathan proposed a full subtractor using two TRG gates [17]. Gupta et al. introduced an improved construction of full reversible adder/subtractor [18] using three F2G gates and a single MUX gate. Moghimi and Reshadinezhad provided a 4 × 4 full adder and subtractor [19] using one Peres gate and one Fredkin gate with a reduction in cost. Montaser et al. presented a full adder and subtractor design using two R-gate [20]. Definition 1. Given two bits X and Y, a half adder (HA) circuit is a combinational circuit which is capable of performing the arithmetic addition of X and Y [26]. The output of the half adder circuit can be expressed in sum-of-products (SOP) form as follows [26]: where C out is the carry from the arithmetic addition of X and Y, and ⊕ is the exclusive-or (XOR) operation.

Definition 2.
Given three bits X, Y and C in , a full adder (FA) circuit is a compositional circuit that fulfills the arithmetic addition of X, Y and C, where X and Y are the basic inputs, and C in is the carry from the last addition operation of the prior least significant bits [26]. The output of the full adder circuit can be expressed in SOP as follows [26,27]: where C out is the carry from the arithmetic addition of X, Y and C in .
Definition 3. A half subtractor (HS) circuit is a combinational circuit that calculates the arithmetic subtraction of two input bits [26]. For two input bits X and Y, the output of the half subtractor can be expressed in SOP as follows: where Di f f is the difference and B out is the borrow out.

Definition 4.
A full subtractor (FS) circuit is a compositional circuit that fulfills the arithmetic subtraction of three input bits [26]. For three input bits X, Y and B in , the output of the full subtractor can be expressed in SOP as follows:
Definition 7. Given a Boolean function f : {0, 1} n → {0, 1} n , f is called reversible if and only if each input vector v i ∈ {0, 1} n is mapped to one and only one exclusive output f (v i ).

Definition 8.
We say that a gate with n input and n output (n × n) is reversible, if that gate is a realization of a reversible Boolean function.

Definition 9.
Given a set of reversible gates L, we say that L is a library, if L can be used to build reversible circuits [21,22].

Definition 10.
Given a reversible gate library L, we say that L is universal, if L can be used to synthesize any reversible circuit (n × n) [21,22].
Definition 11. Given a (k × k) reversible gate Z acting on (n × n) reversible circuit, the Z gate is denoted as Z n p 1 p 2 ···p k , where the superscript represents the number of bit wires in the reversible circuit and the subscript taking p 1 , p 2 · · · p k−1 as the indices of the control bits and p k as the index of the target bit, as shown in Figure 1.

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Definition 6. The truth table of a Boolean function f that maps an input vector v i ∈ {0, 1} n to {0, 1} n , is defined as the lexicographical order of v i mapped to f (v i ) ∈ {0, 1} n : Definition 7. Given a Boolean function f : {0, 1} n → {0, 1} n , f is called reversible if and only if each input vector v i ∈ {0, 1} n is mapped to one and only one exclusive output f (v i ).

Definition 8.
We say that a gate with n input and n output (n × n) is reversible, if that gate is a realization of a reversible Boolean function.
Definition 9. Given a set of reversible gates L, we say that L is a library, if L can be used to build reversible circuits [21,22].

Definition 10.
Given a reversible gate library L, we say that L is universal, if L can be used to synthesize any reversible circuit (n × n) [21,22].
Definition 11. Given a (k × k) reversible gate Z acting on (n × n) reversible circuit, the Z gate is denoted as Z n p 1 p 2 ···p k , where the superscript represents the number of bit wires in the reversible circuit and the subscript taking p 1 , p 2 · · · p k−1 as the indices of the control bits and p k as the index of the target bit, as shown in Figure 1.
. . p k−1 p k Figure 1. A general representation of a reversible (k × k) gate with controls p 1 , p 2 , · · · , p k−1 control wires and p k target wire.

NOT Gate
The NOT (N) gate is a Boolean (1 × 1) reversible gate that works on a single bit and inverts it unconditionally. It has quantum cost of zero [28]. Figure 2 illustrates all possible variations of N gate working on 3-bit circuit. The effect of the N gate acting on a bit indexed l ∈ A in a circuit of n bits is demonstrated as follows: where ⊕ is the exclusive-or operation (XOR).
x 1 Figure 2. All possible variations of N gate acting on three bits.

Figure 1.
A general representation of a reversible (k × k) gate with controls p 1 , p 2 , · · · , p k−1 control wires and p k target wire.

NOT Gate
The NOT (N) gate is a Boolean (1 × 1) reversible gate that works on a single bit and inverts it unconditionally. It has quantum cost of zero [28]. Figure 2 illustrates all possible variations of N gate working on 3-bit circuit. The effect of the N gate acting on a bit indexed l ∈ A in a circuit of n bits is demonstrated as follows: where ⊕ is the exclusive-or operation (XOR). Definition 6. The truth table of a Boolean function f that maps an input vector v i ∈ {0, 1} n to {0, 1} n , is defined as the lexicographical order of v i mapped to f (v i ) ∈ {0, 1} n : Definition 7. Given a Boolean function f : {0, 1} n → {0, 1} n , f is called reversible if and only if each input vector v i ∈ {0, 1} n is mapped to one and only one exclusive output f (v i ).

Definition 8.
We say that a gate with n input and n output (n × n) is reversible, if that gate is a realization of a reversible Boolean function.
Definition 9. Given a set of reversible gates L, we say that L is a library, if L can be used to build reversible circuits [21,22].

Definition 10.
Given a reversible gate library L, we say that L is universal, if L can be used to synthesize any reversible circuit (n × n) [21,22].
Definition 11. Given a (k × k) reversible gate Z acting on (n × n) reversible circuit, the Z gate is denoted as Z n p 1 p 2 ···p k , where the superscript represents the number of bit wires in the reversible circuit and the subscript taking p 1 , p 2 · · · p k−1 as the indices of the control bits and p k as the index of the target bit, as shown in Figure 1.
. . p k−1 p k Figure 1. A general representation of a reversible (k × k) gate with controls p 1 , p 2 , · · · , p k−1 control wires and p k target wire.

NOT Gate
The NOT (N) gate is a Boolean (1 × 1) reversible gate that works on a single bit and inverts it unconditionally. It has quantum cost of zero [28]. Figure 2 illustrates all possible variations of N gate working on 3-bit circuit. The effect of the N gate acting on a bit indexed l ∈ A in a circuit of n bits is demonstrated as follows: where ⊕ is the exclusive-or operation (XOR).   The Feynman (C) gate is a reversible Boolean (2 × 2) gate (also known as the Controlled-NOT gate) that acts on two input bits and inverts the target bit if and only if the control bit is set to one. The quantum cost of the C gate is one [28]. Figure 3 illustrates the six possible variations of C gate.
The effect of the C gate acting on wires indexed i, j ∈ A is described as follows: , 1, 0 4 of 14

Feynman Gate
The Feynman (C) gate is a reversible Boolean (2 × 2) gate (also known as the Controlled-NOT gate) that acts on two input bits and inverts the target bit if and only if the control bit is set to one. The quantum cost of the C gate is one [28]. Figure 3 illustrates the six possible variations of C gate.
The effect of the C gate acting on wires indexed i, j ∈ A is described as follows: Figure 3. All possible variations of C gate acting on three bits.

Controlled Square-Root NOT Gate
The controlled square-root NOT gate is a reversible (2 × 2) gate that acts on two qubits, and apply the square-root NOT gate on the target bit if and only if the control bit is set to 1. There are two possible gates for the controlled square-root NOT gate: controlled-V(v) and controlled-V † (u) gates. Figure 4 illustrates the possible variations of v and u gates acting on three qubits reversible circuit.
The v and u gates acting on wires indexed g, h ∈ A have the following properties: v n gh · u n gh = u n gh · v n gh = I, u n gh · u n gh = v n gh · v n gh = C n gh , where I represents the identity gate.

Toffoli gate
The Toffoli T gate [29] is a reversible Boolean (3 × 3) gate that takes three input bits and produce an output by flipping the target bit if and only if the control bits are set to one, as illustrated in Figure 5b. The T gate can be decomposed to five (2 × 2) elementary gates [30,31], as illustrated in Figure 5b, and thus it has a quantum cost of five. The action of the T gate acting on wires indexed r, s, t ∈ A is described as follows:

Controlled Square-Root NOT Gate
The controlled square-root NOT gate is a reversible (2 × 2) gate that acts on two qubits, and apply the square-root NOT gate on the target bit if and only if the control bit is set to 1. There are two possible gates for the controlled square-root NOT gate: controlled-V(v) and controlled-V † (u) gates. Figure 4 illustrates the possible variations of v and u gates acting on three qubits reversible circuit.
The v and u gates acting on wires indexed g, h ∈ A have the following properties: v n gh · u n gh = u n gh · v n gh = I, u n gh · u n gh = v n gh · v n gh = C n gh , where I represents the identity gate.

Feynman Gate
The Feynman (C) gate is a reversible Boolean (2 × 2) gate (also known as the Cont NOT gate) that acts on two input bits and inverts the target bit if and only if the cont is set to one. The quantum cost of the C gate is one [28]. Figure 3 illustrates the six po variations of C gate.
The effect of the C gate acting on wires indexed i, j ∈ A is described as follows Figure 3. All possible variations of C gate acting on three bits.

Controlled Square-Root NOT Gate
The controlled square-root NOT gate is a reversible (2 × 2) gate that acts on two q and apply the square-root NOT gate on the target bit if and only if the control bit is s There are two possible gates for the controlled square-root NOT gate: controlled-V(v controlled-V † (u) gates. Figure 4 illustrates the possible variations of v and u gates on three qubits reversible circuit.
The v and u gates acting on wires indexed g, h ∈ A have the following propert v n gh · u n gh = u n gh · v n gh = I, u n gh · u n gh = v n gh · v n gh = C n gh , where I represents the identity gate.

Toffoli gate
The Toffoli T gate [29] is a reversible Boolean (3 × 3) gate that takes three inpu and produce an output by flipping the target bit if and only if the control bits are one, as illustrated in Figure 5b. The T gate can be decomposed to five (2 × 2) eleme gates [30,31], as illustrated in Figure 5b, and thus it has a quantum cost of five. The of the T gate acting on wires indexed r, s, t ∈ A is described as follows:

Toffoli Gate
The Toffoli T gate [29] is a reversible Boolean (3 × 3) gate that takes three input bits and produce an output by flipping the target bit if and only if the control bits are set to one, as illustrated in Figure 5b. The T gate can be decomposed to five (2 × 2) elementary gates [30,31], as illustrated in Figure 5b, and thus it has a quantum cost of five. The action of the T gate acting on wires indexed r, s, t ∈ A is described as follows: Symmetry 2021, 13, 1842 5 of 14 21 submitted to Symmetry 5 of 14 Figure 5. The T 3 gate where: 5a all possible variations of T gate acting on three circuit, 5b the T 123 decomposition into five elementary gates.
The T gate can be generalized to work in a circuit of n bits as a (k × k) gate, taking 97 k-inputs and producing k-outputs flipping the target bit if and only if the k − 1 control 98 bits are set to 1. The T gate acting on wires indexed p 1 , p 2 · · · p k−1 , p k ∈ A can be shown 99 as follows: where ∏ k−1 q=1 x p q is a product term of k − 1 variables.
The G n gate library was introduced by Younes [21]. It is a reversible universal 103 gate library that can be used to synthesize any reversible circuit with n-input/output 104 variables, for n ≥ 2. The G n associates N n gate, C n gate and the T n gate to build a library 105 that acts on n-bits circuits. Figure 6 illustrates the G 3 library in a circuit of three bits. The 106 action of the G gate acting on three bits indexed a, b, c ∈ A in a circuit of n = 3 wires can 107 be described as follows: (a) 5 of 14 The T gate can be generalized to work in a circuit of n bits as a (k × k) gate, taking k-inputs and producing k-outputs flipping the target bit if and only if the k − 1 control bits are set to 1. The T gate acting on wires indexed p 1 , p 2 · · · p k−1 , p k ∈ A can be shown as follows: where ∏ k−1 q=1 x p q is a product term of k − 1 variables.

G Gate
The G n gate library was introduced by Younes [21]. It is a reversible universal gate library that can be used to synthesize any reversible circuit with n-input/output variables, for n ≥ 2. The G n associates N n gate, C n gate and the T n gate to build a library that acts on n-bits circuits. Figure 6 illustrates the G 3 library in a circuit of three bits. The action of the G gate acting on three bits indexed a, b, c ∈ A in a circuit of n = 3 wires can be described as follows: The T gate can be generalized to work in a circuit of n bits as a (k × k) gate, taking k-inputs and producing k-outputs flipping the target bit if and only if the k − 1 control bits are set to 1. The T gate acting on wires indexed p 1 , p 2 · · · p k−1 , p k ∈ A can be shown as follows: where ∏ k−1 q=1 x p q is a product term of k − 1 variables.

G Gate
The G n gate library was introduced by Younes [21]. It is a reversible universal gate library that can be used to synthesize any reversible circuit with n-input/output variables, for n ≥ 2. The G n associates N n gate, C n gate and the T n gate to build a library that acts on n-bits circuits. Figure 6 illustrates the G 3 library in a circuit of three bits. The action of the G gate acting on three bits indexed a, b, c ∈ A in a circuit of n = 3 wires can be described as follows: The T gate can be generalized to work in a circuit of n bits as a (k × k) gate, taking k-inputs and producing k-outputs flipping the target bit if and only if the k − 1 control bits are set to 1. The T gate acting on wires indexed p 1 , p 2 · · · p k−1 , p k ∈ A can be shown as follows: where ∏ k−1 q=1 x p q is a product term of k − 1 variables.

G Gate
The G n gate library was introduced by Younes [21]. It is a reversible universal gate library that can be used to synthesize any reversible circuit with n-input/output variables, for n ≥ 2. The G n associates N n gate, C n gate and the T n gate to build a library that acts on n-bits circuits. Figure 6 illustrates the G 3 library in a circuit of three bits. The action of the G gate acting on three bits indexed a, b, c ∈ A in a circuit of n = 3 wires can be described as follows:  Figure 6. The gate representation of G 3 gates for a 3-bit reversible circuit [21]. Definition 12. A garbage output [15] is any meaningless output of a reversible quantum circuit.
Definition 13. Given a reversible quantum circuit, the quantum cost (QC) [15] is defined as the number of elementary quantum gates used to construct this circuit.

Definition 14.
Gate count (GC) [15] of a reversible quantum circuit is the number of quantum gates used to construct this circuit.
Definition 15. Given a reversible quantum circuit, a constant input (CI) [15] is an input bit that is set with a constant input value, and it is used to compute a certain Boolean function.

Definition 16.
Given a logic circuit, the amount of time for a signal to circulate from the input to output is called delay [26].
It is known that the delay in reversible quantum circuits is dependent on the technologies invested in producing those circuits, and it can be explicitly determined when the technologies used in production is determined [15].
The method introduced in [15] for calculating the delay in quantum circuits is defined as follows: 1.

3.
Find the path from input to output which has the maximum delay; this is considered the unit delay ∆ of the circuit.

The Proposed Designs
In this section, we introduce the proposed designs for the reversible HA/HS circuits and the reversible FA/FS circuits.

The Proposed Reversible Half Adder/Subtractor Circuits
We construct our proposed HA/HS using a single G 3 123 gate, as shown in Figure 7a. The proposed design is a 3 × 3 circuit, where x 3 is the control bit. Setting x 1 = X, x 2 = Y and x 3 = 0, the proposed design will work as a HA such that the bit y 2 will output Sum, and y 3 will output C out ; the y 1 bit will produce X which is the negation (NOT) operation. Setting x 1 = X and x 2 = x 3 = Y, the proposed design will work as a HS, where the bit y 2 will output Diff and the bit y 3 will output B out ; the bit y 1 will perform the NOT operation on X. Figure 7b shows the Toffoli decomposition for the proposed HA/HS. Figure 7c illustrates the equivalent decomposition using five elementary gates, where QC equals to four, and the delay equals to three. Table 1 summarizes the possible operations that the proposed HA/HS is able to perform.

The Proposed Reversible Full Adder Circuit
Using two G 3 gates, we are able to construct a FA circuit capable of performing the addition operation. We use both G 3 132 and G 3 231 cascaded as illustrated in Figure 8a. Setting x 2 = 0 as a constant bit and considering x 1 , x 2 and x 4 as X, Y and C in respectively, the proposed FA will calculate the addition operation where the y 2 bit will output the Sum and y 4 bit will output the C out ; in addition, y 1 will output X, and y 3 will output X ⊕ Y which is the exclusive-NOR (XNOR) operation. It is clear that the proposed FA does not produce any garbage output and has only one constant bit. By changing the values of x 2 and x 4 , the proposed FA can perform additional logical operations on x 1 and x 3 such as NOT, AND, exclusive-or (XOR), OR, NOR and N AND, also with no garbage output. Table 2 summarizes the possible operations that the proposed FA is able to perform. Figure 8b illustrates the equivalent decomposition for the proposed FA circuit into its Toffoli decomposition. Using the rules of optimization defined in [30] and a Toffoli decomposition technique in [31], the number of elementary gates used to build the proposed FA can be reduced from 14 gates to eight gates, as shown in Figure 8c. Figure 8d shows the optimized decomposition of the proposed FA into eight elementary gates, with a QC equals to six (using cost01 metric) and a delay equals to 4∆.  The possible functions that can be performed using the proposed design Section 3.1.

The Proposed Reversible Full Adder Circuit
Using two G 3 gates, we are able to construct a FA circuit capable of performing the addition operation. We use both G 3 132 and G 3 231 cascaded as illustrated in Figure 8a. Setting x 2 = 0 as a constant bit and considering x 1 , x 2 and x 4 as X, Y and C in respectively, the proposed FA will calculate the addition operation where the y 2 bit will output the Sum and y 4 bit will output the C out ; in addition, y 1 will output X, and y 3 will output X ⊕ Y which is the exclusive-NOR (XNOR) operation. It is clear that the proposed FA does not produce any garbage output and has only one constant bit. By changing the values of x 2 and x 4 , the proposed FA can perform additional logical operations on x 1 and x 3 such as NOT, AND, exclusive-or (XOR), OR, NOR and N AND, also with no garbage output. Table 2 summarizes the possible operations that the proposed FA is able to perform. Figure 8b illustrates the equivalent decomposition for the proposed FA circuit into its Toffoli decomposition. Using the rules of optimization defined in [30] and a Toffoli decomposition technique in [31], the number of elementary gates used to build the proposed FA can be reduced from 14 gates to eight gates, as shown in Figure 8c. Figure 8d shows the optimized decomposition of the proposed FA into eight elementary gates, with a QC equals to six (using cost01 metric) and a delay equals to 4∆.  Figure 8. (a) The proposed design of the FA using the G 3 library, (b) the Toffoli decomposition of the proposed FA design, (c) decomposes the proposed design FA into its 14 elementary gates, and (d) the optimized decomposition of the proposed FA into eight basic gates with a total QC equals to six.

The Proposed Reversible Full Subtractor Circuit
We are able to build a FS that is capable of performing the binary subtraction operation, using two G 3 gates. The proposed FS uses G 3 132 and G 3 231 in addition to two NOT gates, as illustrated by Figure 9a. Setting x 2 = x 3 = Y, and considering x 1 and x 4 as X and B in , respectively, the proposed FS will perform the binary subtraction operation and the y 2 bit will output Di f f and the y 4 bit will output B out ; in addition, y 1 outputs the result of applying the NOT operation on X and y 3 performs the XOR operation X ⊕ Y. It is clear that the proposed FS has no constant inputs and no garbage as well. Table 2 summarizes the possible operations that the proposed FS is capable of.
The proposed FS can be further optimized by replacing the T 3 gates with a suitable decomposition, as illustrated in Figure 9b. It is evident that the proposed FA design has a QC of eight and a 7∆ delay.

The Proposed Reversible Full Subtractor Circuit
We are able to build a FS that is capable of performing the binary subtraction operation, using two G 3 gates. The proposed FS uses G 3 132 and G 3 231 in addition to two NOT gates, as illustrated by Figure 9a. Setting x 2 = x 3 = Y, and considering x 1 and x 4 as X and B in , respectively, the proposed FS will perform the binary subtraction operation and the y 2 bit will output Di f f and the y 4 bit will output B out ; in addition, y 1 outputs the result of applying the NOT operation on X and y 3 performs the XOR operation X ⊕ Y. It is clear that the proposed FS has no constant inputs and no garbage as well. Table 2 summarizes the possible operations that the proposed FS is capable of.
The proposed FS can be further optimized by replacing the T 3 gates with a suitable decomposition, as illustrated in Figure 9b. It is evident that the proposed FA design has a QC of eight and a 7∆ delay. y 2021, 1, 0 9 of 14 Figure 9. (a) The proposed design of the FS using the G 3 library, and (b) the optimized decomposition of the proposed FA into 12 basic gates with a total QC equals to eight. Table 2. The possible Boolean operations that can be performed using the proposed designs 3.2 , 3.3 by changing the input bits x 2 , x 3 and x 4 .

Experimental Results and Discussion
In this section, the experiments on IBM Q [24] using Qiskit Python SDK [25] are presented for the proposed designs. Each design is tested 8192 times. In addition, we discuss and compare the results obtained by proposed designs with other results in the relevant work. The main criteria of comparison are QC, GO, CI, GC, and circuit delay. Figure 10 shows the actual sequence of gates that are used to implement the proposed designs on IBM Q [24]. This involves Hadamard gate (denoted H), π/4 gate (denoted T), complex conjugate transpose of T (denoted T † ), rotation gate with three Euler angles (denoted U 3 ), and controlled-not gate. All the proposed designs are tested on IBM Q [24] using Qiskit Python SDK [25], each design is tested 8192 times. The success probability is the probability of obtaining the desired output for a given function over all trials. In the presented work, the maximum number of trials permitted by IBM Q 5 Santiago backend specification [24] is 8192 trials and this is the number of trials we used. The average success probability for each proposed design is calculated. Table 3 shows the truth table for the proposed HA, and illustrates the probability of obtaining the correct output after executing on IBM Q [24], with a maximum success probability 0.8829 and an average success probability 0.8259. Further more, Table 4 shows the truth table of the proposed HS, and illustrates the probability of obtaining the correct output after executing on IBM Q with a maximum success probability 0.7545 and an average success probability 0.7456.

Experimental Results and Discussion
In this section, the experiments on IBM Q [24] using Qiskit Python SDK [25] are presented for the proposed designs. Each design is tested 8192 times. In addition, we discuss and compare the results obtained by proposed designs with other results in the relevant work. The main criteria of comparison are QC, GO, CI, GC, and circuit delay.
Executing the Proposed Designs on IBM Q Figure 10 shows the actual sequence of gates that are used to implement the proposed designs on IBM Q [24]. This involves Hadamard gate (denoted H), π/4 gate (denoted T), complex conjugate transpose of T (denoted T † ), rotation gate with three Euler angles (denoted U 3 ), and controlled-not gate. All the proposed designs are tested on IBM Q [24] using Qiskit Python SDK [25], each design is tested 8192 times. The success probability is the probability of obtaining the desired output for a given function over all trials. In the presented work, the maximum number of trials permitted by IBM Q 5 Santiago backend specification [24] is 8192 trials and this is the number of trials we used. The average success probability for each proposed design is calculated. Table 3 shows the truth table for the proposed HA, and illustrates the probability of obtaining the correct output after executing on IBM Q [24], with a maximum success probability 0.8829 and an average success probability 0.8259. Further more, Table 4 shows the truth table of the proposed HS, and illustrates the probability of obtaining the correct output after executing on IBM Q with a maximum success probability 0.7545 and an average success probability 0.7456.    Table 5 shows the truth table of the addition operation for the proposed FA. In addition, it illustrates the success probability of finding the desired output after running the proposed FA on IBM Q [24], with a maximum success probability 0.7703 and an average success probability 0.6935. Figure 10b illustrates the proposed FA circuit implementation using Qiskit Python SDK [25]. The proposed FS is tested on IBM Q [24]. For each possible input, the desired output is produced with certain success probability, as depicted in Table 6. The proposed FS circuit implementation using Qiskit Python SDK [25] is depicted in Figure 10c, with a maximum success probability 0.76 and an average success probability 0.6829.  Table 7 studies the proposed FA and the proposed FS, and compares them with relevant work [18][19][20][35][36][37][38][39][40]. It shows that the proposed FA has no garbage output and QC of six, which is the best among the designs in the comparison. In addition, the proposed FA design has CI of one, which is similar to [20,35,37,39], and GC of two similar to [18,20,35]. The delay of the proposed FA design has the smallest delay among the relevant work that considered circuit delay as a metric. Overall, the proposed FA design functions with better results when it is compared to relevant work.
In addition, Table 7 describes the proposed FS design in terms of known metrics and compares it to relevant work [17][18][19][20]36,37,40]. Table 7 shows that the proposed FS design has no GO and no CI which is the best results obtained when comparing it to relevant work. Additionally, the proposed FS design shows QC of eight and delay of seven which are high when it is compared to the FS design in [17], but the FS design in [17] did not consider other metrics such as GO, CI or GC. Overall, the proposed FS design shows better results when it is compared to relevant designs.

Conclusions
In this paper, we proposed an efficient designs of reversible half and full addition and subtraction circuits. The addition and subtraction operations are the basic operations in the ALUs, since the multiplication and division operations can be obtained using repeated addition and subtraction. The proposed designs are based on a universal single type library G which can be used to construct cheap reversible circuits using similar building blocks. The proposed full adder and full subtractor are built using two G gates, which works as a 1-bit ALU and can also be extended to work on any number of bits using multiplexers. The presented designs are multi-function circuits which are capable of performing additional logical operations: AND, OR, NOT, XOR, XNOR, NOR and NAND. These logical gates are sufficient to construct classical universal libraries, e.g., {AND, OR, NOT}. The proposed designs show reduction in quantum cost, gate count, constant input, and delay with zero garbage output, when they are compared to relevant work in the literature.
The experimental results show the efficiency of the proposed designs when they are implemented and tested on IBM Q to measure the success probability of obtaining the correct results. It is shown that the average success probability of the half adder is 0.8259 with a maximum success probability 0.8239. The average success probability of the half subtractor is 0.7456 with a maximum success probability 0.7545. In addition, the average success probability for the full adder is 0.6935, with a maximum success probability 0.7703. Finally, the full subtractor illustrates 0.6829 average success probability with a maximum success probability of 0.76. An effort is required to improve the average success probability of the proposed designs on different quantum computer architectures. Further effort is required to expand the proposed design to its elemental gates and provide optimization techniques to reduce the gate count and improve the efficiency of the designs.