Two New Asymmetric Boolean Chaos Oscillators with No Dependence on Incommensurate Time-Delays and Their Circuit Implementation

: This manuscript introduces two new chaotic oscillators based on autonomous Boolean networks (ABN), preserving asymmetrical logic functions. That means that the ABNs require a combination of XOR-XNOR logic functions. We demonstrate analytically that the two ABNs do not have ﬁxed points, and therefore, can evolve to Boolean chaos. Using the Lyapunov exponent’s method, we also prove the chaotic behavior, generated by the proposed chaotic oscillators, is insensitive to incommensurate time-delays paths. As a result, they can be implemented using distinct electronic circuits. More speciﬁcally, logic-gates–, GAL–, and FPGA–based implementations verify the theoretical ﬁndings. An integrated circuit using a CMOS 180nm fabrication technology is also presented to get a compact chaos oscillator with relatively high-frequency. Dynamical behaviors of those implementations are analyzed using time-series, time-lag embedded attractors, frequency spectra, Poincaré maps, and Lyapunov exponents.

A remarkable solution to obtain chaotic behavior consists of exploiting the delay paths in autonomous Boolean networks (ABNs) [30][31][32][33][34]. Kauffman proposed the Boolean networks in 1969 as a mathematical framework for studying gene regulatory networks. The mathematics describing ABNs has shown that they could display aperiodic patterns if the Boolean functions have instantaneous response times, the link time-delays are incommensurate, and their nodes perform asymmetric Boolean operations, such as the combination of logic exclusive-OR (XOR) and XNOR functions.
In the context of ABNs, deterministic chaos, also known as Boolean chaos, was initially demonstrated by using Boolean functions implemented with electronic logic circuits (logic gates and field-programmable gate arrays FPGAs) [10,[35][36][37][38]. At circuit level, the basic principle for obtaining Boolean chaos depends on three main characteristics; the asymmetry between the logic states, the short-pulse rejection phenomenon, and, most importantly, the degradation effect [30,31].
As is well-known, the incommensurate delay between two different nodes of an ABN is the critical parameter to obtain chaotic behaviors since it induces the degradation effect [30][31][32][33][34]. Rosin et al. analyzed two ABNs, one composed of a logic XOR function and two delays τ n k and τ n l , and the other one with a logic XNOR function and three delays τ n k , τ n l , and τ n m [38]. They showed that Boolean chaos arises in an FPGA-based implementation when the delays for each of the three delay paths are τ n k ≥ 2.8 ns, τ n l ≥ 1.7 ns, and τ n m ≥ 0.56 ns, respectively. To attain the time-delays, they required 18 extra logic NOT gates to connect the nodes of ABN. Besides, if those time-delays reduce below the minimum, the ABN does not show chaos and evolves to periodic oscillations only, as was analyzed in Ref. [35]. Park et al. presented an ABN composed of a logic XOR gate and ring oscillator [39]. The proposed logic circuit synthesized on an application-specific IC (ASIC), but the design is not straightforward because it also demands specific incommensurate delays in the feedback path to observe Boolean chaos.
Based on the discussion mentioned above, we note a possible benefit of using ABNs can be to get Boolean chaos oscillators with relatively high oscillation frequencies and small form factors since they depend on logic functions only. However, we also found that the proposed ABNs have high sensitivity to the time-delay among network nodes for generating chaos behavior. From a practical point of view, that condition is very complicated to satisfy since the time-delays are heavily related to the electronics technology chosen for implementation. Due to the electronic logic gates being heterogeneous, they do not have the same intrinsic time-delay. As a consequence, the dynamical behaviors of the ABN can be affected by placing the oscillator on a different area into an integrated circuit or FPGA. In conclusion, the previously reported Boolean chaos oscillators may not be suitable for physical realizations with multiple hardware approaches.
In this paper, we propose two ABNs with three and two nodes, respectively. The nodes perform the logic XOR and XNOR operations. This asymmetric approach avoids fixed points in the ABNs, and therefore, their dynamics can converge to chaotic oscillations. By applying the Lyapunov exponent method, we experimentally demonstrate that the Boolean chaos oscillators do not require specific incommensurate time-delays to show chaotic behaviors. Indeed, the Boolean chaos was observed under a wide range of the time-delays for the ABNs nodes. We prove our findings by implementing the proposed ABNs using various logic electronic circuits without any modification neither of the proposed networks nor adding additional path delays. Three discrete physical realizations using commercial logic gates, a Generic Array Logic (GAL), and FPGA are presented. Besides, we design an integrated circuit realization at 180nm fabrication technology.
The structure of the manuscript is as follows. Section 2 introduces the two ABNs and gives the mathematical demonstrations of their equilibrium points. Section 3 shows the analysis based on the Lyapunov exponents to determine the insensibility to time-delays. Section 4 presents the Lyapunov exponents for three different discrete implementations to prove that the ABNs are not affected by the technology. Section 5 introduces a straightforward methodology to design an integrated circuit of the Boolean chaos oscillators. Time-series, phase space reconstruction, Lyapunov exponents, and Poincare maps validate the observed chaos behavior. Finally, the last section concludes the paper.

Mathematical Preliminaries
A Boolean network consists of a number of logical nodes interconnected through direct or indirect links. These are nonlinear networks requiring a mathematical base for analysis. Among the present models there are: the Kauffman (N-K) networks, Boolean differential equations, and piecewise-linear differential equations [33,34]. This work uses the Boolean differential equations to develop important mathematical considerations.

Boolean Differential Equations
Let us consider a system with state variables {v 1 , v 2 , . . . , v n }, v i ∈ R, i = 1, . . . , n. If a Boolean variable x i is related to each state v i , depending on a set of thresholds σ i ∈ R. Then, the set of Boolean variables x = {x 1 , x 2 , . . . , x n } gives a simple qualitative description of the system with 2 n possible states. By adding the time dependence through a set of delays {τ ij }, i = 1, . . . , n, j = 1, . . . , n, τ ij > 0, where τ ij is the time it takes for x j to affect x i , there is an associated time delay for each pair of state variables not necessarily obeying τ ij = τ ji . In this manner, the feedbacks among the Boolean variables can be described by a system of Boolean differential equations as follows [33,34]:  [33,34]. The dynamics of the ABN given by Equation (1) is numerically solved once the Boolean functions are defined with initial conditions on an interval . . , n, where τ = max{τ ij } is the memory length of the system.

Boolean Chaos
In an ideal ABN, the transitions of the signals are arbitrarily fast and the number of transitions increases with time, following a power law. These increasingly fast dynamics result in an unlimited growth of frequency over time, referred to as an ultraviolet catastrophe [30]. However, that phenomenon does not occur in nature because the information-transmitting links and the processing nodes (for instance real logic gates) have a maximum operation frequency, which are physically realized. Hence, they cannot transmit or generate signals above a certain frequency [31]. As a result, the nonideal behaviors of real logic devices are responsible for the origin of chaos in ABNs [30,31]. Those behaviors are (i) Short-pulse rejection (SPR), known as pulse filtering, preventing pulses shorter than a minimum duration from passing through the gate (Theorem 1). (ii) The asymmetry between the logic states, making the propagation delay time through the gate depending on whether the transition is a fall or rise. (iii) The degradation effect triggering a change in the events propagation delay time when they appear in rapid succession. Among them, the degradation effect is the main nonideal behavior source of deterministic chaos in an ABN [32], since Boolean chaos originates from a history-dependent delay [30,31], as defined Lemma 1.

Theorem 1.
For a symmetric ABN consisting of a single XOR logic operation with two self-inputs having delays τ 1 and τ 1 , and with τ spr sufficiently small not collapsing to the always-off state occurs before t = τ 2 , the trajectory will never reach the always-off state. On the other hand, if the ABN has equal delays, the links will produce only regular oscillations. In addition, the fixed points caused by using only symmetric logic functions in the network nodes conduct that the dynamics will always collapse into a low or high logic state, respectively. Theorem 2 and Lemma 2 postulates the conditions. As a reference, the complete proofs of Theorems and Lemmas can be found in [31,35].
Theorem 2. For a symmetric ABN consisting of a single exclusive-OR (XOR) logic operation with two self-inputs having delays τ 1 and τ 2 , the attractors are always periodic.

Lemma 2.
The experimentally realized ABNs should not include a Boolean fixed point, for which all Boolean functions are satisfied simultaneously.

Lyapunov Exponents for ABNs
One of the most reliable tools to demonstrate chaotic behavior is computing the Lyapunov exponent's spectrum . A positive Lyapunov exponent is a signature of chaos [40]. It is defined as the exponential divergence of trajectories with nearly identical initial conditions. For the ABNs case, since the states are discrete, indicating a phase space composed just by 2 N states, the Lyapunov exponent's needs to be computed from distance measures tailored for Boolean systems [41].
Zhang et al. proposed a method to estimate the largest Lyapunov exponent using the Boolean distance definition [30]. The approach works as follows. (i) Acquire experimentally a long time series from an output voltage of the ABN. (ii) Convert that voltage to a Boolean variable x(t). (iii) Given any two segments of starting at times t a and t b , define a Boolean distance with d(s) = 1 T s+T s where T is a fixed parameter, ⊕ is the XOR logic operation, and the Boolean distance d(s) evolves as a function of the time s. (iv) Search in x(t) for all the pairs t a and t b corresponding to the earliest times in each interval T over which As a conclusion, the divergence ln d(s) increases exponentially, as expected for an adequate definition of distance between trajectories in a chaotic system [40].

The Proposed Boolean Chaos Oscillators (BCOs) and Their Fixed Points
Motivated by Ref. [30], this work introduces two ABNs composed by three and two nodes, respectively. The nodes of ABNs perform asymmetric logic functions, i.e., a combination of Boolean operations XOR and XNOR. We detail the proposed ABNs as follows. Figure 1a shows the first Boolean chaos oscillator (BCO). It consists of three nodes where each node has three inputs and one output that propagates to three different nodes. Nodes A and B perform the XOR logic operation while node C executes the XNOR. Expressing BCO-1 in the form of Equation (1), we obtain the following system of Boolean delay equations:

BCO-1
with Boolean functions f i : B 3 → B, i = 1, . . . , 3, and ⊕ the logic XOR operation. The signal propagation time from node j to node i is τ ij for i, j = a, b, c. Theorem 3. For an autonomous Boolean network given by the system of Equation (2), the orbits are always oscillating [36].

Proof.
A Boolean fixed point provokes nonoscillating dynamics due to some orbits eventually collapsing into the fixed point. To demonstrate the proposed Boolean chaos oscillator converges to sustained oscillations indefinitely, we must prove that there is not a fixed point. By contradiction, we demonstrate this theorem. Let us assume that the BCO-1 has a fixed point (X * a , X * b , X * c ), such that: for t >> τ = max{τ aa , τ ab , τ ac , τ ba , τ bb , τ bc , τ ca , τ cb , τ cc }. In this manner, the system of Equation (2) recast as: By substituting Equations (3) and (4) into (5), we obtain: Equation (6) implies X c (t) = X c (t). Since the Boolean space is 2 n , the possible states for X c (t) are {1, 0}. Thus, "1" = "0", or vice-versa indicates a contradiction which leads us to conclude that Boolean network (2) does not have fixed points, and therefore, always oscillates. Figure 2a shows the second Boolean chaos oscillator introduced in this work. The proposed topology consists of two nodes, where each node has three inputs and one output connecting to two different nodes. While node A performs the XOR logic operation, node B executes the XNOR. Additionally, the ABN includes two logic NOT operations to obtain the opposed Boolean states for both nodes. The set of Boolean delay equations for the BCO-2 are:

BCO-2
with ⊕ and ¬ indicating the logic XOR and NOT operations, respectively. In addition, the Boolean Similarly to the previous case, it is necessary to prove that the system (7)   Theorem 4. For an autonomous Boolean network given by the system of Equation (7), the orbits are always oscillating [36].
Proof. We assume that the BCO-2 has the fixed point (X * a , X * b ), such that X * a = X a (t − τ) and X * b = X b (t − τ), for t >> τ = max{τ aa , τ ab , τ aã , τ ba , τ bb , τ bb }. Therefore, system (7) is rewritten as: By inserting Equation (8) into (9), we obtain: Equation (10) means X b (t) = X b (t). This again implies a contradiction and it is possible to claim that the autonomous Boolean network (7) does not have a fixed point and it will oscillate permanently.

Boolean Sensitivity Caused by Asymmetric Logic Functions
As demonstrated in the previous subsection, the presented BCOs do not have fixed points. In this manner, when an autonomous Boolean network is realized experimentally it should include asymmetric Boolean functions to achieve chaotic dynamics [31,35]. As a result, the preference for using logic XOR and XNOR functions in the proposed BCOs lies on the look-up table for these logic operations. Firstly, the idea is considering an equal number of "1"s and "0"s as the output of the XNOR operation to avoid converging into a physical Boolean fixed-point, i.e., where all entries of the look-up table have the same value, and hence inputs and outputs can be the same. From the look-up tables in Figures 1b and 2b, the outputs are different for all inputs, including the cases "000" and "111". On the other hand, since the number of "0"s and "1"s in the look-up tables is equal, the proposed BCOs can have a higher Boolean sensitivity E = 2Kρ(1 − ρ) [30,35]. This is possible with randomly chosen Boolean functions of bias ρ = 0.5 (equal number of zeros and ones) and high in-degree K (the number of input connections to a node) or most effectively by using XOR and XNOR Boolean functions as herein.

Boolean Chaos Robust to Different Incommensurate Time-Delays
The chaos-based applications demand the exploration of different typologies and implementations to find those that are the most suitable. In addition, the chaotic behavior must be robust. It means that the chaos should be generated consistently for a wide range of parameter values. In the ongoing literature, the reported autonomous Boolean networks only show chaos in certain ranges of the feedback delays [10,30,31,[35][36][37][38][39], as was discussed in the Introduction section. At the experimental level, those approaches incorporate an even number of logic NOT gates in the link to act as a time-delay buffer to add extra signal propagation times. Then, the published works need several pairs of NOT gates to satisfy the specific incommensurate time-delays for each one of their links connecting nodes. Otherwise, the chaotic behavior converges to either periodic oscillations or stable dynamics in the Boolean levels high or low.
Conversely, the proposed BCOs in Figures 1 and 2 do not require additional logic NOT gates to generate chaotic oscillations. This means that the chaos behavior depends solely on the incommensurate time-delays, arising only from the intrinsic delay associated with each XOR and XNOR gate. In this manner, we state the following Lemma and Corollary.  Proof. To demonstrate Lemma 3 and Corollary 1, we show the physical implementation of the BCOs in Figures 1 and 2 using commercial off-the-shelf logic gates (74HCXXX family), as shown in Figure 3a. The discrete implementation makes it possible to change the time-delay between feedback nodes easily. Then, we study the dynamics of the proposed BCOs using the Lyapunov exponent method.
The scenario is as follows. First, we consider different cases for the incommensurate time-delays of the links. Those time-delays were realized using a pair of two NOT gates wired in series. Thus, from the experimental output signal of nodes C (BCO-1) and B (BCO-2) for each case in Tables 1 and 2, respectively, we collect a long enough time series. For instance, the BCO-1 output signal of node C for cases 1, 3, and 7 is given in Figure 4a,d,g, respectively. On the other hand, Figure 5a,d present the results for the output signal of node B of BCO-2 for cases 1 and 5, respectively.
Next, we compute the largest Lyapunov exponent, λ max , applying the Boolean distance algorithm introduced in Section 2.3. The results in Tables 1 and 2 shows the largest Lyapunov exponent, λ max , is positive for all cases indicating the proposed BCOs generate robust Boolean chaos. Besides, the chaotic behavior was also verified in the BCOs (both cases 1 in Tables 1 and 2, respectively), without extra time-delays with exception from those incommensurate intrinsic delays of the logic XOR and XNOR gates, i.e., the BCO-1 and BCO-2 do not include any logic NOT gates in the feedback paths.    Table 1 with (a) logic gates 74HCXXX, (b) GAL22V10, and (c) FPGA Spartan6. Case 3 in Table 1 Table 2 with (a) logic gates 74HCXXX, (b) GAL22V10, and (c) FPGA Spartan6. Case 5 in Table 2 with (d) logic gates 74HCXXX, (e) GAL22V10, and (f) FPGA Spartan6. Tables 1 and 2 suggest the most suitable case for obtaining Boolean chaos is when no other delay paths are incorporated in the links because the higher the time-delays, the lower the magnitude of the largest Lyapunov exponent. From the physical implementation point of view, that is a remarkable feature because we can get a small form factor with the proposed Boolean chaos oscillators. Moreover, since the chaos generation does not depend on determined time-delays, the proposed BCOs can be implemented with several hardware technologies, as demonstrated in the next subsection. Table 1. Largest Lyapunov exponent (λ max ) of the BCO in Figure 1 for different time-delays in the feedback paths. The symbol "-" means no extra time-delay, while " √ " refers to a time-delay composed of two logic NOT gates.

Case
Time-Delay Lyapunov Exponent τ aa τ ab τ ac τ ba τ bb τ bc τ ca τ cb τ cc λ max Table 2. Lyapunov exponent of BCO in Figure 2 for different time-delays in the feedback paths.

Boolean Chaos Robust to Distinct Discrete Physical Implementation
This subsection presents three different physical implementations of the Boolean chaos oscillators. The dynamics are affected by physical constraints and hardware differences. This may lead to time-delay variations where the boolean chaos displays. Therefore, the BCO-1 and BCO-2 are constructed with three different electronic devices (i) commercial-off-the-shelf logic gates (introduced previously), (ii) a GAL, and (iii) an FPGA. The experiments in Figure 3 demonstrate the robust generation of Boolean chaos. From the circuit conception, the implementations show the chaotic behavior source is the degradation effect [32]. In addition, there are no additional procedures to calculate the delay paths to achieve chaotic oscillations.
The implementation considers all cases of Tables 1 and 2, but for the sake of simplicity, the Table 3 displays only the examples where the largest Lyapunov exponent is higher. In particular, case 1 for both BCOs is of particular interest because they do not need extra time-delays for generating chaos. More specifically, we use the GAL22V10 for realizing both BCOs, as given in Figure 3b. The programming of the GAL was performed with VHDL language. Figure 4b Figure 4c,f,i for cases 1, 3, 7 in Table 1, respectively. Figure 5c,f display the output signal for cases 1 and 5 in Table 2, respectively.
The measurements exhibit a 100 ns of time and a 2V of voltage grid per square. For all the three presented implementations, the output voltages (Figures 4 and 5) show the cumbersome temporal oscillations without evident periodicity. This continuous-time evolution can be identified as Boolean chaos. To verify the chaotic behavior, we compute the largest Lyapunov exponent for each implemented case of the corresponding technology, as shown in Figure 6. Table 3 also shows that the Lyapunov exponents for the three physical implementations have a similar value. This behavior suggests the Boolean chaos of proposed BCOs is robust to the distinct physical implementations changing the technology.
(a) Case 1 Table 1 (b) Case 3 Table 1 (c) Case 7 Table 1 (d) Case 1 Table 2 (e) Case 5 Table 2 Figure 6. The divergence ln d(s) to determine the largest Lyapunov exponent of the attractor for cases in Table 3 from each discrete physical implementation (Logic gates, GAL, FPGA). It is worth to noting that, although the intrinsic time-delays of the logic XOR and XNOR gates change among the physical realizations, Case-1 for both BCOs continues generating chaotic behavior. In agreement with Lemma 4, the fact that there is Boolean chaos, for various implementations without extra time-delays in the feedback links, demonstrates that the proposed BCOs are not overly sensitive to heterogeneous intrinsic time-delays.

Chip Design
This section describes the integrated circuit-based implementation of the prospected BCOs in this work. The Boolean chaos generators are described with Verilog, a Hardware Description Language (HDL), using the UMC 180 nm Generic Core Cell Library. The BCO-1 hardware description in Figure 7a uses one XNOR3S and two XOR3S cells from the Generic Core library. That verilogHDL code synthesizes the three logic gates, whereas the Encounter tool (from Cadence Design Systems) executes a generic routing algorithm. Similarly, the BCO-2 of Figure 7b uses one XOR3S and one XNOR3S for the description with the verilogHDL code. The integrated circuit was part of a multiprocess wafer run and is shown in Figure 8 (Left). The size of BCO-1 is 75 µm × 60 µm while the BCO-2 has physical dimensions of 32 µm × 26 µm. The area for biasing rails is considered in both scenarios. In any case, it is possible to reduce the size with routing optimization. 1 It is worth noting that the design process of the IC is straightforward, and it does not depend on critical design considerations. However, all the design processes were executed in a semiautomated way using the generic cells and routing tool from Cadence software and UMC 180 nm fabrication technology. Therefore, this demonstrates, once again, the flexibility and robustness of the proposed BCOs.
On the other hand, Figure 8 (Right) shows the test-bench for the integrated circuit. The chip-die is mounted on an FR4 printed circuit board. It is biased with a low-noise V DD = 1.8 V voltage source model B2962A while the oscilloscope DSOS104A captures the voltage time-series for further analysis.

Experimental Results of the Integrated BCO-1 and BCO-2
Now, we present the continuous-time behavior of both BCO-1 and BCO-2 on the integrated circuit. Figure 9 shows the real-time obtained waveforms and the respective dynamical analysis considering:  Figure 9a presents the BCO-1 features for V DD = 3.3 V. The time-series shows a random evolution since it has variable cycle amplitudes regarding maxima and minima, and the frequency content is characterized for a predominant broad distribution and with strong content up to 200 MHz, therefore suggesting chaotic oscillations. Besides, the time-lag embedded attractor (lag equal to the first minimum of the time-lag mutual information function) exhibits a chaotic behavior in phase space, whose underlying complexity can be more properly appreciated on the corresponding Poincaré map for amplitudes of successive local maxima. In this manner, the arbitrarily chosen plane sections the attractor in two and thereby enables the visualization of its complex geometry. We found that the Poincaré map has a dense set of points, which has been identified as characteristic dynamics of the chaotic behavior. To quantify these observations, we determine the largest Lyapunov exponent (λ max ) of the attractor. The result shows the time evolution of the ln d(s) . This divergence presents an almost constant slope for the first part of the curve and then it saturates at a maximum value, corresponding to the uncorrelated signals x(s + T + t a ) and x(s + T + t b ). Next, we estimate the value of λ max , assuming that the divergence of the initially similar segments is exponential in the region of constant slope. As a result, the average of all pairs of similar segments is our estimate of the largest Lyapunov exponent for the BCO-1, giving λ max = 0.4496, which demonstrates that the CMOS Boolean oscillator integrated at 180 nm is chaotic. Figure 9b shows the dynamical analysis for the same BCO-1 but now with V DD = 2.8 V. This BCO-1 displays a clear chaotic attractor in the 0-4 V range and is validated with the Poincaré set. The results for time-series, frequency spectrum up to 150 MHz, Poincaré map, and λ max = 0.4243 have a similar response to the previous case. Therefore, we can conclude the BCO-1 is robust against bias voltage variations.
The same test is included for the BCO-2 biased to VDD = 3.3 V. The circuit presents a chaotic oscillation but the on-chip pad originates an explicit limitation of the voltage swing. This prototype uses internal pad connections and the reduced swing is a consequence of the extended bonding and absence of I/O cells. Therefore, the on-die probes represent an important load impedance and limit output swing to 200 mV. Figure 9c shows the time evolution, spectral content up to 160 MHz, chaotic attractor, and Poincaré map showing the expected results. Finally, Figure 9c also shows the largest Lyapunov exponent, which has a slope less abrupt but still presents a positive exponent (λ max = 0.2492) in spite of the small values of the continuous-time sequence.

Comparison with Similar Implementations
For the sake of reference, Table 4 highlights the principal features of the recent True Random Number Generator (TRNG), systems based on chaotic circuits. The two new boolean chaotic oscillators exhibit competitive numbers compared to the references [20,42]. The comparison includes the most recent works with attempts to fully integrate the system-on-chip. The work in [20] presents a set of inverted-based chaotic oscillators. The area and power consumption are affordable, but the system uses additional off-chip biasing circuits. The chaotic circuit in [42] is fully integrated with the disadvantage of increasing the circuit resources. This is the result of the multiattractor analog system requiring a large bandwidth but the band limitation or frequency centroid is not reported. The two new boolean chaotic oscillators in this work present a reduced circuit size and power dissipation, not considering the chip input-output cells. The proposed boolean chaotic circuits present the most extended frequency span content compared to the recent on-chip implementations.

Conclusions
Two autonomous Boolean networks that generate Boolean chaos have been introduced. From the mathematical model, it was shown that the logical states would never reach a fixed-point, and therefore, will oscillate permanently. The proposed Boolean chaos oscillators exhibited no dependence on incommensurate time-delays, as demonstrated by computing the Lyapunov exponents under various scenarios for the delay paths. The correct physical implementations of the two Boolean chaos oscillators are good evidence of the predicted conditions. Therefore, the BCOs are reliable and robust to be implemented with multiple circuit implementations, both discrete as integrated.
In particular, the synthesis of the chaotic oscillators in an integrated circuit has shown the benefits of a compact CMOS chaos generator with areas 0.0045 mm 2 and 0.000 832 mm 2 for BCO-1 and BCO-2, respectively, as well as high-speed chaotic oscillations with relevant amplitude content up to 200 MHz. Several dynamical analyses such as time-series, chaotic attractors, Poincaré maps, and Lyapunov exponents validated the experimental results.
In this manner, the proposed Boolean chaos oscillators could be useful for various engineering applications, for instance, random number generators, since the design is straightforward, robust, compact, and can be implemented in many options of hardware without needing special considerations.