A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

The ever-increasing demand for faster computing has led us to an era of heterogeneous integration, where interposers and package substrates have become essential components for further performance scaling. High-bandwidth connections are needed for faster communication between logic and memory dies. There are several limitations to current generation technologies, and dielectric buildup layers are a key part of addressing those issues. Although there are several polymer dielectrics available commercially, there are numerous challenges associated with incorporating them into interposers or package substrates. This article reviewed the properties of polymer dielectric materials currently available, their properties, and the challenges associated with their fabrication, electrical performance, mechanical reliability, and electrical reliability. The current state-of-the-art is discussed, and guidelines are provided for polymer dielectrics for the next-generation interposers.


Introduction
The amount of data generated and processed has seen an exponential increase in the past several years due to the digitization of systems. This trend is expected to accelerate further with the advent of generative Artificial Intelligence (AI). To handle such large amounts of data, system bandwidth needs continuous improvements. The CPU-memory bandwidth is expected to double every two years [1]. Interconnections between various chips are the main bottleneck that needs innovative solutions. There is a need to develop low-power, high-speed on-package copper wiring to tackle this challenge. Several new packaging architectures have been developed to cater to this need. Two main approaches include-(1) planar 2D structures such as interposers, where chips are placed next to each other, and (2) 3D architectures, where chips are stacked on top of each other. These approaches utilize either silicon dioxide or polymers as dielectric layers between the wiring for interconnections. Polymer-based wiring in organic interposers is fabricated using panel-manufacturing tools and processes and can support high input-output (IO) densities, as demonstrated by Shinko and Kyocera [2,3]. Forming these high-IO-density interconnects is highly dependent on the dielectric material properties and processing techniques. The pitch scaling of organic laminates is limited because of the dimensional stability of the core material. Non-polymer-based wiring uses silicon back-end-of-line (BEOL) infrastructure to achieve ultra-high IO densities as demonstrated by TSMC's chipon-wafer-on-substrate (CoWoS) [4] and Intel's Embedded-Interconnect-Bridge (EMIB) [1]. However, non-polymer-based interconnects cannot support higher data rates because of the fundamental limitations of the dielectric. Figure 1 shows the schematic stack up of a package substrate or an interposer. A package substrate consists of a substrate core with multiple layers of polymer dielectric and copper wiring on either side. The copper wiring, also known as redistribution layers (RDLs), forms interconnections between the chips and the printed wiring board (PWB). There could be multiple packages stacked on each other as in the case of silicon interposers. Figure 1 depicts just one layer of package substrate for illustration. It should be noted that the terms "interposer" and "package substrate" are used interchangeably in this article due to the similar processing techniques utilized for the fabrication of both.  Table 1 lists the current state-of-the-art in 2.5D interposers and package substrate technologies. In general, wafer-scale technologies are able to achieve finer wiring because of the more-sophisticated damascene processing, but it utilizes silicon dioxide as the dielectric. A higher dielectric constant of silicon dioxide (D k = 4) imposes limitations with respect to the maximum achievable data transfer rates. The effects of dielectric constant on electrical performance are discussed in detail in Section 3. Table 1. State-of-the-art in RDL technologies.

Technology
Package Architecture Dielectric Diel.

Const. Diel. Thickness (µm) RDL L/S/via (µm) Process
Shinko iTHOP [2,5] 2.5D organic interposer Polymer 3.9 >5 2/2/10 Semi-additive Amkor SWIFT [6,7] Fan-out (wafer) Polyimide 3-3.6 >15 2/2/10 Semi-additive SEMCO [8] Fan-out (panel) PBO 3.1 >5 2/2/6 Semi-additive Kyocera APX [3,9] 2.5D organic interposer Epoxy 3.1 >8 6/6/15 Semi-additive DNP [10] 2.5D glass interposer Polyimide 3-3.6 >12 2/2/20 Semi-additive Amkor SLIM [11] 2.5D interposer SiO 2 4 >2 2/2/2 Damascene Intel EMIB [1] Si bridge SiO 2 4 >2 2/2/2 Damascene TSMC CoWoS [4] 2.5D Si interposer SiO 2 4 >2 0.5/0.5 Damascene Figure 2 shows the trend in bump pitch and lithography dimensions for printed wiring board (PWB) substrates in comparison to BEOL wafer foundry. Panel-scale PWBs are produced at larger lithography dimensions (>50 µm) in comparison to interposers. Panel-sized organic laminate substrates, until a few years ago, were produced at >10 µm. There are several challenges faced by panel RDLs that limit the scaling of RDLs' critical dimensions. Lithography tools for panels need a larger depth-of-focus compared to the BEOL counterparts, limiting the scaling to finer dimensions. Panel substrates also face dimensional abnormalities with respect to warpage and planarity and surface roughness, thus limiting the scaling. These surface topography deformations adversely affect the formation of fine features while patterning and worsen with multiple RDLs [12]. BEOL RDLs use dual-damascene processing to achieve finer RDL dimensions below 1 µm up to 0.1 µm. Because of the limitations of semi-additive processing and the lithography tools used in packaging, package RDLs are an order of magnitude larger than BEOL RDLs. This results in a lithography gap between the package and BEOL RDLs. However, many recent advances in wafer and panel packaging have extended package RDLs to 1 µm. This has led to the bridging of the lithography gap depicted in Figure 2. BEOL RDLs, however, suffer from the disadvantage of higher cost due to smaller wafer-size processing. With recent advances in glass interposers, this issue has now been addressed by providing a panel-sized solution, thus lowering the cost of high-density substrates [13,14]. Additionally, panel-scale processing is critical for the manufacturing of large body-size interposers and substrates, which are less economical at the wafer scale. Table 2 lists various polymer dielectrics commercially available on the market. The current state-of-the-art utilizes dry film (denoted as DF in Table 2) prepregs that are laminated onto substrates under the application of pressure and heat. Ajinomoto is the market leader with their several grades of Ajinomoto Buildup Films (ABFs), listed in Table 2. With the advances in interposer substrates, the trend is toward thinner dielectrics. This is one of the reasons for liquid dielectrics getting attention. Benzocyclobutene (BCB)-based dielectrics from Dow (trade name: Cyclotene) are popular and used mainly in wafer-scale packages due to the wafer-scale spin-coating of liquid dielectrics. Vapor-deposited dielectrics are also available on the market, but they are not popular for package substrates. Parylenes are the main class of materials that dominate this area. They are attractive for research for the next-generation interposers/substrates owing to their low dielectric constant values [15]. Several key properties of dielectrics are compiled and presented in Table 2 from the datasheets available online.

Fabrication and Processing
The selection of polymer dielectrics for packaging is challenging due to the conflicting nature of the fundamental physical properties of polymers. Usually, polymers having low dielectric constant (D k ) values have high CTEs and low elastic moduli, as seen in Table 2. Traditional epoxy-based dielectrics used in package substrates have silica fillers that compensate for the poor mechanical properties of the polymer matrix, but result in an increased D k . Most low-k (D k < 2.5) dielectrics do not have silica fillers, leading to lower D k , but poor mechanical stability. Thus, the selection of polymer dielectrics for RDL applications needs to be carried out with several considerations, which include thermal and mechanical stability, moisture sensitivity, processability, and chemical inertness. D k and D f need to be as low as possible to minimize RDL capacitance and dissipation losses. The processability of polymers is an important factor in being able to build a multilayer structure consisting of RDL routing with microvias. It is critical to control the thickness of the dielectric to achieve the desired microvia dimensions. For targeting smaller microvia dimensions, thinner dielectrics are needed. Dry film dielectrics conventionally used in package substrates are not available with less than a 5 µm thickness. This leaves only liquid-or vapor-deposited dielectrics, as listed in Table 2. Another reason for desiring thin dielectrics is that a lower aspect ratio of the microvias gives better thermomechanical reliability. Liquid dielectrics are difficult to process on panels, as they need to be spin-coated. The uniformity and planarity of spin-coated dielectrics on large panels are poor, especially on multilayered substrates. Furthermore, for impedance matching, very fine thickness control (<1 µm) is desired. Vapor-deposited polymers are, thus, very attractive due to sub-micrometer thickness control. Alternative processing techniques such as "slot die coating" are also gaining traction for depositing thin dielectric layers on large panels. The elastic modulus and CTE of polymers play crucial roles in the thermomechanical reliability of microvias. A low elastic modulus (<7 GPa) is desired to lower the stresses induced in RDLs. A very high modulus makes the polymer less pliable and not able to accommodate the expansion of copper. On the other hand, the CTE value needs to be as low as possible, preferably <40 ppm/K for RDL critical dimensions smaller than 5 µm. Tensile strength and maximum elongation are also critical to prevent polymer cracking. Polymers become viscous and more flowable above their glass transition temperature. Therefore, to prevent RDL failure, the glass transition temperature should ideally be above the solder reflow temperature of about 250 • C. Moisture absorption in polymers leads to ionic migration under the influence of electrical bias. Therefore, moisture absorption needs to be <0.1% with ideally zero ionic content for conductor spacings of <2 µm. In addition, the adhesion of the dielectric to copper is an important factor. This aspect will be discussed in detail in Section 4. Traditionally, package substrates are fabricated at lower temperatures than wafer RDLs. This is an important factor for keeping the cost of the substrates lower. Dielectrics with low curing temperatures <200 • are, thus, desired.  Figure 3 shows the various steps involved in substrate fabrication using a semiadditive process (SAP) traditionally utilized in panel-scale packaging. A core substrate is used to form multiple metal layers on either side. The polymer dielectric is applied using vacuum lamination of dry films followed by seed-layer metallization using electroless or sputter deposition. The next steps include photoresist patterning, electroplating, and photoresist removal. The seed layer used for metalizing is then etched away, thus completing the fabrication of one metal layer. For connecting the adjacent metal layers, vertical interconnects or microvias are drilled, conventionally using laser ablation. Alternatively, microvias can also be made using photo-imageable dielectrics (PIDs) using lithography. PIDs are gaining importance in the industry for their ability to form finer microvias, as well as lines with the damascene process. Figure 3 depicts only one-side processing; however, two-side processing is usually carried out for panel substrates. These steps are repeated to form multiple metal layers on the core to form an interposer or a package substrate. Traditional SAP involves wet processing techniques such as wet electroless deposition, photoresist development and stripping, and copper etching. The polymer dielectrics used to build up layers need to be resistant to the acidic and basic chemicals involved.  While there are many factors influencing adhesion, roughness is one of the main physical properties of the dielectric that influences the adhesion of copper lines onto the dielectric. However, higher roughness is detrimental to the resolution of fine-line features during lithography. Therefore, several materials having low surface roughness have been developed in order to achieve finer RDL wiring. Figure 4 demonstrates the effect that dielectric roughness can have in resolving fine line patterns in photoresists. Two dielectrics with average roughness values (Ra) of 130 nm and 70 nm were evaluated. A positivetone photoresist was patterned with 2 µm lines and spaces. A higher roughness results in diffused reflections at the copper-photoresist interface, resulting in residues and incomplete opening of the photoresist [17]. A smoother dielectric gives better results under the same conditions.
Miniaturization of microvias is important for maximizing the IO density of interposers. Figure 5 shows microvias formed in polymer dielectrics. Figure 5a shows a laser drilled microvia with 3 µm diameter. Figure 5b shows a 4 µm microvia filled with copper. The effect of the filler material on the via shape can be seen clearly. Smaller microvias are difficult to form in dielectrics with filler and often result in much debris, which creates processing challenges. Therefore, it is necessary to reduce the filler percentage, as well as the filler size for further microvia scaling. Figure 5c shows a microvia with a 3 µm top diameter formed in a 5 µm-thick PID using lithography. Tapering of vias is not desirable from the reliability perspective [18]. To achieve smaller and vertical microvias, thinner, filler-less, and higher-resolution PID materials are needed.  The traditional panel-scale SAP utilizes wet desmear followed by electroless deposition for seed layer deposition. Wet desmear involves roughening of the polymer surface using permanganate solution, which provides mechanical interlocking of the seed layer to the polymer. This, however, results in a very rough surface (Ra > 200 nm), leading to challenges during lithography for achieving <5 µm critical dimensions. Therefore, there is an increased focus on the physical vapor deposition of metal seed layers for higher wiring density RDLs [21]. Layer-to-layer registration is a critical aspect affected by the CTE of the underlying dielectric. The CTE affects the dimensional shifts of the copper pads, thereby affecting the alignment accuracy of microvias. Low CTE and rigid dielectrics are, thus, desired for better via alignment accuracy [22].

Electrical Performance
Heterogeneous integration of chiplets is one of the main approaches adopted by the semiconductor industry to achieve higher performances at lower costs. In this approach, separately manufactured chiplets are integrated into an advanced interposer substrate. These heterogeneously integrated systems require high-bandwidth interconnections and low power consumption. Package parasitic losses need to be reduced for improving the signaling and electrical performance of the package. The low resistance and capacitance of RDLs are critical for reducing parasitic losses.
Bandwidth is driven by two factors-the number of IOs and the bit rate per IO (Equation (1)). The number of IOs is determined by the wiring density and the number of layers. The bit rate is determined by the signal speed and interconnect length. Therefore, in order to improve the bandwidth, faster data rates are needed.
Energy per bit (EPB) is an important metric used to compare the energy efficiency of heterogeneous systems. EPB is directly proportional to capacitance (Equation (2)), and achieving high energy efficiency requires the use of low D k materials in interposers. There are studies indicating that a reduction in D k from 3.9 to 2.4 can reduce the EPB by 40% for an interposer with an interconnect length of 5 mm [23]. The effect of D k on the maximum achievable data rates can be seen in Figure 6. The readability of the signal degrades as the bit rate is increased from 2 Gbps to 16 Gbps. The eye width is just 24.5% of the unit interval at 16 Gbps for silicon RDLs due to the higher capacitance. Silicon-dioxide-based damascene RDLs, thus, have limitations in terms of increasing the data transfer rates.
Crosstalk, latency, and losses need to be reduced to improve the bandwidth density of RDLs. Crosstalk mainly originates from the capacitive coupling of metal wires, and losses arise from the resistance and capacitance of the wires. Latency is also a function of the resistance and capacitance of the channels. Therefore, reducing the capacitance of the dielectric leads to improvements in latency, bandwidth, and energy efficiency.
Traditional silicon back-end RDLs use silicon dioxide as a dielectric, which has a high dielectric constant (D k = 4) and, thus, is limited in electrical performance. Therefore, polymer dielectrics with D k < 3 are gaining importance. The dielectric constant and loss are functions of frequency. In typical dielectrics, there are several types of polarizationorientation polarization, ionic polarization, distortion polarization, and electronic polarization [24]. All these are frequency-dependent, and their combined effect determines the dielectric constant at a certain frequency. The dielectric constant of polymers depends on the polarizability of the chemical bonds and groups present in them. Different chemical bonds have different polarizability. Organic molecules and bonds have low polarizability in general. Because of this, the lowest dielectric constant materials are generally polymers. Several polymers have been synthesized so far having low D k for use in RDLs at the chip level [25]. However, wider adoption is absent due to the integration and reliability challenges. Table 3 shows the values of the polarizability and bond strength of common chemical bonds present in polymers [25]. The polarizability of sigma bonds is lower than that of pi bonds. Saturated hydrocarbon groups are, thus, desired in polymer dielectrics. However, higher bond strength is desired from the mechanical reliability point of view. Low polarizability also means low chemical reactivity of molecular groups, resulting in the poor processability of polymers. Because of these conflicting properties, a balance of various molecular groups is necessary to achieve the desired combination of electrical and mechanical properties of polymer dielectrics. The standard dielectric materials used in organic package substrates are based on epoxy polymers. Traditional epoxy polymers for packaging are primarily a blend of Bisphenol A and epichlorohydrin, shown in Figure 7a,b. The compound containing bromine shown in Figure 7c is added for fire retardancy, which is necessary for packaging applications. Different grades of Ajinomoto Buildup Film (ABF) are some examples of epoxy-based polymer dielectrics. Some epoxies also contain functional groups that are more polar, such as carbonyl and hydroxyl. While these functional groups are beneficial for improving adhesion to metals such as copper and are favorable from that standpoint, they often result in higher losses. Cyanate esters have low dielectric constants and low dielectric loss factors. These have been introduced in epoxy-based materials to reduce losses [26]. The presence of stiffeners in the main chain of the polymer such as phenyl rings limits the mobility of the structure and helps in achieving low loss [27].

Mechanical Reliability
A high-performance package substrate consists of multiple layers of polymer dielectrics and conducting metal lines. The reliability issues arise because of the inherent mismatch between the physical and mechanical properties of these layers. Polymer dielectrics have a higher CTE and a lower elastic modulus, whereas copper used for conducting lines has a relatively lower CTE and higher elastic modulus. This mismatch results in the development of stresses. These stresses are developed mainly during the fabrication processes and during the regular operation of electronic devices. Continuous buildup of the stresses ultimately results in physical deformations and, thus, permanent failure of the package and, thereby, the device. It is, therefore, important to design interposers to sustain the stresses developed during their targeted lifetimes. The thermal cycling test (TCT) and the highly accelerated stress test (HAST) are two main reliability tests performed on interposers.

Polymer-Cu Adhesion
The adhesion of copper to polymer dielectrics is the most-important issue pertaining to the miniaturization of RDL L/S. Delamination of copper traces from the dielectric becomes more probable at finer L/S because of the increase in stresses. Because of the presence of molecular groups having low polarizability, adhesion between the copper seed layer and low-D k polymers is challenging. Low-D k dielectrics have low roughness because of the absence of filler. Because of the smoother surface, adhesion by mechanical interlocking is insignificant. Therefore, it becomes essential to optimize or develop innovative pre-sputtering processes to enhance adhesion. There are several ways of enhancing adhesion reported in the literature [29]-surface roughening, chemical modification of the surface, use of an adhesion-promoting layer, UV treatment [30], etc. The main mechanism of adhesion is the mechanical and chemical interaction between the seed layer and the polymer. Yoong Oh et al. [31] studied the effect of plasma pre-treatment on the adhesion of Cu/Ti to the polymer dielectric. The formation of an interlayer between the titanium seed and ABF was reported. Transmission electron microscopy (TEM) images showed the formation of a few nanometers-thick inter-layer on a plasma-treated ABF dielectric [31]. There are numerous reports on the study of metal-polymer interactions. X-ray photoelectron spectroscopy (XPS) has proven to be an important tool for the study of these interactions [32][33][34][35][36][37][38]. Freilich et al. [36,37] studied the interactions of copper and titanium with polyimide using XPS and ultraviolet photoemission spectroscopy (UPS). Based on their findings, a mechanism for the formation of Ti-polymer bonds was proposed. It was theorized that the interaction of titanium with polyimide led to the formation of Ti-O bonds, followed by Ti-C bonds. The formation of reduced imide as an intermediate was also hypothesized. Burkstrand et al. [38] studied the interactions of evaporated Cu, Ni, and Cr on a variety of polymer substrates. The proposed mechanism consisted of the formation of chelate-like metal-oxygen-polymer complexes. The higher adhesion of metals with certain polymers was attributed to the presence of chelate-like complexes. The effects of different types of plasmas on polymer surfaces have been reported in the literature [31,33,35,[39][40][41][42]. The breaking of polymer bonds due to plasma leads to the formation of active chemical species on the polymer surface. This improves the chemical interaction and wettability of the surface and, therefore, aids adhesion. Some reports have also indicated that the effect of plasma diminishes with duration and high temperature [42].
Some of the important processing steps that influence the interactions between metals and polymers are plasma surface treatment, deposition of metals, and annealing. Plasma treatment affects the polymer surface in two ways: it roughens the polymer surface and creates unsatisfied bonds, thereby activating the surface. During the deposition of metal, the arriving atoms may perform a random walk on the surface or diffuse into the polymer. Metal atoms encountering each other on their diffusion path may form aggregates at the surface and in the polymer bulk [43].
By optimizing the pre-sputtering processes, adhesion between the polymer and metal seed layers can be controlled as shown in Figure 8. A higher interaction between the metal and polymer is necessary. In the case of the titanium seed layer, the formation of a larger number of Ti-C bonds enhances adhesion. Figure 9 shows the difference in the XPS spectra of a titanium-deposited polymer dielectric. An increase in adhesion strength was observed from 8.9 N/cm to 11.2 N/cm for the ABF-GX92 dielectric. It corresponded to an 11.9% increase in the Ti-C component in the XPS C-1s spectra [28]. However, it should be noted that, because of the large variety of molecular groups present in polymers, different polymers may require different types of processing to optimize copper-polymer adhesion.

Thermal Cycling Reliability
Thermal cycling reliability is tested using the JEDEC (Joint Electron Device Engineering Council) standard [44]. For HPC applications, the RDL substrate is subject to temperature cycles from −55 • C to 125 • C. Due to the temperature variations, cyclic stresses are developed in the RDL, leading to fatigue failure in copper. Shinko electric industries have demonstrated an organic interposer with thin-film RDL [2]. The critical dimensions of the RDL in the integrated thin-film high-density organic package (i-THOP) were 2/2 µm L/S and 10 µm-diameter microvias. The thermal cycling reliability for 1000 thermal cycles and b-HAST reliability for 150 h were demonstrated. Kudo et al. demonstrated thermal cycling and HAST reliability of a nine-level polymer RDL structure with barrier layers [45,46]. Furuya et al. demonstrated a two-layer RDL structure with 2 µm L/S and 5 µm microvias in a polymer dielectric [47]. Hu et al. demonstrated a three-layer RDL structure with 1.5 µm L/S and 10 µm microvias using an embedded trench approach [48]. Nair et al. demonstrated the thermal cycling reliability of 4 µm microvias using the embedded trench process [49]. Okamoto et al. demonstrated the thermal cycling reliability of 3 µm microvias in a photosensitive polymer dielectric [20]. Figure 10a shows the daisy chain structures fabricated in a PID. Figure 10b shows the evolution of resistance over thermal cycles. The sharp increase in resistance at 1500 cycles was attributed to the cracking at the microvia-pad interface observed in Figure 10c. Glass-based interposer substrates are gaining importance due to their tunable CTE for optimizing board-level reliability [14]. However, because of the brittle nature of glass, cracking of the glass core is a challenge. Figure 11 shows cracking in a glass substrate at the polymer-glass interface. For the prevention of cracking in glass substrates, thinner, low-stress, low-CTE polymer dielectrics are needed to reduce the stresses on the glass. The optimization of the dicing parameters and pull-back mechanisms have also been shown to be helpful for the prevention of cracking [50].

Highly Accelerated Stress Test
The highly accelerated stress test (HAST), also known as the pressure cooker test, is critical for determining the reliability of RDL interposers. Moisture absorption by polymers can lead to mechanical and electrical failure in RDLs. Figure 12 shows cracking at various interfaces in Parylene-N due to high moisture uptake during HAST. The test samples were subject to an 85% relative humidity and a 135 • C temperature for 96 h. High moisture absorption is, thus, detrimental to the mechanical rigidity of polymer dielectrics. Lowmoisture-absorbing polymers are, therefore, needed for preventing such failures.

Residual Stresses and Warpage
Residual stress is developed in RDLs because of the thermal processes such as curing and annealing [51]. High residual stresses lead to large warpage of the substrate and can also induce cracks in the dielectric. Residual stress and warpage become critical issues when dealing with large-body interposers and substrates. Kovach et al. used low-stress processes such as electron-beam curing and electroplating to minimize the stress in the copperpolyimide layers [52]. Chen et al. studied the stress relaxation properties of polyimide in the metal-polyimide interface [53]. It was observed that an intermediate polyimide layer offers significant stress relaxation by plastic deformation. Electroplated copper has the most-pronounced effect on stress development due to its high elastic modulus. Electroplated copper undergoes self-annealing, leading to a gradual increase in stress over time [54,55]. Self-annealing of copper can also lead to the formation of voids due to stress migration [56,57]. Warpage of the substrate is proportional to the stress; thus, lowering stress would automatically lead to a lower warpage [58]. Warpage of interposers and substrates is important from the reliability and assembly point of view. Large warpage can lead to solder bridging during the assembly process and could also lead to poor reliability of solder joints due to accumulated stresses. Warpage depends on the modulus, CTE, and dimensions of the substrate. This was illustrated in a study by Hegde et al., wherein warpage was compared for different dielectric materials laminated on FR4. The material having the highest modulus showed the highest warpage, despite a low CTE value. The same study also showed that, when the properties of both the substrate and the dielectric were considered, the thickness, modulus, and CTE of the substrate influenced the warpage more strongly [59]. Figure 13 shows the stress evolution in RDLs with the process steps and copper thickness, respectively. Copper has the most-dominant effect on stress evolution, especially after annealing. Furthermore, with an increasing thickness of the copper, the stress becomes independent of the dielectric thickness and properties. However, the low modulus of the polymer dielectric helps keep the stress low for most parts of the fabrication process. The effects of the dielectric and substrate properties on stresses and warpage have been reported [60]. The elastic modulus and CTE of polymer dielectrics have the most-pronounced effect on the stresses and on RDL reliability.

Electrical Reliability
Electrical reliability concerns in polymer RDLs arise due to two main phenomenaionic migration and dielectric breakdown. As we scale down the RDL dimensions, the electric field between two adjacent lines increases because of the reduction in the conductor spacing. The elevated electric field plays an important role in determining the electrical reliability of RDL L/S. Ionic impurities in the presence of moisture give rise to a higher ionic migration rate. Additionally, a higher electric field combined with elevated operating temperatures leads to leakage and dielectric breakdown. It is very crucial to address both of these challenges for achieving electrically reliable RDLs. Electrical reliability evaluations are conducted according to the JEDEC reliability standard [61].

Ionic Migration
Polymers contain ionic impurities originating from the byproducts during polymer synthesis [62,63]. Because of these impurities, polymer dielectrics act as electrolytes facilitating the transfer of metal ions across two conducting lines [64]. As we reduce the RDL L/S, the electric field across two lines increases and leads to an increase in the rate of migration of metal ions from the anode to the cathode. This can lead to the formation of conducting pathways or dendrites [65,66] across two conductors, leading to shorting. Figure 14a shows oxidation and shorting of comb structures coated with BCB dielectric. The test samples were subject to biased-HAST (b-HAST) conditions of an 85% relative humidity, 135 • C temperature, and 5 V applied bias for 96 h. Moisture absorption during b-HAST led to the oxidation of copper. The reaction of copper with oxygen from the polymer backbone is also a possibility. Figure 14b shows dendrite formation due to ionic impurities present in the dielectric. To prevent failures due to ionic migration, it is important to minimize ionic impurities arising from the polymerization reactions. Additionally, it is important to reduce moisture absorption by the careful selection of molecular groups during the formulation of polymer dielectrics.

Dielectric Breakdown and Leakage
The dielectric breakdown strength is an important property for the electrical reliability of polymer RDLs. When a voltage is applied across a dielectric, the electrical insulation of the dielectric fails at a certain value of voltage, leading to a high leakage current. This phenomenon is known as "dielectric breakdown". It is typically observed as an electrical arc across the electrodes, resulting in a catastrophic decrease in insulation resistance. The leakage current in polymer dielectrics does not follow Ohm's law. Before the onset of breakdown, the current density across the electrodes increases almost exponentially with the electric field. Once reaching the breakdown potential, it abruptly increases to extremely high values, thus destroying the dielectric by burning due to localized high current densities. There are different mechanisms of dielectric breakdown reported in the literature-intrinsic, avalanche, thermal, hopping, charge-injection, and electro-mechanical breakdown [67][68][69][70]. Thermal breakdown occurs when the dielectric is overheated by an electric current, causing the polymer to melt or burn at a certain voltage. In this case, the dielectric strength is proportional to the square root of the plastic's thermal and electrical conductivity ratio [68]. In this case, impact ionization is the most-common cause of electrical breakdown. The chemical and molecular structure of polymers affects the bond characteristics, as shown in Table 3, and thereby, the dielectric strength of polymers. The breakdown strength is directly proportional to the elastic modulus and inversely proportional to the dielectric constant [71]. Figure 15 shows the results of biased-HAST on BCB-coated comb structures. The test conditions were the same as mentioned earlier. The effect of conductor spacing on the failure time is clearly demonstrated. For a 5 µm conductor spacing, failure did not occur even after 100 h, while for a 1 µm spacing, failure occurred within 20 h. This was attributed to the dielectric breakdown of the polymer at elevated temperatures and at high electric fields. Figure 16 shows SEM images of electrical failure in comb structures with Parylene-C as the dielectric. The high leakage current caused localized melting of copper, leading to electrical shorting, possibly due to thermal breakdown. Energy dispersive spectroscopy (EDS) maps showed chlorine concentration and clustering around Cu traces, denoting accelerated failure due to the ionization of chlorine atoms. Table 4 shows the dielectric constant and dielectric strength values of relevant dielectric materials used in packaging. Theoretically, a bias voltage of 530 V needs to be applied to cause dielectric breakdown across two conductors with a 1 µm spacing and BCB as the dielectric. However, in the b-HAST experiments, the dielectric strength was found to be significantly lower than the values from the datasheet. This is because the breakdown strength is significantly degraded by the presence of defects and impurities. Furthermore, various other factors such as ramp rate, dielectric thickness, and temperature affect the measured dielectric strength values. Therefore, detailed studies need to be carried out to understand the effects of all these factors on dielectric breakdown, as well as on the electrical reliability of polymer dielectrics. With the miniaturization of critical dimensions in package RDLs, defect-free polymer dielectrics having high breakdown strengths are necessary for achieving electrical reliability.

Summary and Future Needs
The overall trend in the semiconductor industry is towards heterogeneous integration of chiplets onto interposers. Multiple high-bandwidth memory dies are expected to be integrated with logic dies all onto a single interposer. This requires larger interposer body sizes. This translates to performance, processing, and reliability challenges with respect to polymer dielectrics. The following list summarizes the critical needs.

•
Lower D k (<2.5) dielectrics are needed for achieving higher bandwidth densities, as well as for minimizing losses and latency. With larger interposer and substrate sizes, the total length of connections between chiplets is going to be longer than the traditional homogeneously integrated chips. This necessitates lower RDL capacitance for maintaining the electrical performance and loss budgets. • Novel processing techniques are needed for integrating new dielectric materials. This needs to be performed using large panel-scale processing to lower the cost of larger substrates. • Thinner dielectric layers (<5 µm) are needed for reducing the overall buildup thickness. Larger substrates will have restrictively higher warpages with the current RDL design rules. It is critical to use thinner dielectrics and build thinner substrates. Additionally, thinner dielectrics are desired to make smaller and reliable microvias with diameters smaller than 5 µm. • Low-CTE (<40 ppm/K) and low-stress polymers are needed to minimize the stresses induced in RDLs. The miniaturization of RDLs will be restricted with the high stresses induced by current high-CTE dielectrics. The stability of CTE and mechanical properties up to the operating and solder reflow temperatures is also critical. • Fillers in polymer dielectrics create processing, yield, and reliability challenges in achieving finer RDL dimensions, as discussed in Section 2. Filler-less polymer dielectrics with low roughness (Ra < 20 nm) are needed for the scaling of RDL lines, as well as microvias. • Defect-free polymers with high dielectric breakdown strength are needed to prevent electrical failures in RDLs. Additionally, low moisture absorption (<0.1 wt%) and zero ionic content are critical to prevent ionic migration of metal atoms.

Conflicts of Interest:
The authors declare no conflict of interest.