Electrohydrodynamic-Jet (EHD)-Printed Diketopyrrolopyroole-Based Copolymer for OFETs and Circuit Applications

We report the employment of an electrohydrodynamic-jet (EHD)-printed diketopyrrolopyrrole-based copolymer (P-29-DPPDTSE) as the active layer of fabricated organic field-effect transistors (OFETs) and circuits. The device produced at optimal conditions showed a field-effect mobility value of 0.45 cm2/(Vs). The morphologies of the printed P-29-DPPDTSE samples were determined by performing optical microscopy, X-ray diffraction, and atomic force microscopy experiments. In addition, numerical circuit simulations of the optimal printed P-29-DPPDTSE OFETs were done in order to observe how well they would perform in a high-voltage logic circuit application. The optimal printed P-29-DPPDTSE OFET showed a 0.5 kHz inverter frequency and 1.2 kHz ring oscillator frequency at a 40 V supply condition, indicating the feasibility of its use in a logic circuit application at high voltage.


Introduction
A variety of developed polymeric semiconductors have shown good electrical performances and, in many cases, outperform their metal oxide (ZnO, etc.) and amorphous silicon counterparts [1][2][3]. The planar structures of the polymeric chains have been shown to give rise to increased extents of molecular self-assembly and well-developed microcrystalline domains, and thereby high electrical performances with field-effect mobilities (µ FET s) of over 70 cm 2 /(V·s) in organic field-effect transistors (OFETs) [4,5]. Various printing technologies, such as capillary force lithography and roll-to-roll coating, as well as aerosol jet, inkjet, and electrohydrodynamic-jet (EHD) printing, have been recently used to deposit and pattern polymeric semiconductors [6][7][8][9].
EHD printing has proven to be a particularly cost-effective and simple printing tool [10]. This printing tool generates a strong electrostatic field between a nozzle tip and a substrate to eject ink directly polymers because of the relatively high viscosities of such polymer inks, compared to those of small-48 molecule inks; as a result, this printing tool can produce high-resolution patterns of polymeric 49 semiconductors [14].

Materials
P-29-DPPDTSE was prepared by using the previously reported method [5]. The number average molecular weight and polydispersity index (PDI) of the polymer were measured by carrying out room-temperature gel permeation chromatography with a polystyrene standard calibration together with tetrahydrofuran as the eluent. The number average molecular weight and PDI of P-29-DPPDTSE were determined to be 35,700 g/mol and 1.65, respectively.

Morphological Characterization
The crystal structures of EHD-printed P-29-DPPDTSE were characterized using two-dimensional grazing-incidence wide-angle X-ray scattering (2D-GIWAXS) performed at the 3C beamline of the Pohang Accelerator Laboratory (PAL), Pohang, Korea. AFM experiments were conducted using a Multimode Illa (Veeco Inc. PL, USA) operating in tapping mode with a silicon cantilever. The P-29-DPPDTSE samples used in the XRD and AFM studies were printed using the EHD jet on an octadecyltrichlorosilane (ODTS)-modified silicon wafer to mimic the device fabrication process and then dried under a vacuum at room temperature. After this deposition of the polymer, the samples were annealed at 200 • C for 10 min to test the effect of thermal annealing.

Device Fabrication and Measurements
To fabricate OFETs based on P-29-DPPDTSE, we used heavily N-doped silicon with a 100 nm-thick thermally grown layer of SiO 2 as a dielectric. The capacitance of the dielectric layer was 30 nFcm −2 . OFET properties of the P-29-DPPDTSE were characterized in a bottom gate/top contact architecture with gold source/drain electrodes. The surface of the silicon oxide, before being modified with ODTS, was first cleaned with a piranha solution [H 2 O 2 (40 mL)/concentrated H 2 SO 4 (60 mL)] for 20 min at 280 • C, rinsed with distilled water several times, and treated with ozone for 15 min. Then the SiO 2 dielectric was treated with an ODTS monolayer and with toluene for 90 min at room temperature. EHD printing was then used to deposit the P-29-DPPDTSE semiconductor layer on the ODTS-treated SiO 2 dielectric. For the fabrication of printed OFETs, EHD-jet printing of P-29-DPPDTSE was conducted using an EHD printer (Enjet, Suwon, Korea) operated using its cone-jet mode. A metallic nozzle holder attached to a glass syringe in the EHD printer was filled with a 1 wt% P-29-DPPDTSE solution in chloroform. The P-29-DPPDTSE solution was ejected at a flow rate of 0.10 µL/min using a syringe pump through a nozzle with a diameter of 50 µm. To apply an electrostatic field between the nozzle and the Au substrate ground, a supply voltage of 2.5 kV was generated by an installed power supply. The printing speed and working distance were fixed at 5 mm/s and 100 µm, respectively. The entire process was interfaced with a computer and monitored using a CCD (charge-coupled device) camera. Finally, Au source and drain electrodes (100 nm thickness) were deposited by carrying out thermal evaporation through a shadow mask (with the channel region having a length (L) of 50 µm, and width (W) of 1000 µm). The OFET devices were annealed at 200 • C for 10 minutes under a nitrogen atmosphere. OFET device measurements were taken in an N 2 -purged glove box (H 2 O, O 2 < 0.1 ppm) using both Keithley 2400 and 236 source/measure units. The µ FET values were extracted in the saturation regime from the slope of the source-drain current.

Computational Simulations
In the development process of inorganic semiconductors such as silicon, the industry uses the evaluation results of dynamic circuit characteristics in actual application circuits as the main indexes. Therefore, in OFET development, it is important to examine the performance when applied to more practical application circuits by performing dynamic AC (alternating current) analysis in addition to device measurement and analysis in steady-state DC (direct current) state. In this process, an inverter circuit, a standard cell, which is the most basic logic application, is mainly used for benchmarking between different technologies. Other standard cell circuits, such as NAND and NOR, could be expanded, but in this work, an inverter was selected as the main benchmark circuit as in many inorganic semiconductor technology development works.
In order to apply the P-29-DPPDTSE-based OFET to the integrated circuits, it was essential to provide a design environment using an electronic design automation (EDA) tool, and to do so, a compact model capable of describing electrical characteristics such as I-V (current-voltage) and C-V (capacitance and voltage) under various design bias conditions of OFETs was required. A compact model consisting of analytical equations was implemented in the SPICE (Simulation Program with Integrated Circuit Emphasis) design tool. Then, the circuit optimization was performed by simulating the characteristics of the design circuit for various bias conditions and device sizes in conjunction with other circuit-constituting elements. In order to verify the high-voltage logic circuit characteristics of the synthesized OFETs, Synopsys' HSPICE was used, specifically to simulate dynamic circuit characteristics in conjunction with extracted BSIM4 (Berkeley Short-channel IGFET (Insulated-Gate Field-Effect Transistor) Model 4) model parameter libraries for describing electrical characteristics of each device. Note that BSIM4, which is a widely used industry-standard model and provides various fitting parameters, was used. For the dynamic AC analysis, it is important to extract the model parameters for the electric behaviors. The feasibility of applying BSIM4 to OFETs has already been confirmed in our previous work [22]. Note that, in the developed model library, the gate leakage current and the parasitic capacitance between the gate and source/drain can be negligible due to the use of a very thick gate oxide and due to the fringe field due to the use of a very large device area, respectively.

Results and Discussion
EHD printing was used to fashion P-29-DPPDTSE as the active layers of the OFETs (Figures 1b and 2a). Previous studies by the Kim group optimized the thermal annealing conditions for the device fabrication [5]. The morphologies of the EHD-printed P-29-DPPDTSE lines were intimately related to its electrical properties when used as active layers in the OFETs. Patterned P-29-DPPDTSE lines were characterized by using AFM (Figure 2b,c). The pristine P-29-DPPDTSE sample and that annealed at 200 • C showed root-mean-square (RMS) roughness values of 2.20 nm and 2.03 nm, respectively, with the annealed sample more clearly showing a granular morphology. Molecular packing of P-29-DPPDTSE in the printed lines was investigated by taking XRD measurements of them ( Figure 3). Both the pristine and annealed P-29-DPPDTSE lines showed (001), (002), and (003) XRD peaks along the out-of-plane direction. The pristine P-29-DPPDTSE sample yielded a (001) diffraction peak at q = 0.23 Å −1 , with an interlayer distance of 27.3 Å. By contrast, the annealed P-29-DPPDTSE sample yielded a (001) peak at q = 0.22 Å −1 , with an increased interlayer distance of 28.6 Å. This result may have been due to a straightening of bent side chains as a result of thermal annealing.     at half-maximum of the peak). As summarized in    To obtain more accurate information about the crystallinity of the EHD-printed P-29-DPPDTSE patterns, coherence lengths were extracted from the (001) diffraction peaks in the out-of-plane profiles of the samples (Figure 3c), with these lengths determined as 2π/FWHM (FWHM: full width at half-maximum of the peak). As summarized in Table 1, compared to the (001) peak for the pristine P-29-DPPDTSE sample, that for the annealed sample showed a lower FWHM value, yielding a greater coherence length of 400.7 Å. This result was indicative of a smaller grain boundary of the annealed P-29-DPPDTSE sample, which could reduce the barrier for changes to efficient transport [23,24]. Table 1. Results of the crystallographic analysis of E-jet-printed P-29-DPPDTSE crystals. d(001) denotes the d-spacing value of the (001) plane. The coherence lengths were determined from the full width at half-maximum of the peak (FWHM) values of the (001) peaks in Figure 3. The electrical characteristics of the EHD-printed P-29-DPPDTSE films ( Figure 4) were evaluated by fabricating typical bottom-gate/top-contact OFETs. The P-29-DPPDTSE OFET devices annealed at 200 • C showed ( Table 2) a hole µ FET of 0.45 cm 2 /(V·s) with an on/off ratio of 3.0 × 10 3 , while the OFETs without thermal annealing showed a much lower hole µ FET of 0.09 cm 2 /(V·s) with an on/off ratio of 6.3 × 10 2 . To better understand the circuit operation, the electrical behaviors of the synthesized OFETs were modeled by using the Berkeley Short-Channel IGFET Model 4 (BSIM4) [22,25]. As shown in Figure 5a, the extracted BSIM4 model (lines) reproduced the measured P-29-DPPDTSE OFET (symbols) quite well and could accurately simulate the circuits in conjunction with a circuit simulator, such as SPICE. As shown in Figure 5b, the logic-circuit performances of the p-type OFET inverter with an operating frequency of 0.5 KHz were evaluated; these values were well modeled by the developed BSIM4 model library. 188        The inverter gate we tested basically consisted of one resistive load, R L (∼60 MΩ), and one driver OFET with W/L values of 1000/50 µm (see inset schematic of Figure 6a). When the input voltage (V in ) was in a low-voltage state (0 V), the p-type OFET acted as a shortened switch and pulled the output voltage (V out ) to the DC supply, supply voltage (V DD ). On the other hand, the transistor was in the open state, and finally, V out was pulled down by the resistor R L to ground as V in reached a high-voltage state (V DD ). Figure 6a,b show, respectively, the acquired voltage-transfer curves and the inverter gains of the designed inverter for supply voltages ranging from 20 V to 40 V. Performance parameters such as the minimum output high voltage (V OH ), maximum output low voltage (V OL ), rising time (t R ), falling time (t F ), and propagation delay time (t P ) of the inverter for various supply voltages are also summarized in the table of Figure 6b [26]. When the circuit performance of the EHD-printed P-29-DPPDTSE OFET in this work is compared to the circuit performance of the Poly(quinacridone-quinoxaline), PQCQx, polymer-based OFET from our previous work [25], it is observed that EHD-printed P-29-DPPDTSE OFET shows much better performance than the previous work. Since the two OFET devices target different operating voltages, it is difficult to make a direct comparison. Therefore, we compared the two OFET devices at the same over-drive voltage defined by the threshold voltage and the supply voltage difference for a fair comparison. Comparing the logic inverter gain to a similar over-drive voltage case (V DD = 40 V in this work), the gain of the EHD-printed P-29-DPPDTSE OFET is 6.91, and the gain of the PQCQx OFET is 3.20, which shows that the EHD-printed P-29-DPPDTSE OFET has better logic circuit performance.

Conditions Crystallographic Parameters Value
Additionally, as depicted in Figure 7, a five-stage ring oscillator composed of a designed inverter with resistive load was also evaluated. The output terminal (V out ) of the last stage was connected to the input terminal of the first stage with a feedback path. An output oscillation frequency (f OSC ) of 1.2 kHz was measured for a V DD of 40 V, and f OSC increased as the supply voltage (V DD ) was increased, as plotted in Figure 7c.

203
When the circuit performance of the EHD-printed P-29-DPPDTSE OFET in this work is 204 compared to the circuit performance of the Poly(quinacridone-quinoxaline), PQCQx, polymer-based

205
OFET from our previous work [25], it is observed that EHD-printed P-29-DPPDTSE OFET shows 206 much better performance than the previous work. Since the two OFET devices target different 207 operating voltages, it is difficult to make a direct comparison. Therefore, we compared the two OFET

Conclusions
In this work, a conjugated P-29-DPPDTSE polymer based on both a DPP unit and a selenophene vinylene selenophene unit was applied in EHD-printed OFETs and simulated in circuits. The thermally annealed OFET device showed a high field-effect mobility value at 0.45 cm 2 /(Vs). The morphologies of the printed P-29-DPPDTSE samples were determined by carrying out OM, XRD, and AFM experiments, and a designed inverter and ring oscillator using P-29-DPPDTSE-based OFETs were shown to successfully realize a logic operation with, respectively, frequencies of 0.5 kHz and 1.2 kHz at a 40 V supply condition.