Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

: The tunnel ﬁeld-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.


Introduction
The phenomenon of band-to-band tunneling (BTBT) enables a tunnel field-effect transistor (TFET) to achieve smaller than a 60 mV/dec subthreshold swing (SS) at room temperature [1][2][3]. The integration of TFET and the conventional metal-oxide-semiconductor field-effect transistor (MOSFET) on the same silicon chip is a promising choice for future integrated circuits (ICs) [4]. Circuit implementations with both TFET and MOSFET proposed in the existing literature have achieved good performance [5][6][7][8]. Electrostatic discharge (ESD) protection is one of the key reliability issues of ICs, especially in advanced technologies [9,10]. Recently, silicon-based point TFETs have been investigated in the role of ESD protection devices and proposed for use in an ESD protection network [11][12][13][14]. It was verified that by using a TFET to replace the traditional diode in the whole-chip ESD protection network, the whole-chip ESD robustness can be improved since a secondary discharge path is added [14]. However, the results in the aforementioned literature show that the point TFET cannot make a significant contribution to the whole-chip ESD protection due to the low discharge capability. Therefore, it is necessary to search for a new TFET with different structures or different materials possessing higher discharge currents and lower trigger voltages compared to point TFETs.
In this paper, first, TFETs in different configurations are compared and it is found that the germanium-source (Ge-source) TFET has better ESD characteristics compared to the silicon point and line TFETs. Second, the application of the Ge-source TFET in the wholechip ESD protection network is investigated, and the thermal instability of a Ge-source TFET induced failure is observed. Last, available solutions are discussed, and simulation results are analyzed in detail.

Model Calibration and Devices Structure
The simulations for this work were performed using the Sentaurus-TCAD tool. We used the non-local dynamic BTBT model, van Overstraeten-de Man avalanche generation model, high-field saturation model, Philips unified mobility model, thermodynamic model, band gap narrowing and Shockley-Read-Hall recombination models. The simulation parameters were calibrated by reproducing the experimental results of the TFET [14,15], which are presented in Figure 1a,b. It is evident that the experimental and simulated data agree with one another. source TFET induced failure is observed. Last, available solutions are discussed, and simulation results are analyzed in detail.

Model Calibration and Devices Structure
The simulations for this work were performed using the Sentaurus-TCAD tool. We used the non-local dynamic BTBT model, van Overstraeten-de Man avalanche generation model, high-field saturation model, Philips unified mobility model, thermodynamic model, band gap narrowing and Shockley-Read-Hall recombination models. The simulation parameters were calibrated by reproducing the experimental results of the TFET [14,15], which are presented in Figure 1a,b. It is evident that the experimental and simulated data agree with one another.  The cross-sectional views of the point TFET, line TFET and Ge-source TFET used in this work are shown in Figure 2. The parameters are as follows: effective oxide thickness Tox = 1 nm , depth of the junction Xj = 30 nm, thickness of the pocket between the gate oxide and the source Tpocket = 3 nm , lengths of the drain and channel equal to 100 nm, length of The cross-sectional views of the point TFET, line TFET and Ge-source TFET used in this work are shown in Figure 2. The parameters are as follows: effective oxide thickness T ox = 1 nm, depth of the junction X j = 30 nm, thickness of the pocket between the gate oxide and the source T pocket = 3 nm, lengths of the drain and channel equal to 100 nm, length of gate-source overlap L ov = 80 nm, gate metal work function φ = 5 eV, p+ source doping N S = 1 × 10 20 cm −3 (Ge-source TFET: N S = 1 × 10 19 cm −3 ), n+ drain

Transfer Characteristics
As mentioned in [12,13], the TFETs subjected to an ESD stress have a BTBT-assisted avalanche generation mechanism. However, as the BTBT current of the point TFET is not high enough, the reduction in trigger voltage is still not satisfactory. Therefore, optimization of the TFET structure to increase the BTBT current can reduce the trigger voltage. Generally, the line TFET has a larger BTBT current than the point TFET because the tunneling area can be increased easily by enlarging the length of the gate-source overlap region (Lov) [16]. Using the germanium material in the source region can further increase the TFET's current because the material has a narrower band gap and lower carrier effective mass than silicon and, consequently, the BTBT generation rate is increased [15,17]. Simulated transfer curves of the three types of TFETs are shown in Figure 3, where it can be observed that the Ge-source TFET has a significantly higher BTBT current under the same bias condition with a comparable device size.

Transfer Characteristics
As mentioned in [12,13], the TFETs subjected to an ESD stress have a BTBT-assisted avalanche generation mechanism. However, as the BTBT current of the point TFET is not high enough, the reduction in trigger voltage is still not satisfactory. Therefore, optimization of the TFET structure to increase the BTBT current can reduce the trigger voltage. Generally, the line TFET has a larger BTBT current than the point TFET because the tunneling area can be increased easily by enlarging the length of the gate-source overlap region (L ov ) [16]. Using the germanium material in the source region can further increase the TFET's current because the material has a narrower band gap and lower carrier effective mass than silicon and, consequently, the BTBT generation rate is increased [15,17]. Simulated transfer curves of the three types of TFETs are shown in Figure 3, where it can be observed that the Gesource TFET has a significantly higher BTBT current under the same bias condition with a comparable device size. The gates of TFETs can be connected to their own drains or sources. In this work gates are connected to the drains, and, in turn, the BTBT and avalanche generation occur in proximity to the source/channel interface. Note that since a proper gate m work function was used, the leakage currents under the normal operating condition = VD = 1 V) are low enough, as shown in Figure 3.

Electrostatic Discharge Characteristics
Under the ESD event, the gate and drain voltages are both elevated when the cu is injected into the drain terminals. The vertical electric field across the channel incre the energy bands bend and, in turn, the BTBT current is generated. This current prov the initial carriers for avalanche generation, and, therefore, a relatively low breakd voltage is obtained [13]. Figure 4 shows the contour plots of the BTBT generation impact ionization rates of all three TFETs under the same applied voltage (3 V). It ca observed that the Ge-source TFET has a significantly higher BTBT generation rate impact ionization rate.  The gates of TFETs can be connected to their own drains or sources. In this work, the gates are connected to the drains, and, in turn, the BTBT and avalanche generation both occur in proximity to the source/channel interface. Note that since a proper gate metal work function was used, the leakage currents under the normal operating condition (V G = V D = 1 V) are low enough, as shown in Figure 3.

Electrostatic Discharge Characteristics
Under the ESD event, the gate and drain voltages are both elevated when the current is injected into the drain terminals. The vertical electric field across the channel increases, the energy bands bend and, in turn, the BTBT current is generated. This current provides the initial carriers for avalanche generation, and, therefore, a relatively low breakdown voltage is obtained [13]. Figure 4 shows the contour plots of the BTBT generation and impact ionization rates of all three TFETs under the same applied voltage (3 V). It can be observed that the Ge-source TFET has a significantly higher BTBT generation rate and impact ionization rate. The gates of TFETs can be connected to their own drains or sources. In this work, the gates are connected to the drains, and, in turn, the BTBT and avalanche generation both occur in proximity to the source/channel interface. Note that since a proper gate meta work function was used, the leakage currents under the normal operating condition (VG = VD = 1 V) are low enough, as shown in Figure 3.

Electrostatic Discharge Characteristics
Under the ESD event, the gate and drain voltages are both elevated when the curren is injected into the drain terminals. The vertical electric field across the channel increases the energy bands bend and, in turn, the BTBT current is generated. This current provides the initial carriers for avalanche generation, and, therefore, a relatively low breakdown voltage is obtained [13]. Figure 4 shows the contour plots of the BTBT generation and impact ionization rates of all three TFETs under the same applied voltage (3 V). It can be observed that the Ge-source TFET has a significantly higher BTBT generation rate and impact ionization rate.    Transmission line pulsing (TLP) simulation is widely used to estimate the behav of ESD protection devices and circuits. In the simulation, the current pulse has a rise t of 10 ns and a pulse width of 100 ns to mimic the human body model ESD event [12, The quasi-statistic characteristics are obtained by averaging the transient data in an in val of 60 to 90 ns. According to [18,19], the lattice temperature is usually used as the cr rion to determine device failure in simulations. The critical failure temperature is usu defined as a value that is hundreds of degrees kelvin lower than the melting temperatu The critical failure temperatures of the full-silicon TFET and Ge-source TFET in the sim lation are set to 1200 and 890 K, respectively. Figure 5 shows the TLP curves of different TFETs and the reverse shallow-tren isolation (STI) diode. The parameters of the reverse STI diode are consistent with TFE It is concluded that the quasi-static electrical characteristics of all TFETs are well compa to the reverse STI diode. The authors of [14] proved that point TEFTs can replace the verse STI diode, and for this reason, this work will only discuss the comparison betw TFETs. It is evident that under 0.1 mA/μm current pulse, the trigger voltage is as low 2.3 V for Ge-source TFET, while it is 5.2 and 6.9 V for the line TFET and point TFET, spectively. As the voltage across the Ge-source TFET is significantly lower than that acr the line TFET and point TFET, a lower amount of heat will be generated in the Ge-sou TFET. Consequently, the failure current of the Ge-source TFET increases.

BTBT Gen
The discharge capacity of the TFETs is higher than that of the traditional diodes s in Figure 5. It should be noted that the above conclusion stands when the ESD curr flows from the n+ region to the p+ region. When the ESD current flows from the p+ reg to the n+ region, both the TFET and the diode operate in positive diode mode and t have a similar discharge capability.  Transmission line pulsing (TLP) simulation is widely used to estimate the behavior of ESD protection devices and circuits. In the simulation, the current pulse has a rise time of 10 ns and a pulse width of 100 ns to mimic the human body model ESD event [12,14]. The quasi-statistic characteristics are obtained by averaging the transient data in an interval of 60 to 90 ns. According to [18,19], the lattice temperature is usually used as the criterion to determine device failure in simulations. The critical failure temperature is usually defined as a value that is hundreds of degrees kelvin lower than the melting temperature. The critical failure temperatures of the full-silicon TFET and Ge-source TFET in the simulation are set to 1200 and 890 K, respectively. Figure 5 shows the TLP curves of different TFETs and the reverse shallow-trenchisolation (STI) diode. The parameters of the reverse STI diode are consistent with TFETs. It is concluded that the quasi-static electrical characteristics of all TFETs are well compared to the reverse STI diode. The authors of [14] proved that point TEFTs can replace the reverse STI diode, and for this reason, this work will only discuss the comparison between TFETs. It is evident that under 0.1 mA/µm current pulse, the trigger voltage is as low as 2.3 V for Ge-source TFET, while it is 5.2 and 6.9 V for the line TFET and point TFET, respectively. As the voltage across the Ge-source TFET is significantly lower than that across the line TFET and point TFET, a lower amount of heat will be generated in the Ge-source TFET. Consequently, the failure current of the Ge-source TFET increases.  Transmission line pulsing (TLP) simulation is widely used to estimate the behavior of ESD protection devices and circuits. In the simulation, the current pulse has a rise time of 10 ns and a pulse width of 100 ns to mimic the human body model ESD event [12,14] The quasi-statistic characteristics are obtained by averaging the transient data in an interval of 60 to 90 ns. According to [18,19], the lattice temperature is usually used as the criterion to determine device failure in simulations. The critical failure temperature is usually defined as a value that is hundreds of degrees kelvin lower than the melting temperature The critical failure temperatures of the full-silicon TFET and Ge-source TFET in the simulation are set to 1200 and 890 K, respectively. Figure 5 shows the TLP curves of different TFETs and the reverse shallow-trenchisolation (STI) diode. The parameters of the reverse STI diode are consistent with TFETs It is concluded that the quasi-static electrical characteristics of all TFETs are well compared to the reverse STI diode. The authors of [14] proved that point TEFTs can replace the reverse STI diode, and for this reason, this work will only discuss the comparison between TFETs. It is evident that under 0.1 mA/μm current pulse, the trigger voltage is as low as 2.3 V for Ge-source TFET, while it is 5.2 and 6.9 V for the line TFET and point TFET, respectively. As the voltage across the Ge-source TFET is significantly lower than that across the line TFET and point TFET, a lower amount of heat will be generated in the Ge-source TFET. Consequently, the failure current of the Ge-source TFET increases.
The discharge capacity of the TFETs is higher than that of the traditional diodes seen in Figure 5. It should be noted that the above conclusion stands when the ESD current flows from the n+ region to the p+ region. When the ESD current flows from the p+ region to the n+ region, both the TFET and the diode operate in positive diode mode and thus have a similar discharge capability.  The discharge capacity of the TFETs is higher than that of the traditional diodes seen in Figure 5. It should be noted that the above conclusion stands when the ESD current flows from the n+ region to the p+ region. When the ESD current flows from the p+ region to the n+ region, both the TFET and the diode operate in positive diode mode and thus have a similar discharge capability.
In order to evaluate the device characteristics under fast ESD events, such as the charged device model (CDM), a very fast TLP (VFTLP) current with a rise time and pulse width of 0.2 and 2 ns, respectively, is applied to the TFETs. The simulation curves are shown in Figure 6. In order to evaluate the device characteristics under fast ESD events, such as the charged device model (CDM), a very fast TLP (VFTLP) current with a rise time and pulse width of 0.2 and 2 ns, respectively, is applied to the TFETs. The simulation curves are shown in Figure 6.
The results reveal that, as expected, the trigger voltage trend is the same as that obtained in the TLP simulation. However, the failure current of the line TFET is almost identical to that of the point TFET. This is because when the device is fully turned on, the BTBT current is no longer the dominant factor affecting the current conduction. The Ge-Source TFET still performs better than the other two TFETs. It should be mentioned that the failure current for the VFTLP simulation is higher than that for the TLP simulation because the VFTLP pulse width is significantly shorter than the TLP pulse width.  Figure 7 shows the schematic of the whole-chip ESD protection network with TFETs, where the TFETs are connected to an input/output (I/O) pad instead of traditional diodes. The clamp circuit consists of a trigger circuit and a big MOSFET. The trigger circuit is implemented via a resistive-capacitive (RC) network with a 500 ns time constant, which ensures that the big MOSFET is in ON-state during the whole ESD event. The equivalent resistance of the metal wires is also considered.

Whole-chip ESD Protection Network with Different TFETs
In the whole-chip ESD protection, the pin-to-pin protection has the longest path and, therefore, the lowest robustness. The TFET is introduced to enhance the robustness, as shown in Figure 7. When the ESD current flows from pin1 to pin2, three discharge paths exist, i.e., the primary path path1-path3-path5 (Pp), the secondary path path2-path5 (Ps1) and path1-path4 (Ps2). Since TFET1 and TFET4 operate as positive biased p-n diodes, Pp has a relatively low conduction voltage and is the primary path. On the other hand, Ps1 and Ps2 with relatively high conduction voltages form the secondary paths. In the simulations, the TFETs and MOSFET have widths of 200 and 600 μm, respectively. The results reveal that, as expected, the trigger voltage trend is the same as that obtained in the TLP simulation. However, the failure current of the line TFET is almost identical to that of the point TFET. This is because when the device is fully turned on, the BTBT current is no longer the dominant factor affecting the current conduction. The Ge-Source TFET still performs better than the other two TFETs. It should be mentioned that the failure current for the VFTLP simulation is higher than that for the TLP simulation because the VFTLP pulse width is significantly shorter than the TLP pulse width. Figure 7 shows the schematic of the whole-chip ESD protection network with TFETs, where the TFETs are connected to an input/output (I/O) pad instead of traditional diodes. The clamp circuit consists of a trigger circuit and a big MOSFET. The trigger circuit is implemented via a resistive-capacitive (RC) network with a 500 ns time constant, which ensures that the big MOSFET is in ON-state during the whole ESD event. The equivalent resistance of the metal wires is also considered.

Basic TLP Simulation Results
A TLP current having an amplitude of 0.8 A is applied to the whole-chip protection  In the whole-chip ESD protection, the pin-to-pin protection has the longest path and, therefore, the lowest robustness. The TFET is introduced to enhance the robustness, as shown in Figure 7. When the ESD current flows from pin1 to pin2, three discharge paths exist, i.e., the primary path path1-path3-path5 (P p ), the secondary path path2-path5 (P s1 ) and path1-path4 (P s2 ). Since TFET1 and TFET4 operate as positive biased p-n diodes, P p has a relatively low conduction voltage and is the primary path. On the other hand, P s1 and P s2 with relatively high conduction voltages form the secondary paths. In the simulations, the TFETs and MOSFET have widths of 200 and 600 µm, respectively.

Basic TLP Simulation Results
A TLP current having an amplitude of 0.8 A is applied to the whole-chip protection networks with three different TFETs. Figure 8 shows the node voltage and path current at 20 ns. It can be observed that the clamping voltage is 5.01 V for the Ge-source TFET-based protection network, whereas the voltages are 6.64 and 6.68 V for the line and point TFET counterparts, respectively. This difference is due to a higher conduction of the current (0.23 A) by the Ge-source TFET compared to the line TFET (15.18 mA) and point TFET (1.38 mA). The point and line TFET-based protection networks pass the 0.8 A TLP test. The corresponding maximal temperatures are 1090 and 1066 K, respectively, which are lower than the default silicon failure temperature of 1200 K. On the contrary, the Ge-source TFET fails because the maximal temperature in the TFET reaches the default Ge failure temperature of 890 K at 55 ns, as shown in Figure 9. In fact, the failure current of the Ge-source TFET-based protection network is only 0.5 A.

Basic TLP Simulation Results
A TLP current having an amplitude of 0.8 A is applied to the whole-chip protection networks with three different TFETs. Figure 8 shows the node voltage and path current at 20 ns. It can be observed that the clamping voltage is 5.01 V for the Ge-source TFET-based protection network, whereas the voltages are 6.64 and 6.68 V for the line and point TFET counterparts, respectively. This difference is due to a higher conduction of the current (0.23 A) by the Ge-source TFET compared to the line TFET (15.18 mA) and point TFET (1.38 mA). The point and line TFET-based protection networks pass the 0.8 A TLP test. The corresponding maximal temperatures are 1090 and 1066 K, respectively, which are lower than the default silicon failure temperature of 1200 K. On the contrary, the Gesource TFET fails because the maximal temperature in the TFET reaches the default Ge failure temperature of 890 K at 55 ns, as shown in Figure 9. In fact, the failure current of the Ge-source TFET-based protection network is only 0.5 A.

Thermal Instability of TFET-Based Protection Network
The early failure of the Ge-source TFET reduces the whole-chip ESD robustness, mainly because the Ge-source TFET has a low clamping voltage and excessive current flows through it. From Figure 8c, it can be noted that the Ge-source TFET discharges a current as high as 1.15 mA/μm, while its failure current is only 0.64 mA/μm, as shown in Figure 5. A large amount of current flows from the TFETs to the ground, generating excessive heat and causing failure. This behavior indicates that the TFET-based protection network has low thermal instability. As for the single device's ESD robustness, the Gesource TFET is better than the point and line TFETs. However, in the whole-chip ESD protection network, the current distribution significantly affects the failure location and determines the overall robustness. In the whole-chip protection network design, the TFETs should be properly designed to guarantee that the failure location appears in the MOSFET.

Optimization of the TFET-Based Protection Network
A ballast resistor is often introduced to improve the non-uniform conduction phenomenon in ESD protection [20]. However, this method is not suitable for the TFET-based whole-chip protection network because every TFET should have a ballast resistor, which significantly increases the serial resistance in the whole protection network and reduces the overall ESD robustness. An available solution is to reduce the Ge mole fraction in the source region, namely, using the silicon-germanium (SiGe) material rather than pure Ge

Thermal Instability of TFET-Based Protection Network
The early failure of the Ge-source TFET reduces the whole-chip ESD robustness, mainly because the Ge-source TFET has a low clamping voltage and excessive current flows through it. From Figure 8c, it can be noted that the Ge-source TFET discharges a current as high as 1.15 mA/μm, while its failure current is only 0.64 mA/μm, as shown in Figure 5. A large amount of current flows from the TFETs to the ground, generating excessive heat and causing failure. This behavior indicates that the TFET-based protection network has low thermal instability. As for the single device's ESD robustness, the Gesource TFET is better than the point and line TFETs. However, in the whole-chip ESD protection network, the current distribution significantly affects the failure location and determines the overall robustness. In the whole-chip protection network design, the TFETs should be properly designed to guarantee that the failure location appears in the MOSFET.

Optimization of the TFET-Based Protection Network
A ballast resistor is often introduced to improve the non-uniform conduction phenomenon in ESD protection [20]. However, this method is not suitable for the TFET-based whole-chip protection network because every TFET should have a ballast resistor, which significantly increases the serial resistance in the whole protection network and reduces the overall ESD robustness. An available solution is to reduce the Ge mole fraction in the source region, namely, using the silicon-germanium (SiGe) material rather than pure Ge

Thermal Instability of TFET-Based Protection Network
The early failure of the Ge-source TFET reduces the whole-chip ESD robustness, mainly because the Ge-source TFET has a low clamping voltage and excessive current flows through it. From Figure 8c, it can be noted that the Ge-source TFET discharges a current as high as 1.15 mA/µm, while its failure current is only 0.64 mA/µm, as shown in Figure 5. A large amount of current flows from the TFETs to the ground, generating excessive heat and causing failure. This behavior indicates that the TFET-based protection network has low thermal instability. As for the single device's ESD robustness, the Gesource TFET is better than the point and line TFETs. However, in the whole-chip ESD protection network, the current distribution significantly affects the failure location and determines the overall robustness. In the whole-chip protection network design, the TFETs should be properly designed to guarantee that the failure location appears in the MOSFET.

Optimization of the TFET-Based Protection Network
A ballast resistor is often introduced to improve the non-uniform conduction phenomenon in ESD protection [20]. However, this method is not suitable for the TFET-based whole-chip protection network because every TFET should have a ballast resistor, which significantly increases the serial resistance in the whole protection network and reduces the overall ESD robustness. An available solution is to reduce the Ge mole fraction in the source region, namely, using the silicon-germanium (SiGe) material rather than pure Ge in Crystals 2021, 11, 128 9 of 11 the source region. This reduction decreases the BTBT generation rate and impact ionization coefficient and, in turn, increases the breakdown voltage. Figure 10 shows the node voltage and path current of the SiGe-source TFET-based ESD protection network under a 0.8 A current TLP simulation, in which the Ge mole fraction was set to 0.5. It can be noted that the clamping voltage increases from 5.01 to 6.11 V compared to the pure Ge-source TFET. However, this voltage is still lower than those in the point and line TFETs. As the SiGe-source TFETs conduct proper currents, the protection network does not fail even under a 1.1 A TLP simulation. The TFET and MOSFET maximal temperatures are 699 and 1150 K, respectively. Figure 11 shows the node voltage and path current under a 1.2 A TLP simulation. It can be observed that the Pin1 voltage starts to decrease and the current flowing through the MOSFET starts to increase at around 80 ns, indicating that thermal breakdown occurs in the MOSFET rather than the TFETs. A comparison of the four protection networks is shown in Table 1. rystals 2021, 11, x FOR PEER REVIEW 9 in the source region. This reduction decreases the BTBT generation rate and impact zation coefficient and, in turn, increases the breakdown voltage. Figure 10 shows the node voltage and path current of the SiGe-source TFET-b ESD protection network under a 0.8 A current TLP simulation, in which the Ge mole tion was set to 0.5. It can be noted that the clamping voltage increases from 5.01 to 6 compared to the pure Ge-source TFET. However, this voltage is still lower than tho the point and line TFETs. As the SiGe-source TFETs conduct proper currents, the pr tion network does not fail even under a 1.1 A TLP simulation. The TFET and MO maximal temperatures are 699 and 1150 K, respectively. Figure 11 shows the node vo and path current under a 1.2 A TLP simulation. It can be observed that the Pin1 vo starts to decrease and the current flowing through the MOSFET starts to increa around 80 ns, indicating that thermal breakdown occurs in the MOSFET rather tha TFETs. A comparison of the four protection networks is shown in Table 1.  Figure 10. Transmission line pulse response of the SiGe-source TFET-based ESD network.   Crystals 2021, 11, x FOR PEER REVIEW in the source region. This reduction decreases the BTBT generation rate and impa zation coefficient and, in turn, increases the breakdown voltage. Figure 10 shows the node voltage and path current of the SiGe-source TFE ESD protection network under a 0.8 A current TLP simulation, in which the Ge m tion was set to 0.5. It can be noted that the clamping voltage increases from 5.01 t compared to the pure Ge-source TFET. However, this voltage is still lower than the point and line TFETs. As the SiGe-source TFETs conduct proper currents, the tion network does not fail even under a 1.1 A TLP simulation. The TFET and M maximal temperatures are 699 and 1150 K, respectively. Figure 11 shows the node and path current under a 1.2 A TLP simulation. It can be observed that the Pin1 starts to decrease and the current flowing through the MOSFET starts to inc around 80 ns, indicating that thermal breakdown occurs in the MOSFET rather t TFETs. A comparison of the four protection networks is shown in Table 1.

Conclusions
In this paper, the ESD characteristics of a point TFET, a line TFET and a Ge-source TFET were compared and their application in a whole-chip ESD protection network was evaluated using TCAD simulations. It was found that the Ge-source TFET had the best single-device ESD characteristics, especially a very low clamping voltage. However, in the whole-chip ESD protection, the Ge-source TFET-based network had the lowest robustness. This is because the Ge-source TFET had a very low clamping voltage and conducted excessive current, resulting in an early thermal failure. Simulation results show that a reduction in the Ge mole fraction in the source region limited the current flowing through the TFET, in turn increasing the whole-chip ESD robustness.