Heteroepitaxial Growth of III-V Semiconductors on Silicon

Monolithic integration of III-V semiconductor devices on Silicon (Si) has long been of great interest in photonic integrated circuits (PICs), as well as traditional integrated circuits (ICs), since it provides enormous potential benefits, including versatile functionality, low-cost, large-area production, and dense integration. However, the material dissimilarity between III-V and Si, such as lattice constant, coefficient of thermal expansion, and polarity, introduces a high density of various defects during the growth of III-V on Si. In order to tackle these issues, a variety of growth techniques have been developed so far, leading to the demonstration of high-quality III-V materials and optoelectronic devices monolithically grown on various Si-based platform. In this paper, the recent advances in the heteroepitaxial growth of III-V on Si substrates, particularly GaAs and InP, are discussed. After introducing the fundamental and technical challenges for III-V-on-Si heteroepitaxy, we discuss recent approaches for resolving growth issues and future direction towards monolithic integration of III-V on Si platform.


Introduction
Silicon (Si) has long been of great importance in a wide range of micro/nanoelectronics industry because it offers numerous benefits, such as large wafer size, low cost, abundant source, and mature manufacturing technology [1]. Indeed, for instance, Si-based complementary metal-oxide-semiconductor (CMOS) technology is the fundamental building block in most of the contemporary electronics [2,3], and Si has also been one of the dominant prime materials for photovoltaic technology since the 1950s [4]. More importantly, the utility of Si has expanded from traditional electronics to next-generation photonics industry as Si photonics, enabling ultra-fast and low-cost optical data transmission on Si-on-insulator (SOI) platform compatible with a CMOS process, has emerged recently [5]. Unfortunately, however, bulk Si material is an indirect bandgap semiconductor and hence very inefficient for light emission. Although Si-based light-emitting devices, such as Si Raman laser [6,7] and p-n junction emitter [8][9][10], have been developed, their performances are impractical and far less than those of III-V devices [11,12]. On the other hand, most III-V semiconductors provide superior optoelectronic properties owing to their direct bandgap and high electron mobility properties. These advantages enable the III-V semiconductors to be widely used in light-emitting/absorbing devices, including light-emitting diodes (LEDs), lasers, detectors, and solar cells [13][14][15][16]. In addition, the III-V materials have been employed for power devices, such as high electron mobility transistor (HEMT) [17,18]. However, the limited wafer size of III-V materials (3 or 4 inch), which increases manufacturing cost, is a critical drawback. In addition, the use of III-V semiconductors requires careful attention due to their toxicity [19], and despite the advances in the InP-based PICs [20,21],

Threading Dislocation
Second, the TDs originating from the large lattice mismatch between III-V and Si is also an important issue [28,[76][77][78]. The lattice constant mismatch, e.g., 4% (8%) between GaAs (InP) and Si, introduces a build-up of strain energy on the epitaxial layer during the growth. If the thickness of III-V epilayer on Si exceeds a certain value, the so-called critical thickness, the accumulated strain energy proportional to the thickness of epilayer is released via the formation of misfit dislocations (MDs) along the heterointerface and TDs toward the surface. Matthews et al. [76] described a theoretical model for the critical thickness of epilayer. In this model, it is assumed that a pre-existing dislocation in substrate is replicated in the epitaxial layer and glides back and forth by the misfit strain to create misfit dislocation at the interface. The critical thickness ℎ is found to be where is the length of the Burgers vector for the dislocation, is the Poisson ratio, is the angle between the dislocation line and its Burgers vector, is the lattice mismatch strain, and is the angle between the slip plane and the line in the film plane that is perpendicular to the intersection line of the slip plane and interface.
As the line defects cannot be naturally terminated within the crystal lattice, the MDs along the heterointerface can reach the edge of epilayer or merge with pre-existing TDs within the substrate. In addition, the MDs can form the dislocation half-loop, introducing additional TDs which penetrate the whole layer and reach the surface. Because the dislocation half-loop is likely to be nucleated at pre-existing crystal defects, it is also important to control the crystal imperfection during the growth. It is well known that the TDs introduce the electronic state in the bandgap of III-V semiconductor which acts as nonradiative recombination centers.
The density of TDs is very important and straightforward parameter which describes the quality of epitaxial layer. There are three common approaches used to measure the TDD of III-V epitaxial layer [79][80][81]: (1) Etch-pit density (EPD) measurement; (2) Transmission electron microscopy (TEM) measurement; (3) X-ray diffraction (XRD) measurement. First, for EPD measurement, etching solution is applied to the semiconductors. Because the etching rate at the dislocation is higher than that at crystalline region, the pits around TDs are formed and thereby can be easily counted by optical observation or atomic force microscopy (AFM). The EPD measurement is very easy, quick, and cheap process, but it tends to underestimate the TDD. Moreover, quantitative analyses, such as Burgers vector determination, are impossible. Second, TEM measurement enables direct observation of TDs

Threading Dislocation
Second, the TDs originating from the large lattice mismatch between III-V and Si is also an important issue [28,[76][77][78]. The lattice constant mismatch, e.g., 4% (8%) between GaAs (InP) and Si, introduces a build-up of strain energy on the epitaxial layer during the growth. If the thickness of III-V epilayer on Si exceeds a certain value, the so-called critical thickness, the accumulated strain energy proportional to the thickness of epilayer is released via the formation of misfit dislocations (MDs) along the heterointerface and TDs toward the surface. Matthews et al. [76] described a theoretical model for the critical thickness of epilayer. In this model, it is assumed that a pre-existing dislocation in substrate is replicated in the epitaxial layer and glides back and forth by the misfit strain to create misfit dislocation at the interface. The critical thickness h c is found to be where b is the length of the Burgers vector for the dislocation, ν is the Poisson ratio, α is the angle between the dislocation line and its Burgers vector, f is the lattice mismatch strain, and λ is the angle between the slip plane and the line in the film plane that is perpendicular to the intersection line of the slip plane and interface. As the line defects cannot be naturally terminated within the crystal lattice, the MDs along the heterointerface can reach the edge of epilayer or merge with pre-existing TDs within the substrate. In addition, the MDs can form the dislocation half-loop, introducing additional TDs which penetrate the whole layer and reach the surface. Because the dislocation half-loop is likely to be nucleated at pre-existing crystal defects, it is also important to control the crystal imperfection during the growth. It is well known that the TDs introduce the electronic state in the bandgap of III-V semiconductor which acts as nonradiative recombination centers.
The density of TDs is very important and straightforward parameter which describes the quality of epitaxial layer. There are three common approaches used to measure the TDD of III-V epitaxial layer [79][80][81]: (1) Etch-pit density (EPD) measurement; (2) Transmission electron microscopy (TEM) measurement; (3) X-ray diffraction (XRD) measurement. First, for EPD measurement, etching solution is applied to the semiconductors. Because the etching rate at the dislocation is higher than that Crystals 2020, 10, 1163 5 of 36 at crystalline region, the pits around TDs are formed and thereby can be easily counted by optical observation or atomic force microscopy (AFM). The EPD measurement is very easy, quick, and cheap process, but it tends to underestimate the TDD. Moreover, quantitative analyses, such as Burgers vector determination, are impossible. Second, TEM measurement enables direct observation of TDs and quantitative analysis. However, an accurate analysis is restricted only to the highly defected crystals because of the small volume of the examined sample. Last, unlike the EPD and TEM measurements, XRD provides non-destructive measurement of TDD in the range from 10 5 to 10 9 cm −2 . It is possible to calculate the TDD by measuring a few (hkl) rocking curve widths, because dislocations broaden the rocking curve. Gay et al. [82] and Ayers [81] introduced the theory for the measurement of TDD in metals and (001) zinc-blende semiconductors, respectively.

Thermal Crack
Finally, a large difference in coefficient of thermal expansion (CTE) causes the introduction of a thermal strain during any temperature changing process [83,84]. In particular, when the wafer cooled down from III-V growth temperature (580 • C for GaAs) to room temperature (RT), the accumulated thermal strain is likely to be relaxed by forming thermal cracks. The thermal cracks can be easily found in the GaAs-on-Si heteroepitaxy, where the GaAs has a larger CTE than Si (6.6 × 10 −6 K −1 and 2.3 × 10 −6 K −1 for GaAs and Si, respectively), because a tensile strain is applied to the epitaxial layer during the cool-down process. Griffith [85] first proposed the simple fracture model of brittle materials for predicting the onset of crack growth. In this model, the critical thickness of heteroepitaxial layer under tensile strain can be approximated. The derived condition for crack propagation is [86][87][88] where h G is the thickness of epitaxial layer, Y is the biaxial modulus, γ is the surface energy per unit area for semiconductor, and ε is the in-plane tensile strain. If the surface energy for the favorable (110) crack plane in zinc-blende structure is approximated by γ(110) = Y(1 − ν)a/2 √ 2π 2 , the Griffith criterion for crack propagation in the (001) heteroepitaxy of a zinc-blende semiconductor becomes [88] where a is the lattice constant, and ν is the Poisson ratio. The Griffith criterion describes the condition for crack propagation, rather than for crack formation, under pre-existing cracks. Nonetheless, because the presence of any imperfections in the epitaxial layer also affects the crack formation [89], the thickness at which the crack forms may be close to the Griffith thickness h G [88]. A wide variety of theoretical models which describe the condition for crack formation can be found elsewhere [90,91].
In general, thermal crack lines exactly parallel or perpendicular to each other appear in the III-V epitaxial layer [92]. This can be explained by the unique <110> {111} slip system in zinc-blende III-V semiconductors. In case of zinc-blende III-V grown on (001) oriented substrates, most of misfit dislocations are 60 • dislocations. Particularly, two types of misfit dislocations are preferred, α and β, lying along two orthogonal <110> directions at the interface, due to the asymmetry of zinc-blende crystal structure [93][94][95]. At the interface under tensile strain, the α (group V atom core) and β (group III atom core) dislocations have [110] and 110 line direction, respectively. The directions of these dislocations are reversed at the interface under compressive stress. In addition, the asymmetric cracking occurs in III-V epitaxial layer, which means that the density of two orthogonal cracks is quite different [91,93,95,96]. During the early stage of crack formation, cracks with one of <110> directions are dominant. However, if the epitaxial layer is far thicker than the critical thickness of crack formation, Crystals 2020, 10, 1163 6 of 36 orthogonal crack lines are commonly observed. This can be ascribed mainly to the difference in glide velocity of α and β dislocations [97].
In addition, as the crack nucleation originates from other pre-existing defects, the presence of any imperfections in the epitaxial layer also affects the crack formation [89]. Like other defects, the presence of thermal cracks introduces destructive effects on the quality of III-V epilayer and performance of optoelectronic devices, such as light scattering centers, electrical leakage path, and limitation on the total thickness of epilayer [98]. More importantly, like the APBs, high density of thermal cracks significantly reduces the yield of device fabrication.
For the GaAs-on-Si, thermal cracks begin to propagate if the thickness of GaAs exceeds about 3 µm, and the number of cracks increases as the thickness increases [89]. As shown in Figure 2a, the cracks appear predominantly in only one of <110> direction when the thickness of GaAs is close to the critical thickness for crack formation. For the thick GaAs (8.1 µm) layer far beyond critical thickness, high density of cracks in two orthogonal directions can be observed, as in Figure 2b. limitation on the total thickness of epilayer [98]. More importantly, like the APBs, high density of thermal cracks significantly reduces the yield of device fabrication. For the GaAs-on-Si, thermal cracks begin to propagate if the thickness of GaAs exceeds about 3 μm, and the number of cracks increases as the thickness increases [89]. As shown in Figure 2a, the cracks appear predominantly in only one of <110> direction when the thickness of GaAs is close to the critical thickness for crack formation. For the thick GaAs (8.1 μm) layer far beyond critical thickness, high density of cracks in two orthogonal directions can be observed, as in Figure 2b. For InP-on-Si, on the other hand, the issue of thermal cracks is not as critical as in GaAs-on-Si growth. It was reported that the thermally-induced tensile stress in InP film on Si was much less than that in GaAs film on Si [99]. This can be attributed to the fact that the InP has lower growth temperature and a smaller difference of CTE from Si, compared with GaAs. Additionally, the rearrangement of misfit dislocations in InP, partially accommodating the thermally-induced stress during the cooling process, occurs at relatively low temperature (~250 °C).

APB-Free III-V on Silicon
To obtain a single domain of III-V materials on Si is prerequisite for growing high-quality III-V layer because the APBs, the planar defect, propagate from the heterointerface to the surface. Indeed, the presence of APBs makes it almost impossible to fabricate and operate optoelectronic devices. This section will introduce several methods to achieve APB-free III-V layer on Si substrates, mainly focusing on the use of on-axis (001) Si substrates. This is because most of modern ICs and PICs industry uses CMOS-compatible on-axis (001) Si substrates.

Offcut Silicon Substrates
It is well known that the use of offcut Si substrates with various angles from 4° to 7° is effective in suppression of the formation of APBs [100][101][102][103]. As mentioned in Section 2.1, the monatomic steps of the Si(001) surface consist of two alternating (2 × 1) and (1 × 2) dimerization. However, it was observed that the misoriented Si with an offcut angle larger than 4˚ experienced the surface reconstruction after proper annealing process, yielding a (2 × 1) single domain [73,74,104,105]. In this case, the Si-Si dimers are parallel to the upper terrace, and the steps are predominantly double-atomic steps. This reconstruction can be explained by the formation energy [74]. The monatomic steps are found to have lowest formation energy, but the formation of double-atomic steps is energetically For InP-on-Si, on the other hand, the issue of thermal cracks is not as critical as in GaAs-on-Si growth. It was reported that the thermally-induced tensile stress in InP film on Si was much less than that in GaAs film on Si [99]. This can be attributed to the fact that the InP has lower growth temperature and a smaller difference of CTE from Si, compared with GaAs. Additionally, the rearrangement of misfit dislocations in InP, partially accommodating the thermally-induced stress during the cooling process, occurs at relatively low temperature (~250 • C).

APB-Free III-V on Silicon
To obtain a single domain of III-V materials on Si is prerequisite for growing high-quality III-V layer because the APBs, the planar defect, propagate from the heterointerface to the surface. Indeed, the presence of APBs makes it almost impossible to fabricate and operate optoelectronic devices. This section will introduce several methods to achieve APB-free III-V layer on Si substrates, mainly focusing on the use of on-axis (001) Si substrates. This is because most of modern ICs and PICs industry uses CMOS-compatible on-axis (001) Si substrates.

Offcut Silicon Substrates
It is well known that the use of offcut Si substrates with various angles from 4 • to 7 • is effective in suppression of the formation of APBs [100][101][102][103]. As mentioned in Section 2.1, the monatomic steps of the Si(001) surface consist of two alternating (2 × 1) and (1 × 2) dimerization. However, it was observed that the misoriented Si with an offcut angle larger than 4 • experienced the surface Crystals 2020, 10, 1163 7 of 36 reconstruction after proper annealing process, yielding a (2 × 1) single domain [73,74,104,105]. In this case, the Si-Si dimers are parallel to the upper terrace, and the steps are predominantly double-atomic steps. This reconstruction can be explained by the formation energy [74]. The monatomic steps are found to have lowest formation energy, but the formation of double-atomic steps is energetically preferred on the misoriented surface towards [110] or 110 direction, in which the monatomic steps with dimers parallel and perpendicular to the upper terrace alternate. Therefore, the surface reconstruction in the offcut Si(001) is necessary to obtain the single domain of III-V layer on Si [106][107][108][109]. However, the formation of double-atomic step doesn't always guarantee the APB-free III-V epitaxial layer on Si. Bringans et al. [110] reported the surface rearrangement of Si(001) by interaction with arsenic. On the double-atomic stepped Si(001) with a (2 × 1) single dimerization, applying As 4 flux leads to the formation of a monolayer of As-As dimers, depending on the As 4 flux exposure conditions. The orientation of As dimers can be parallel or perpendicular to the step edge, which can affect the nucleation of GaAs. To obtain the III-V single domain on Si, therefore, As or Ga pre-layer, as well as surface reconstruction, should be considered [111][112][113][114].
By using offcut Si substrates, high-quality III-V layers on Si without APBs have been successfully demonstrated [16,48,49]. However, the offcut Si substrates are incompatible with CMOS, as well as advanced Si manufacturing technologies. Moreover, recent booming development of Si photonics accelerates the necessity of CMOS-compatible on-axis (001) Si substrates. Unlike the offcut Si, it is very difficult to obtain the single domain of III-V on on-axis Si due to the difficulty in the reconstruction of monatomic steps, and therefore recent research focus of III-V-on-Si heteroepitaxy moved towards the growth of III-V on the CMOS-compatible on-axis (001) Si substrate.

Selective Area Growth
The selective-area growth (SAG), allowing the epitaxial layer to grow on the pre-defined region, has been intensively developed due to its unique defect reduction property, the so-called aspect ratio trapping (ART) [115][116][117][118] or necking effect [119,120]. The basic concept of SAG is to trap the defects inside the sidewalls of patterned dielectric mask materials, typically SiO 2 , on Si substrates. Unlike the bulk growth, for the SAG technique, more complex growth parameters, as well as the optimization of mask pattern design, are required to achieve high-quality selective growth because of the reduced dimensions and confined structures [26]. Nonetheless, the SAG is very effective in reducing the density of defects if the dielectric mask pattern has enough aspect ratio (h/w where h and w indicate mask height and width, respectively). As shown in Figure 3, the TD segments are likely to glide along the {111} slip plane, which forms an angle of 54.7 • with the 110 orientation during the growth. Hence, the TD segments on the {111} slip plane, reaching the oxide sidewall, are trapped, regardless of whether the {111} slip plane is parallel or perpendicular to the trench orientation. In addition, the angle of 54.7 • determines the minimum aspect ratio (at least 1.43) for trapping the TDs on the {111} slip plane. The SAG using trench structures also traps the planar defects, namely the APBs, in a similar way of TDs. However, only planar defects formed on the {111} plane parallel to the trench orientation can be trapped, as shown in the third case of Figure 3. In other words, the planar defects on planes perpendicular to the trench orientation will not be trapped. However, Orzali et al. [121], who employed the chemically etched V-shaped Si surface for defect reduction, reported that the nucleation of GaAs initiated only on the etched {111} Si plane contributed to the prevention of APB formation.
Even though many SAG techniques have shown their capability of reducing the density of defects, the APB issue is not fully resolved. In order to address APB and rough surface issues, growing III-V materials on the chemically etched (111) Si surface with nanowire coalescence was proposed [122,123]. For example, Li et al. [123] reported GaAs-on-V-grooved Si (GoVS) templates which offered APB-free flat GaAs layer on on-axis (001) Si substrates. To obtain GoVS template, n-type on-axis (001) Si substrates patterned with SiO 2 stripe were chemically etched by potassium hydroxide (KOH) solution to form trench structure exposing (111) facets, and subsequently the GaAs nanowires were selectively grown on the V-grooved Si by metal-organic chemical vapor deposition (MOCVD). After removing the SiO 2 stripe pattern, coalesced GaAs thin films were regrown on the nanowire arrays. Figure 4a shows a scanning electron microscopy (SEM) image of the resultant coalesced GaAs layer with a flat surface. The surface morphology of 300 nm-thick coalesced GaAs layer measured by atomic-force microscopy (AFM) produced a root-mean-square (rms) of 1.9 nm across a scanned area of 5 × 5 µm 2 . The APBs were not observed in the GoVS template, which can be explained by the III-V growth on Si {111} plane. A transmission electron microscopy (TEM) image in Figure 4b presents a unique stacking fault trapping. It was shown that a tiara-like structure beneath the SiO 2 sidewall, created by Si undercutting, effectively trapped most of the stacking faults around the interface of GaAs/Si (111). Owing to this unique trapping mechanism, after removing the SiO 2 , the subsequent GaAs overgrowth can be performed with maintaining the ability of defect trapping, as shown in Figure 4c. Although some of stacking faults can escape the tiara-like structure in the thick stacking-disorder regions, the escaped stacking faults can be annihilated by crossing of two stacking faults due to the closely spaced V-groove structure. bulk growth, for the SAG technique, more complex growth parameters, as well as the optimization of mask pattern design, are required to achieve high-quality selective growth because of the reduced dimensions and confined structures [26]. Nonetheless, the SAG is very effective in reducing the density of defects if the dielectric mask pattern has enough aspect ratio (h/w where h and w indicate mask height and width, respectively). As shown in Figure 3, the TD segments are likely to glide along the 111 slip plane, which forms an angle of 54.7° with the 110 orientation during the growth. Hence, the TD segments on the 111 slip plane, reaching the oxide sidewall, are trapped, regardless of whether the 111 slip plane is parallel or perpendicular to the trench orientation. In addition, the angle of 54.7° determines the minimum aspect ratio (at least 1.43) for trapping the TDs on the 111 slip plane. The SAG using trench structures also traps the planar defects, namely the APBs, in a similar way of TDs. However, only planar defects formed on the 111 plane parallel to the trench orientation can be trapped, as shown in the third case of Figure 3. In other words, the planar defects on planes perpendicular to the trench orientation will not be trapped. However, Orzali et al. [121], who employed the chemically etched V-shaped Si surface for defect reduction, reported that the nucleation of GaAs initiated only on the etched {111} Si plane contributed to the prevention of APB formation.   Even though many SAG techniques have shown their capability of reducing the density of defects, the APB issue is not fully resolved. In order to address APB and rough surface issues, growing III-V materials on the chemically etched (111) Si surface with nanowire coalescence was proposed [122,123]. For example, Li et al. [123] reported GaAs-on-V-grooved Si (GoVS) templates which offered APB-free flat GaAs layer on on-axis (001) Si substrates. To obtain GoVS template, ntype on-axis (001) Si substrates patterned with SiO2 stripe were chemically etched by potassium hydroxide (KOH) solution to form trench structure exposing (111) facets, and subsequently the GaAs nanowires were selectively grown on the V-grooved Si by metal-organic chemical vapor deposition (MOCVD). After removing the SiO2 stripe pattern, coalesced GaAs thin films were regrown on the nanowire arrays. Figure 4a shows a scanning electron microscopy (SEM) image of the resultant coalesced GaAs layer with a flat surface. The surface morphology of 300 nm-thick coalesced GaAs layer measured by atomic-force microscopy (AFM) produced a root-mean-square (rms) of 1.9 nm across a scanned area of 5 × 5 μm 2 . The APBs were not observed in the GoVS template, which can be explained by the III-V growth on Si {111} plane. A transmission electron microscopy (TEM) image in Figure 4b presents a unique stacking fault trapping. It was shown that a tiara-like structure beneath the SiO2 sidewall, created by Si undercutting, effectively trapped most of the stacking faults around the interface of GaAs/Si (111). Owing to this unique trapping mechanism, after removing the SiO2, the subsequent GaAs overgrowth can be performed with maintaining the ability of defect trapping, as shown in Figure 4c. Although some of stacking faults can escape the tiara-like structure in the thick stacking-disorder regions, the escaped stacking faults can be annihilated by crossing of two stacking faults due to the closely spaced V-groove structure. For the InP growth on on-axis Si, Zhu et al. [124], investigating the APB-free InP-on-grooved Si (IoVS) templates similar to the GoVS, demonstrated electrically pumped 1.5-μm InGaAs/InAlGaAs laser monolithically grown on IoVS template. The method for obtaining IoVS template is very similar to that of GoVS. A main difference is that a 10 nm-thick GaAs wetting layer was grown on the exposed (111) Si facets before the InP nanowire growth. This is because employing GaAs wetting layer reduces a strain for InP growth and prevents InP seed layer from being clustered.

MOCVD/MOVPE-Grown Buffer Layer
Alcotte et al. [125] developed APB-free GaAs layer directly grown on nominal (001) Si substrates For the InP growth on on-axis Si, Zhu et al. [124], investigating the APB-free InP-on-grooved Si (IoVS) templates similar to the GoVS, demonstrated electrically pumped 1.5-µm InGaAs/InAlGaAs laser monolithically grown on IoVS template. The method for obtaining IoVS template is very similar to that of GoVS. A main difference is that a 10 nm-thick GaAs wetting layer was grown on the exposed Crystals 2020, 10, 1163 9 of 36 (111) Si facets before the InP nanowire growth. This is because employing GaAs wetting layer reduces a strain for InP growth and prevents InP seed layer from being clustered.

MOCVD/MOVPE-Grown Buffer Layer
Alcotte et al. [125] developed APB-free GaAs layer directly grown on nominal (001) Si substrates without the SAG. In this work, microelectronics standard nominal (001) Si 300 mm wafers, first deoxidized in a SiConi TM chamber with NF 3 /NH 3 remote plasma, were subsequently transferred into the MOCVD chamber and annealed at high temperature (800 • C~950 • C) in H 2 ambient. This optimized preparation promotes reconstructing the 2 × 1 surface, namely the formation of double atomic steps, which is believed to be a crucial step for inhibiting the formation of APBs. In Figure 5a, the AFM image of a 400 nm-thick GaAs grown on unoptimized Si shows a high density of randomly distributed APBs. In contrast, the optimized Si surface mainly consists of double atomic steps (Figure 5b), and the APBs were not observed in the 150 nm-thick GaAs layer grown on optimized Si ( Figure 5c). In addition, the surface roughness of 150 nm GaAs layer grown on optimized Si was measured to be 0.8 nm rms, corresponding to the lowest value reported for 1 µm-thick GaAs grown on offcut Si substrates.
Crystals 2020, 10, x FOR PEER REVIEW 9 of 40 5b), and the APBs were not observed in the 150 nm-thick GaAs layer grown on optimized Si ( Figure  5c). In addition, the surface roughness of 150 nm GaAs layer grown on optimized Si was measured to be 0.8 nm rms, corresponding to the lowest value reported for 1 μm-thick GaAs grown on offcut Si substrates. In addition to the GaAs/Si, Volz et al. [126] also demonstrated the APB-free GaP/Si template using homoepitaxial Si buffer and heteroepitaxial GaP buffer layer grown by vapor phase epitaxy (VPE) and metal-organic vapor phase epitaxy (MOVPE), respectively. To obtain APB-free GaP/Si template, the 500 nm-thick homoepitaxial Si buffer layer was first grown on deoxidized on-axis (001) Si at 200 mbar and 850 °C, where the optimized post-annealing (10 min, 950 mbar H2, 975 °C) process was subsequently performed. In Figure 6a, the AFM image of the annealed Si buffer surface confirms the formation of double-atomic steps (0.27 nm height), which is believed to be responsible for preventing APB nucleation. Then, the GaP layer was grown on the prepared Si buffer layer in a twostep procedure consisting of a nucleation and an overgrowth. For the optimal growth of GaP nucleation layer, flow-rate modulated epitaxy (FME) method, in which the Ga and P precursors are alternately injected into reactor, was employed. The low-temperature FME growth mode results in a two-dimensional continuous GaP nucleation layer, irrespective of whether Ga or P was first deposited. Figure 6b presents a TEM image of a continuous GaP nucleation layer grown by P-started FME method at 450 °C. In contrast, a continuously-injected nucleation forms three-dimensional GaP islands, which can evolve into stacking faults upon coalescence. After the growth of the optimal 3 nm GaP nucleation layer, bulk GaP layer was overgrown at 625 °C with continuous growth mode. As shown in Figure 6c, most of APBs are self-annihilated within 50 nm-thick GaP layers by kinking towards {111} plane or higher index plane. Consequently, the formation of double-atomic steps by the annealed homoepitaxial Si buffer contributed to the suppression of APB nucleation, and the two- In addition to the GaAs/Si, Volz et al. [126] also demonstrated the APB-free GaP/Si template using homoepitaxial Si buffer and heteroepitaxial GaP buffer layer grown by vapor phase epitaxy (VPE) and metal-organic vapor phase epitaxy (MOVPE), respectively. To obtain APB-free GaP/Si template, the 500 nm-thick homoepitaxial Si buffer layer was first grown on deoxidized on-axis (001) Si at 200 mbar and 850 • C, where the optimized post-annealing (10 min, 950 mbar H 2 , 975 • C) process was subsequently performed. In Figure 6a, the AFM image of the annealed Si buffer surface confirms the formation of double-atomic steps (0.27 nm height), which is believed to be responsible for preventing APB nucleation. Then, the GaP layer was grown on the prepared Si buffer layer in a two-step procedure consisting of a nucleation and an overgrowth. For the optimal growth of GaP nucleation layer, flow-rate modulated epitaxy (FME) method, in which the Ga and P precursors are alternately injected into reactor, was employed. The low-temperature FME growth mode results in a two-dimensional continuous GaP nucleation layer, irrespective of whether Ga or P was first deposited. Figure 6b presents a TEM image of a continuous GaP nucleation layer grown by P-started FME method at 450 • C. In contrast, a continuously-injected nucleation forms three-dimensional GaP islands, which can evolve into stacking faults upon coalescence. After the growth of the optimal 3 nm GaP nucleation layer, bulk GaP layer was overgrown at 625 • C with continuous growth mode. As shown in Figure 6c, most of APBs are self-annihilated within 50 nm-thick GaP layers by kinking towards {111} plane or higher index plane. Consequently, the formation of double-atomic steps by the annealed homoepitaxial Si buffer contributed to the suppression of APB nucleation, and the two-step GaP growth on the Si buffer consisting of low-temperature (LT) FME nucleation and high-temperature HT overgrowth enabled APBs to kink and self-annihilate with each other. FME method at 450 °C. In contrast, a continuously-injected nucleation forms three-dimensional GaP islands, which can evolve into stacking faults upon coalescence. After the growth of the optimal 3 nm GaP nucleation layer, bulk GaP layer was overgrown at 625 °C with continuous growth mode. As shown in Figure 6c, most of APBs are self-annihilated within 50 nm-thick GaP layers by kinking towards {111} plane or higher index plane. Consequently, the formation of double-atomic steps by the annealed homoepitaxial Si buffer contributed to the suppression of APB nucleation, and the twostep GaP growth on the Si buffer consisting of low-temperature (LT) FME nucleation and hightemperature HT overgrowth enabled APBs to kink and self-annihilate with each other.

MBE-Grown Buffer Layer
Most of the mature approaches for APB elimination employ MOCVD/MOVPE growth system to obtain virtual templates, such as GoVS, GaAs/Si, and GaP/Si. In general, these methods require pre-treatment under high temperature and high-pressure hydrogen before growth to promote the formation of double-atomic steps. On the other hand, solid-state molecular beam epitaxy (MBE) doesn't provide the hydrogen-based treatment. Nonetheless, all MBE-grown and APB-free III-V layer on on-axis Si is beneficial in terms of the low-cost and straightforward process because III-V devices grown on GaP/Si or GaAs/Si virtual substrates commonly use two different growth system, namely III-V and APB-free buffer growth by MBE and MOCVD/MOVPE, respectively. In addition, the MBE system has shown superior performance in growing high-quality InAs/GaAs QD lasers, which are promising Si-based light sources in Si photonics.
There have been only a few reports on the approaches using direct MBE growth without a virtual template. For example, Kwoen et al. [127], investigating the effect of AlGaAs nucleation layer on the elimination of APBs, demonstrated APB-free GaAs layer directly grown on on-axis (001) Si. In this paper, four different compositions of 40 nm-thick Al x Ga 1-x As nucleation layer was investigated, and subsequently 2.3 µm-thick GaAs buffer layer was grown. Figure 7a-d present the cross-sectional SEM images of GaAs/Si with Al x Ga 1−x As and GaAs nucleation layer. Unlike the GaAs/Si with Al 0.7 Ga 0.3 As seed layer in which APBs extended to GaAs surface (Figure 7d), the Al 0.3 Ga 0.7 As seed layer was effective in self-annihilation of APBs near the nucleation layer (Figure 7b). The GaAs crystal quality was also confirmed by photoluminescence (PL) emission intensity. As shown in Figure 7e, the PL intensity of InAs QD layer grown on GaAs/Si with Al 0.3 Ga 0.7 As nucleation layer was two times higher than that with a GaAs nucleation layer, and, as the Al content of Al x Ga 1−x As nucleation layer increases, the PL intensity tended to decrease. It was revealed that the APB-free GaAs layer could be obtained by employing the Al 0.3 Ga 0.7 As nucleation layer and the APB suppression mechanism was attributed to the self-annihilation of APBs rather than the formation of double-atomic step on Si surface. However, the detailed annihilation mechanism is not clearly understood, and the critical growth parameters remain uncertain. It was previously believed that the formation of double-atomic (D) steps on Si was the key step for APB or IB annihilation during the III-V growth on Si. In 2020, however, Li et al. [128] first proposed a new mechanism for APB annihilation and reported all MBE-grown APB-free GaAs monolithically grown on on-axis Si (001) using an annealed Si buffer layer. In this report, a 200 nm-thick Si buffer layer, comprised of 100 nm-thick Si layer and five sets of 20 nm-thick Si layers annealed at 900 °C and 1200 °C, respectively, was grown on the deoxidized on-axis (001) Si substrate. Subsequently, conventional GaAs buffer layer, defect filter layers (DFLs), and QD laser structures were grown. Both the use of AlGaAs seed layer [127,129] and heat treatment on the deoxidized Si (001) substrate up to 1200 °C [130], known to offer APB-free GaAs growth on Si, showed APBs on the GaAs surface in this experiment, whereas the sample with an annealed 200 nm-thick Si buffer layer exhibited APB-free GaAs surface. To examine the origin of the APB annihilation, AFM images of surface morphology of Si substrates without and with the annealed Si buffer layer were shown in Figure 8a,b, respectively. Contrary to the deoxidized Si surface showing a random atomic-step distribution (Figure 8a), ordered Si steps were observed in the annealed buffer Si surface, as shown in Figure 8b. The ordered Si steps consist of alternating straight and meandering Si monatomic steps (Figure 8c), each of which has the height of around 0.13 nm (Figure 8d). This indicates that the annealed Si buffer produces singleatomic (S) steps rather than the D steps. The inset of Figure 8c illustrates a schematic diagram of alternating straight and meandering single-atomic steps denoted by Sa and Sb, respectively. It was previously believed that the formation of double-atomic (D) steps on Si was the key step for APB or IB annihilation during the III-V growth on Si. In 2020, however, Li et al. [128] first proposed a new mechanism for APB annihilation and reported all MBE-grown APB-free GaAs monolithically grown on on-axis Si (001) using an annealed Si buffer layer. In this report, a 200 nm-thick Si buffer layer, comprised of 100 nm-thick Si layer and five sets of 20 nm-thick Si layers annealed at 900 • C and 1200 • C, respectively, was grown on the deoxidized on-axis (001) Si substrate. Subsequently, conventional GaAs buffer layer, defect filter layers (DFLs), and QD laser structures were grown. Both the use of AlGaAs seed layer [127,129] and heat treatment on the deoxidized Si (001) substrate up to 1200 • C [130], known to offer APB-free GaAs growth on Si, showed APBs on the GaAs surface in this experiment, whereas the sample with an annealed 200 nm-thick Si buffer layer exhibited APB-free GaAs surface. To examine the origin of the APB annihilation, AFM images of surface morphology of Si substrates without and with the annealed Si buffer layer were shown in Figure 8a  ss-sectional TEM measurements with two viewing directions of [110] (Figure 9a igure 9e,f) were conducted on the sample without and with the annealed Si buffer la ple without the annealed Si buffer, although the APBs nucleated at the GaAs/Si i te along higher index planes and hence annihilate with each other (Figure 9a), som re not self-annihilated penetrate the whole GaAs layer (Figure 9c). For the sample w Si buffer, on the other hand, periodic arrays of the self-annihilated APBs, where the d the periodic arrays corresponds to the half-width of each Si step terrace, were obse b. Moreover, most of the APBs initiated from Sa + Sb array were annihilated within 5 As layer, as shown in Figure 9d. A similar tendency was also confirmed from [11 0] d Figure 9e,f. Consequently, it was revealed for the first time that the Si surface with alte Sa and meandering Sb single-atomic steps, formed by the annealed Si buffer layer,  (Figure 9a), some APBs which are not self-annihilated penetrate the whole GaAs layer (Figure 9c). For the sample with the annealed Si buffer, on the other hand, periodic arrays of the self-annihilated APBs, where the distance between the periodic arrays corresponds to the half-width of each Si step terrace, were observed in Figure 9b. Moreover, most of the APBs initiated from S a + S b array were annihilated within 500 nm-thick GaAs layer, as shown in Figure 9d. A similar tendency was also confirmed from 110 direction view in Figure 9e,f. Consequently, it was revealed for the first time that the Si surface with alternating straight S a and meandering S b single-atomic steps, formed by the annealed Si buffer layer, enabled the periodic APBs to follow the shapes of S a + S b steps and annihilate within 500 nm-thick GaAs overlayer.

Reduction of the Dislocations
For high-quality III-V layer monolithically grown on Si, achieving a low density of TD is a key issue. In particular, the TDs penetrating an active region of optoelectronic devices significantly degrade their performance. For example, quantum-well (QW) lasers monolithically grown on Si substrates, in which the TDD is 5 × 10 7 cm −2 corresponding to common TDD of GaAs/Si, shows no lasing behavior [131]. Therefore, a great deal of effort has been made on the reduction of TDD since the 1980s, and now the TDD of about 10 6 cm −2 for GaAs-on-Si can be achieved [48,132]. This section introduces general approaches essential for reducing TDD in III-V/Si heteroepitaxy.

Reduction of the Dislocations
For high-quality III-V layer monolithically grown on Si, achieving a low density of TD is a key issue. In particular, the TDs penetrating an active region of optoelectronic devices significantly degrade their performance. For example, quantum-well (QW) lasers monolithically grown on Si substrates, in which the TDD is 5 × 10 7 cm −2 corresponding to common TDD of GaAs/Si, shows no lasing behavior [131]. Therefore, a great deal of effort has been made on the reduction of TDD since the 1980s, and now the TDD of about 10 6 cm −2 for GaAs-on-Si can be achieved [48,132]. This section introduces general approaches essential for reducing TDD in III-V/Si heteroepitaxy.

Nucleation and III-V Buffer Layer
Initial stage of III-V growth on Si plays an important role since the growth begins with the formation of the island on Si surface, which considerably affects the TDD of the following overlayer. Therefore, a wide variety of methods have been extensively studied, including Si buffer layer

Nucleation and III-V Buffer Layer
Initial stage of III-V growth on Si plays an important role since the growth begins with the formation of the island on Si surface, which considerably affects the TDD of the following overlayer. Therefore, a wide variety of methods have been extensively studied, including Si buffer layer [133,134], pre-layer formation [112,135,136], two-step growth [106,108], migration-enhanced epitaxy [137,138], and amorphous buffer layer [139,140]. Among these approaches, the so-called two-step growth has been most widely adopted in GaAs/Si. The two-step growth starts with low-temperature (LT) growth (400 • C) of GaAs in the initial stage, followed by annealing and growing the GaAs at typical growth temperature about 550 • C~600 • C. The reason for using this growth order is because at LT the GaAs becomes continuous before the defects are introduced. Figure 10 compares the ways how the GaAs islands coalesce into a continuous layer at high and low growth temperature [25]. At the typical growth temperature of GaAs (550 • C~600 • C), the GaAs islands have a lot of defects before coalesced. Once these islands coalesce, the defects, trapped inside the island, are extended in continuous layer. Then, the extended defects are difficult to be removed. In general, LT growth introduces a higher density of islands than that of high-temperature (HT) growth due to the reduced diffusive mobility of adatoms. For LT growth, therefore, many defects originating from the high density of islands are generated. Hence, two-step growth including LT growth is expected to produce high density of defects. However, the two-step growth generally exhibits much better structural properties than single-step growth. This can be explained by that the defects of which the form is less diverse and more mobile may annihilate during growth and coalescing. growth has been most widely adopted in GaAs/Si. The two-step growth starts with low-temperature (LT) growth (400 °C) of GaAs in the initial stage, followed by annealing and growing the GaAs at typical growth temperature about 550 °C~600 °C. The reason for using this growth order is because at LT the GaAs becomes continuous before the defects are introduced. Figure 10 compares the ways how the GaAs islands coalesce into a continuous layer at high and low growth temperature [25]. At the typical growth temperature of GaAs (550 °C~600 °C), the GaAs islands have a lot of defects before coalesced. Once these islands coalesce, the defects, trapped inside the island, are extended in continuous layer. Then, the extended defects are difficult to be removed. In general, LT growth introduces a higher density of islands than that of high-temperature (HT) growth due to the reduced diffusive mobility of adatoms. For LT growth, therefore, many defects originating from the high density of islands are generated. Hence, two-step growth including LT growth is expected to produce high density of defects. However, the two-step growth generally exhibits much better structural properties than single-step growth. This can be explained by that the defects of which the form is less diverse and more mobile may annihilate during growth and coalescing. In addition, a three-step growth, the modified two-step growth method in which an intermediate-temperature (IT) layer is added between LT and HT layer, was commonly employed in recent years [128,[141][142][143]. Nozaki et al. [144] proposed and reported that the three-step growth method in GaAs-on-Si improved the surface morphology, as well as crystallinity. The detailed mechanism of this improvement was not clearly understood, but it was ascribed to the GaAs top layer grown at HT without direct contact to the LT nucleation layer. In addition, Wang et al. [145] directly compared the effect of three-step growth on the quality of GaAs on Si with two-step growth. It was shown that the three-step growth with two thermal cycle annealing produced rms roughness of 1.8 nm and the TDD of 1.1 × 10 7 cm −2 (3 × 10 6 cm −2 ) calculated from XRD (EPD), all of which are improved compared with the conventional two-step process.
Similar to GaAs/Si, the InP-on-Si system also commonly employs the two-step growth [146][147][148]. However, direct growth of InP on Si produces much higher TDD than that of GaAs on Si due to larger lattice mismatch (~8%) [149]. For the InP-on-Si, accordingly, the insertion of the intermediate buffer layer between InP and Si is preferred. In addition, a three-step growth, the modified two-step growth method in which an intermediate-temperature (IT) layer is added between LT and HT layer, was commonly employed in recent years [128,[141][142][143]. Nozaki et al. [144] proposed and reported that the three-step growth method in GaAs-on-Si improved the surface morphology, as well as crystallinity. The detailed mechanism of this improvement was not clearly understood, but it was ascribed to the GaAs top layer grown at HT without direct contact to the LT nucleation layer. In addition, Wang et al. [145] directly compared the effect of three-step growth on the quality of GaAs on Si with two-step growth. It was shown that the three-step growth with two thermal cycle annealing produced rms roughness of 1.8 nm and the TDD of 1.1 × 10 7 cm −2 (3 × 10 6 cm −2 ) calculated from XRD (EPD), all of which are improved compared with the conventional two-step process.
Similar to GaAs/Si, the InP-on-Si system also commonly employs the two-step growth [146][147][148]. However, direct growth of InP on Si produces much higher TDD than that of GaAs on Si due to larger lattice mismatch (~8%) [149]. For the InP-on-Si, accordingly, the insertion of the intermediate buffer layer between InP and Si is preferred.

Intermediate Buffer Layer
To avoid the problem arising from material dissimilarity between Si and III-V, the basic solution to insert other materials of which the lattice constant and CTE are matched with Si has been developed. For GaAs/Si heteroepitaxy, a wide variety of methods using germanium (Ge) [150][151][152][153][154], GaAsP [155,156], and InGaP [157] were developed. Among these materials, Ge has been most widely used because of its complete miscibility with Si, well-developed Ge-on-Si growth technology, and nearly the same lattice constant and CTE matching between GaAs and Ge [158]. Moreover, the compositionally graded Ge/Ge x Si 1−x offers efficient strain relaxation in the buffer layer, and therefore a final Ge cap layer serves as a virtual substrate for GaAs growth. In 1991, Fitzgerald et al. [159] reported the primary study on the compositionally graded Ge x Si 1−x layers (x = 0.23, 0.32, and 0.5) on Si, producing the TDD on the order of low 10 6 cm −2 . After that, substantial efforts have been devoted to achieving an artificial Ge/Ge x Si 1−x /Si substrates [113,[160][161][162][163][164]. For instance, Groenert et al. [158] demonstrated RT continuous-wave (cw) GaAs/Al x Ga 1−x As QW lasers monolithically grown on the graded Ge/Ge x Si 1−x /Si virtual substrates. As shown in Figure 11, most of dislocations are effectively confined within graded Ge x Si 1−x buffer layer, which offers strain relaxed pure Ge top layer and GaAs layer. The TDD on the Ge cap layer was measured to be 1.2 × 10 6 cm −2 .

Intermediate Buffer Layer
To avoid the problem arising from material dissimilarity between Si and III-V, the basic solution to insert other materials of which the lattice constant and CTE are matched with Si has been developed. For GaAs/Si heteroepitaxy, a wide variety of methods using germanium (Ge) [150][151][152][153][154], GaAsP [155,156], and InGaP [157] were developed. Among these materials, Ge has been most widely used because of its complete miscibility with Si, well-developed Ge-on-Si growth technology, and nearly the same lattice constant and CTE matching between GaAs and Ge [158]. Moreover, the compositionally graded Ge/GexSi1−x offers efficient strain relaxation in the buffer layer, and therefore a final Ge cap layer serves as a virtual substrate for GaAs growth. In 1991, Fitzgerald et al. [159] reported the primary study on the compositionally graded GexSi1−x layers (x = 0.23, 0.32, and 0.5) on Si, producing the TDD on the order of low 10 6 cm −2 . After that, substantial efforts have been devoted to achieving an artificial Ge/GexSi1−x/Si substrates [113,[160][161][162][163][164]. For instance, Groenert et al. [158] demonstrated RT continuous-wave (cw) GaAs/AlxGa1−xAs QW lasers monolithically grown on the graded Ge/GexSi1−x/Si virtual substrates. As shown in Figure 11, most of dislocations are effectively confined within graded GexSi1−x buffer layer, which offers strain relaxed pure Ge top layer and GaAs layer. The TDD on the Ge cap layer was measured to be 1.2 × 10 6 cm −2 . Today, for GaAs/Si system, direct growth of GaAs buffer layers using multi-step growth method is more preferred to the intermediate buffer layer, such as Ge or graded GeSi layers. This is because the use of Ge/GeSi buffer generally requires much thicker layers than that of common GaAs buffer layers despite similar TDD on the order of low 10 6 cm −2 . For the monolithic integration on Si platform, in general, a thin buffer layer is favorable in terms of thermal cracks [98] and co-integration with other components [12]. Although using thin Ge/GeSi buffer layers has been also demonstrated [165], the order of TDD (~10 8 cm −2 ) is much higher than that of thick Ge/GeSi or GaAs buffer layer (~10 6 cm −2 ). In addition, the chemical-mechanical polishing (CMP) process [164] used to obtain smooth surface in rough Ge/GeSi buffers can increase the fabrication cost and complexity.
Unlike the GaAs/Si, the InP/Si heteroepitaxy normally adopts the intermediate (graded) buffer layers because of the large lattice mismatch between InP and Si (~8%). The prevailing material Today, for GaAs/Si system, direct growth of GaAs buffer layers using multi-step growth method is more preferred to the intermediate buffer layer, such as Ge or graded GeSi layers. This is because the use of Ge/GeSi buffer generally requires much thicker layers than that of common GaAs buffer layers despite similar TDD on the order of low 10 6 cm −2 . For the monolithic integration on Si platform, in general, a thin buffer layer is favorable in terms of thermal cracks [98] and co-integration with other components [12]. Although using thin Ge/GeSi buffer layers has been also demonstrated [165], the order of TDD (~10 8 cm −2 ) is much higher than that of thick Ge/GeSi or GaAs buffer layer (~10 6 cm −2 ). In addition, the chemical-mechanical polishing (CMP) process [164] used to obtain smooth surface in rough Ge/GeSi buffers can increase the fabrication cost and complexity.
Unlike the GaAs/Si, the InP/Si heteroepitaxy normally adopts the intermediate (graded) buffer layers because of the large lattice mismatch between InP and Si (~8%). The prevailing material commonly used for the intermediate buffer is GaAs [166][167][168][169]. The most typical approach for growing InP on Si is employing the mature multi-step growth of GaAs on Si with strained-layer superlattices filtering the TDs [149,170,171]. Even though the GaP buffer layer has also been utilized, it was known to be less effective in terms of TDD, residual stress, and quality of InP, compared with the GaAs buffer layer [172][173][174]. Besides, the employment of compositionally graded buffer layer, including InGaAs, InGaP, InAlAs, and InGaAlAs alloys, has shown successful reduction of the TDD in InP/GaAs [175][176][177][178]. For example, Quitoriano et al. [175], who studied graded buffers grown on GaAs substrates to obtain high-quality InP without phase separation, demonstrated low TDD of 1.2 × 10 6 cm -2 through the hybrid InGaAs and InGaP graded buffer layer. In a similar way, to further decrease the TDD of InP/GaAs/Si epitaxy, growing the graded buffer layers on the GaAs/Si substrates has also been explored. For instance, Shi et al. [149] have shown a low TDD of 5 × 10 6 cm −2 by using 1.8 µm-thick graded In 0.4 Ga 0.6 As buffers on 2 µm-thick GoVS template.

Epitaxial Lateral Overgrowth
Epitaxial lateral overgrowth (ELO) is also an important technique to inhibit the propagation of TDs in epitaxial layer. Like ART process reviewed in Section 3.1.2, ELO is also based on SAG method. In the ELO process, a III-V buffer layer is first grown on Si substrate, and subsequently a dielectric mask, such as SiO 2 , is deposited on the III-V buffer layer. Then, the dielectric mask is selectively etched to expose the III-V buffer layer for regrowth. Then, the III-V epitaxial layer is vertically regrown through the opened region of the mask and thereafter can be laterally grown over the mask. The most of TDs in the buffer layer are blocked by the bottom of the mask, but a small number of TDs around the opened region will propagate upwards, as shown in Figure 12a. Therefore, the laterally grown epitaxial layer above the dielectric mask exhibits a high crystalline quality.  [166][167][168][169]. The most typical approach for growing InP on Si is employing the mature multi-step growth of GaAs on Si with strained-layer superlattices filtering the TDs [149,170,171]. Even though the GaP buffer layer has also been utilized, it was known to be less effective in terms of TDD, residual stress, and quality of InP, compared with the GaAs buffer layer [172][173][174]. Besides, the employment of compositionally graded buffer layer, including InGaAs, InGaP, InAlAs, and InGaAlAs alloys, has shown successful reduction of the TDD in InP/GaAs [175][176][177][178]. For example, Quitoriano et al. [175], who studied graded buffers grown on GaAs substrates to obtain high-quality InP without phase separation, demonstrated low TDD of 1.2 × 10 6 cm -2 through the hybrid InGaAs and InGaP graded buffer layer. In a similar way, to further decrease the TDD of InP/GaAs/Si epitaxy, growing the graded buffer layers on the GaAs/Si substrates has also been explored. For instance, Shi et al. [149] have shown a low TDD of 5 × 10 6 cm −2 by using 1.8 μmthick graded In0.4Ga0.6As buffers on 2 μm-thick GoVS template.

Epitaxial Lateral Overgrowth
Epitaxial lateral overgrowth (ELO) is also an important technique to inhibit the propagation of TDs in epitaxial layer. Like ART process reviewed in Section 3.1.2, ELO is also based on SAG method. In the ELO process, a III-V buffer layer is first grown on Si substrate, and subsequently a dielectric mask, such as SiO2, is deposited on the III-V buffer layer. Then, the dielectric mask is selectively etched to expose the III-V buffer layer for regrowth. Then, the III-V epitaxial layer is vertically regrown through the opened region of the mask and thereafter can be laterally grown over the mask. The most of TDs in the buffer layer are blocked by the bottom of the mask, but a small number of TDs around the opened region will propagate upwards, as shown in Figure 12a. Therefore, the laterally grown epitaxial layer above the dielectric mask exhibits a high crystalline quality.  For the GaAs on Si, pioneering works on ELO have been reported since 1980s [180][181][182]. However, the early reports on ELO for GaAs-on-Si suffered from the limited defect-free region and the mechanical weakness of the laterally grown parts, both of which became severe as the ELO layer was further grown. In order to resolve these limitations of ELO technique, a great deal of effort has been dedicated to optimizing growth conditions [118,179,[183][184][185][186][187][188][189]. For example, Chang et al. [179], investigating the dependence of the ratio of the ELO layer width to the thickness (W/T ratio) on the growth temperature and the seed line separation, showed that the width of dislocation-free GaAs region achieved about 43 µm. In this work, misoriented (100) Si substrates, on which a GaAs buffer layer was grown by MBE, were used for ELO of GaAs by liquid phase epitaxy (LPE). For comparison, the width of the line seed (opened region for regrowth) was fixed as 5 µm, but the line seed separation was varied as 200, 500, and 1000 µm. In addition, growth temperature of GaAs was chosen as 500, 530, and 560 • C. As shown in Figure 12b, a maximum W/T ratio of 17.5 was achieved by the line seed separation of 500 µm and the growth temperature of 530 • C. Figure 12c shows a wide ELO layers of 195 µm-width after the growth time of 7 hours. To identify dislocation-free region, etch-pit density (EPD) was measured by KOH etching. As shown in Figure 12d, a high density of TDs which propagated from the GaAs buffer layer through the narrow line seed region can be clearly seen. However, no etch pits were found in the laterally overgrown GaAs. In addition, He et al. [188] proposed a three-stage ELO to obtain uniform and flat coalescence of selectively grown GaAs. In this report, 1.8 µm GaAs buffer was first grown on 4 • offcut (001) Si substrate toward the <011> direction. Then, 80 nm-thick SiO 2 mask was deposited on buffer layer, and nano-trench of 120 nm-width and 100 nm-separation was patterned on the mask. Last, the three-stage of ELO growth, comprised of the selective growth, coalescence, and planar growth stage, were carried out by MOCVD. It was shown that the nano-trench and three-step growth resulted in a mirror-smooth coalesced 410 nm-thick GaAs film.
In case of InP-on-Si, ELO techniques have been more widely employed [190][191][192][193][194][195][196], compared with GaAs-on-Si in which direct growth of GaAs on Si is preferred. Because it is very difficult to obtain low density of TDs through the direct growth of InP on Si, the use of ELO method is beneficial for achieving high-quality InP layer on Si. For the optimization of parameters of InP ELO on (001) InP substrate, Sun et al. [197] investigated the dependence of lateral overgrowth and vertical growth rate of InP on the mask stripe orientation. It was revealed that while the vertical growth rate was relatively independent of the opened stripe orientation, the maximum lateral overgrowth rate was achieved when the opened stripe oriented at 30 • and 60 • off [110] direction, as shown in Figure 13a. Following this result, Sun et al. [198] achieved a broad lateral overgrowth of InP on (001) Si substrate. In addition, Metaferia et al. [199] studied the morphological evolution during ELO of InP on Si with mesh opening, and showed that the coalesced region produced the TDD in a range from 6 × 10 6 cm −2 to 4 × 10 7 cm −2 depending on the thickness of ELO layer. In this work, 1.5 µm-thick InP/Si and 40 nm-thick SiO 2 mask were used to overgrow InP. The mesh and line masks (opening and masking width of 200 nm and 3 µm, respectively), tilted 15 • and 30 • off the [110] direction, are compared. The angle between the opening line in mask and [110] direction was chosen from previous result by Sun et al. [197]. As shown in Figure 13b,c, the coalescence of the InP layer occurs predominantly at the corners of the mask. Such a coalescence mechanism in mesh mask resulted in higher growth rate than that in line mask, attributed to the less probability of the boundary plane formation. The quicker coalescence in the mesh opening resulted in better surface roughness at the early growth stage (~10 µm-thick InP layer), but, after an extended growth (~100 µm-thick InP layer), both mesh and line opening cases exhibited a similar surface roughness (rms roughness of 16 nm~25 nm). It was shown that regardless of both angles (15 • and 30 • ) and masks (mesh and line opening) the TDDs were measured to be similar value. The TDD of about 10 µm-thick and 100 µm-thick InP layer was measured to be 2~4 × 10 7 cm −2 and 6~7 × 10 6 cm −2 , respectively.

Thermal Annealing
The traditional way to reduce defect density is thermal cycle annealing (TCA) during growth, enabling thermally-activated dislocation migration and thus the annihilation of dislocations. Indeed, the TCA-induced reduction of TDD in GaAs/Si has been substantially investigated [200][201][202][203][204][205]. For instance, Yamaguchi et al. [201], investigating the TCA effects on the defect reduction in GaAs/Si, reported that the dislocation density was considerably reduced as the annealing temperature and cycling number increased. The etch pit density (EPD) was reduced from 10 8 cm −2 to 2 × 10 6 cm −2 after TCA. It was revealed that the thermally-induced stress as a driving force of dislocation motion contributed to the dislocation annihilation, such as coalescence. The numerical analysis also showed that the large number of TCA and/or annealing temperatures of more than 700 °C were effective in the reduction of TDD. However, in the case that the grown films initially have low density of dislocation which can move and coalesce, the attainable reduction of TDD is limited. In addition, Jung et al. [203] demonstrated that the in-situ TCA effectively reduced the TDD of GaAs grown on on-axis GaP/Si (001). To investigate the effect of in-situ TCA, a 1.5 μm-thick GaAs layer was first grown on GaP/Si, followed by four cycles of annealing. Then, another 1.5 μm-thick GaAs layer was regrown. For comparison, 3 μm-thick GaAs layer was also grown on GaP/Si without TCA. During in-situ TCA, the wafer was heated up to 700 °C and held for 5 min. Then, the temperature cooled down to 320 °C. The electron channeling contrast imaging (ECCI) revealed that the TDD of the TCAtreated sample (5.5 × 10 7 cm −2 ) was much lower than that of untreated sample (2.8 × 10 8 cm −2 ). It was also found that the TCA process improved the surface roughness from 7.8 nm to 4.8 nm (rms). Recently, Shang et al. [206] investigated the effect of TCA on the reduction in TDD of GaAs-on-Si template. As shown in Figure 14A, a minimum TDD of 3 × 10 7 cm −2 was obtained after 12 cycles of TCA. A noticeable reduction in TDD was achieved at 4 (8) cycles of annealing at 735 °C (700 °C). The maximum annealing temperature was set to below 745 °C because annealing at above 745 ˚C causes remarkable degradation of the GaAs surface, such as the formation of Ga droplet, as shown in Figure   Figure 13.

Thermal Annealing
The traditional way to reduce defect density is thermal cycle annealing (TCA) during growth, enabling thermally-activated dislocation migration and thus the annihilation of dislocations. Indeed, the TCA-induced reduction of TDD in GaAs/Si has been substantially investigated [200][201][202][203][204][205]. For instance, Yamaguchi et al. [201], investigating the TCA effects on the defect reduction in GaAs/Si, reported that the dislocation density was considerably reduced as the annealing temperature and cycling number increased. The etch pit density (EPD) was reduced from 10 8 cm −2 to 2 × 10 6 cm −2 after TCA. It was revealed that the thermally-induced stress as a driving force of dislocation motion contributed to the dislocation annihilation, such as coalescence. The numerical analysis also showed that the large number of TCA and/or annealing temperatures of more than 700 • C were effective in the reduction of TDD. However, in the case that the grown films initially have low density of dislocation which can move and coalesce, the attainable reduction of TDD is limited. In addition, Jung et al. [203] demonstrated that the in-situ TCA effectively reduced the TDD of GaAs grown on on-axis GaP/Si (001).
To investigate the effect of in-situ TCA, a 1.5 µm-thick GaAs layer was first grown on GaP/Si, followed by four cycles of annealing. Then, another 1.5 µm-thick GaAs layer was regrown. For comparison, 3 µm-thick GaAs layer was also grown on GaP/Si without TCA. During in-situ TCA, the wafer was heated up to 700 • C and held for 5 min. Then, the temperature cooled down to 320 • C. The electron channeling contrast imaging (ECCI) revealed that the TDD of the TCA-treated sample (5.5 × 10 7 cm −2 ) was much lower than that of untreated sample (2.8 × 10 8 cm −2 ). It was also found that the TCA process improved the surface roughness from 7.8 nm to 4.8 nm (rms). Recently, Shang et al. [206] investigated the effect of TCA on the reduction in TDD of GaAs-on-Si template. As shown in Figure 14A, a minimum TDD of 3 × 10 7 cm −2 was obtained after 12 cycles of TCA. A noticeable reduction in TDD was achieved at 4 (8) cycles of annealing at 735 • C (700 • C). The maximum annealing temperature was set to below 745 • C because annealing at above 745 • C causes remarkable degradation of the GaAs surface, such as the formation of Ga droplet, as shown in Figure 14B. In Figure 14C, ECCI images showed that the TDD was reduced from 4.18 × 10 8 cm −2 to 3 × 10 7 cm −2 after 16 cycles of TCA. It should be noted that a surface TDD lower than 2 × 10 6 cm -2 was obtained after a step-graded filter layer was grown on the post-TCA GaAs-on-Si. In a similar mechanism of TCA, post-growth annealing (PGA), carried out after completing the growth, has also been widely employed to reduce the TDD of GaAs [207][208][209].
Crystals 2020, 10, x FOR PEER REVIEW  19 of 40 14B. In Figure 14C, ECCI images showed that the TDD was reduced from 4.18 × 10 8 cm −2 to 3 × 10 7 cm −2 after 16 cycles of TCA. It should be noted that a surface TDD lower than 2 × 10 6 cm -2 was obtained after a step-graded filter layer was grown on the post-TCA GaAs-on-Si. In a similar mechanism of TCA, post-growth annealing (PGA), carried out after completing the growth, has also been widely employed to reduce the TDD of GaAs [207][208][209]. For the InP/Si, TCA or PGA has also been applied to improve the crystal quality [168,169,210,211]. However, the effect of thermal annealing on the defect reduction is not as dramatic as in GaAs/Si because the difference of CTE between InP and Si is relatively small; thus, the dislocation motion by thermally-driven stress is limited.

Strained-Layer Superlattices Defect Filter Layer
Strained-layer superlattices (SLSs) have long been extensively investigated in order to reduce the dislocation density since the 1980s [212][213][214][215]. Matthews et al. [212], who proposed the use of an SLS to reduce the TDD, demonstrated that the strain field in GaAsP-GaAs superlattice turned aside the TD propagating upward. The SLSs commonly consist of multiple pairs of two lattice-mismatched layers alternately under compression and tension. If the thickness of each SLS layer is less than a certain critical thickness, which otherwise creates misfit dislocations, each SLS layer accommodates elastic strains caused by lattice mismatch. The strain field of SLSs can bend over and force the dislocations propagating upward to move laterally toward the edge of the sample, leading to the dislocation coalescence and annihilation. Noted that the SLSs should have enough lattice mismatch and thickness to generate strain required for bending dislocations.
Ternary-binary SLSs DFLs have been widely used in GaAs/Si heteroepitaxy, including InGaAs/GaAs, InAlAs/GaAs, GaAsP/GaAs, and so on [216][217][218][219][220][221][222][223][224]. For example, Mingchu et al. [224] optimized InGaAs/GaAs DFLs for 1.3-μm QD lasers on Si. In this work, the indium composition and thickness in InxGa1−xAs/GaAs SLSs, as well as the growth condition of GaAs spacer layer, were investigated. In the growth method I (Figure 15a), the GaAs spacer layer was grown while the temperature in chamber was ramping up from 420 °C to 610 °C after the SLS growth at 420 °C. In contrast, in the growth method II (Figure 15b), the GaAs spacer layer was grown at 610 °C after finishing the ramp-up of temperature and in-situ annealing of the SLSs. In Figure 15c, the PL peak intensity of QD laser structure with growth method II was at least three times higher than that with growth method I. This improvement can be attributed to the high-temperature growth of GaAs spacer layer and in-situ annealing of SLSs. The high-temperature growth and annealing promoted the dislocation motion and resultant annihilation. It is also revealed that the optimized indium composition and GaAs thickness in SLSs were 0.18 and 10 nm, respectively. In Figure 15d, it was For the InP/Si, TCA or PGA has also been applied to improve the crystal quality [168,169,210,211]. However, the effect of thermal annealing on the defect reduction is not as dramatic as in GaAs/Si because the difference of CTE between InP and Si is relatively small; thus, the dislocation motion by thermally-driven stress is limited.

Strained-Layer Superlattices Defect Filter Layer
Strained-layer superlattices (SLSs) have long been extensively investigated in order to reduce the dislocation density since the 1980s [212][213][214][215]. Matthews et al. [212], who proposed the use of an SLS to reduce the TDD, demonstrated that the strain field in GaAsP-GaAs superlattice turned aside the TD propagating upward. The SLSs commonly consist of multiple pairs of two lattice-mismatched layers alternately under compression and tension. If the thickness of each SLS layer is less than a certain critical thickness, which otherwise creates misfit dislocations, each SLS layer accommodates elastic strains caused by lattice mismatch. The strain field of SLSs can bend over and force the dislocations propagating upward to move laterally toward the edge of the sample, leading to the dislocation coalescence and annihilation. Noted that the SLSs should have enough lattice mismatch and thickness to generate strain required for bending dislocations.
Ternary-binary SLSs DFLs have been widely used in GaAs/Si heteroepitaxy, including InGaAs/GaAs, InAlAs/GaAs, GaAsP/GaAs, and so on [216][217][218][219][220][221][222][223][224]. For example, Mingchu et al. [224] optimized InGaAs/GaAs DFLs for 1.3-µm QD lasers on Si. In this work, the indium composition and thickness in In x Ga 1−x As/GaAs SLSs, as well as the growth condition of GaAs spacer layer, were investigated. In the growth method I (Figure 15a), the GaAs spacer layer was grown while the temperature in chamber was ramping up from 420 • C to 610 • C after the SLS growth at 420 • C. In contrast, in the growth method II (Figure 15b), the GaAs spacer layer was grown at 610 • C after finishing the ramp-up of temperature and in-situ annealing of the SLSs. In Figure 15c, the PL peak intensity of QD laser structure with growth method II was at least three times higher than that with growth method I. This improvement can be attributed to the high-temperature growth of GaAs spacer layer and in-situ annealing of SLSs. The high-temperature growth and annealing promoted the dislocation motion and resultant annihilation. It is also revealed that the optimized indium composition and GaAs thickness in SLSs were 0.18 and 10 nm, respectively. In Figure 15d, it was shown that the employment of three sets of In 0.18 Ga 0.82 As/GaAs SLSs DFLs effectively blocked and annihilated the TDs.
Crystals 2020, 10, x FOR PEER REVIEW 20 of 40 shown that the employment of three sets of In0.18Ga0.82As/GaAs SLSs DFLs effectively blocked and annihilated the TDs. In the InP/Si platform, the DFLs based on InGaAs/InP, In(Ga)AsP/InP, (In)GaP/InP, and so on [149,170,[225][226][227][228][229][230] have been also commonly adopted. For instance, Shi et al. [149] reported the effect of In0.73Ga0.27As/InP SLSs DFLs on the reduction of TDD in InP grown on on-axis (001) Si. In this report, InP buffer layers were first grown on GoVS template using multi-step growth, followed by four sets of InGaAs (13 nm)/InP (19 nm) 10-pair SLSs with 300 nm-thick InP spacer layers. In Figure  16a, bright-field scanning transmission electron microscopy (STEM) image of InP-on-Si structure exhibits the generation and propagation of TDs. A high density of TDs on the order of 10 10 cm −2 generated from the InP/GaAs interface (line 1) was reduced to the TDD of 1.5 × 10 9 cm −2 through multi-step grown InP buffer layer (line 2). The final InP surface defect density was measured to be 1.17 × 10 8 cm −2 after four sets of InGaAs/InP DFLs (line 6). In Figure 16b, a zoomed-in STEM image of SLSs DFLs clearly shows that most of the dislocations are bent along the bottom or top interfaces of each SLS layer, resulting in the mutual annihilation of TDs. It was also revealed that SLSs with high indium composition (In0.82Ga0.18As) achieved low TDD of 7.9 × 10 7 cm −2 but formed rough surface with many hillocks. By considering surface morphology, as well as defect filtering efficiency, therefore, the optimized indium composition was about 71%. However, in general, using SLSs DFLs in InP-on-Si is not as effective as in GaAs-on-Si. For example, the TDD of InP-based materials remains on the order of 10 8 cm −2 , while, in GaAs-based materials, the order of 10 6 cm −2 can be achieved. The reason for the discrepancy is not clearly understood, but it is believed to be due to the phase separation in the SLSs and/or the high density of dislocations arising from larger lattice mismatch in InP/Si than In the InP/Si platform, the DFLs based on InGaAs/InP, In(Ga)AsP/InP, (In)GaP/InP, and so on [149,170,[225][226][227][228][229][230] have been also commonly adopted. For instance, Shi et al. [149] reported the effect of In 0.73 Ga 0.27 As/InP SLSs DFLs on the reduction of TDD in InP grown on on-axis (001) Si. In this report, InP buffer layers were first grown on GoVS template using multi-step growth, followed by four sets of InGaAs (13 nm)/InP (19 nm) 10-pair SLSs with 300 nm-thick InP spacer layers. In Figure 16a, bright-field scanning transmission electron microscopy (STEM) image of InP-on-Si structure exhibits the generation and propagation of TDs. A high density of TDs on the order of 10 10 cm −2 generated from the InP/GaAs interface (line 1) was reduced to the TDD of 1.5 × 10 9 cm −2 through multi-step grown InP buffer layer (line 2). The final InP surface defect density was measured to be 1.17 × 10 8 cm −2 after four sets of InGaAs/InP DFLs (line 6). In Figure 16b, a zoomed-in STEM image of SLSs DFLs clearly shows that most of the dislocations are bent along the bottom or top interfaces of each SLS layer, resulting in the mutual annihilation of TDs. It was also revealed that SLSs with high indium composition (In 0.82 Ga 0.18 As) achieved low TDD of 7.9 × 10 7 cm −2 but formed rough surface with many hillocks. By considering surface morphology, as well as defect filtering efficiency, therefore, the optimized indium composition was about 71%. However, in general, using SLSs DFLs in InP-on-Si is not as effective as in GaAs-on-Si. For example, the TDD of InP-based materials remains on the order of 10 8 cm −2 , while, in GaAs-based materials, the order of 10 6 cm −2 can be achieved. The reason for the discrepancy is not clearly understood, but it is believed to be due to the phase separation in the SLSs and/or the high density of dislocations arising from larger lattice mismatch in InP/Si than that in GaAs/Si [175]. It is also reported that, if the TDD is on the order of 10 8 cm −2 or greater, the SLSs is not very effective in dislocation filtering [216].
Crystals 2020, 10, x FOR PEER REVIEW 21 of 40 that in GaAs/Si [175]. It is also reported that, if the TDD is on the order of 10 8 cm −2 or greater, the SLSs is not very effective in dislocation filtering [216]. In addition, instead of SLSs, the self-assembled QDs can be used as DFLs [231][232][233]. The employment of InAs QDs as DFLs in GaAs-based material was first proposed and demonstrated by Yang et al. [231]. Because the strain-driven self-organized QDs produce large three-dimensional strain field around themselves, dislocations around QDs can be bent over and annihilated in a similar way to SLSs DFLs. For instance, Shi et al. [232] reported a four-fold reduction in density of TDs in InP/Si system by using self-organized InAs/InAlGaAs QDs as DFLs. In Figure 17a, a number of TDs, generated from InP/GaAs and GaAs/Si interfaces, propagate toward the top surface, leading to the TDD of 1.3 × 10 9 cm −2 . In contrast, adopting the seven-layer of InAs/InAlGaAs QDs DFLs in InP/Si clearly shows dislocation bending and filtering effects, offering a four-fold reduction in TDD (3.2 × 10 8 cm −2 ), as shown in Figure 17b. In addition, instead of SLSs, the self-assembled QDs can be used as DFLs [231][232][233]. The employment of InAs QDs as DFLs in GaAs-based material was first proposed and demonstrated by Yang et al. [231]. Because the strain-driven self-organized QDs produce large three-dimensional strain field around themselves, dislocations around QDs can be bent over and annihilated in a similar way to SLSs DFLs. For instance, Shi et al. [232] reported a four-fold reduction in density of TDs in InP/Si system by using self-organized InAs/InAlGaAs QDs as DFLs. In Figure 17a, a number of TDs, generated from InP/GaAs and GaAs/Si interfaces, propagate toward the top surface, leading to the TDD of 1.3 × 10 9 cm −2 . In contrast, adopting the seven-layer of InAs/InAlGaAs QDs DFLs in InP/Si clearly shows dislocation bending and filtering effects, offering a four-fold reduction in TDD (3.2 × 10 8 cm −2 ), as shown in Figure 17b.

Minimizing Thermal Cracks
Controlling thermally-induced strain during the growth is very important because the residual strain by a large difference of CTE leads to thermal cracks or delamination, which are unacceptable for the device fabrication. In order to prevent the crack formation, basically, the thickness of epitaxial layer should be less than the critical thickness of crack formation. In addition, any imperfections, such as surface contaminants and defects, should be minimized because the formation of thermal crack is heterogeneous nucleation [98]. For III-V-on-Si heteroepitaxy, however, both thick buffer layers and crystal imperfections are inevitable. Therefore, various strategies for minimizing thermal cracks, including porous Si layer [234], strain compensated layer [235,236], use of indium dopant [237], and patterned substrate [83,92,238,239], have been proposed. Among these techniques, the use of patterning has been widely developed. For example, Huang et al. [239] reported crack-free GaAs layer on Si with an area of 800 × 700 μm 2 by employing mid-patterned growth. In this work, to obtain crack-free GaAs/Si template, three steps were carried out: (1) a 2.3 μm-thick GaAs layer with AlAs/AlGaAs nucleation layer was first grown on (100) Si substrate with 3˚ off toward [011], and the in-situ TCA was applied; (2) rectangular mesa structures (800 × 700 μm 2 ) were achieved by chemical etching with H2SO4/H2O2/H2O (1:1:2) and KOH (40 wt. %) solutions in sequence; (3) a 1.7 μm-thick GaAs buffer layer was regrown, and the second in-situ TCA was performed. Then, GaAs-based Fabry-Perot filtering cavity with an InP-based p-i-n absorption structure was finally grown on the mid-patterned GaAs/Si platform. As shown in Figure 18a, no crack line is observed in the wet-etched epilayers grown on mid-patterned GaAs/Si. In contrast, for the sample without patterning, a high density of crack lines (~112 cm −1 ) parallel to the [011] or [01 1] direction was confirmed in Figure  18b. The crack-free and high-quality GaAs layer was attributed to the mid-patterned growth that enables the thermal stress to be consumed for reducing dislocation. In other words, the thermal energy was used to form the parallel dislocations, which alleviates the thermal stress.

Minimizing Thermal Cracks
Controlling thermally-induced strain during the growth is very important because the residual strain by a large difference of CTE leads to thermal cracks or delamination, which are unacceptable for the device fabrication. In order to prevent the crack formation, basically, the thickness of epitaxial layer should be less than the critical thickness of crack formation. In addition, any imperfections, such as surface contaminants and defects, should be minimized because the formation of thermal crack is heterogeneous nucleation [98]. For III-V-on-Si heteroepitaxy, however, both thick buffer layers and crystal imperfections are inevitable. Therefore, various strategies for minimizing thermal cracks, including porous Si layer [234], strain compensated layer [235,236], use of indium dopant [237], and patterned substrate [83,92,238,239], have been proposed. Among these techniques, the use of patterning has been widely developed. For example, Huang et al. [239] reported crack-free GaAs layer on Si with an area of 800 × 700 µm 2 by employing mid-patterned growth. In this work, to obtain crack-free GaAs/Si template, three steps were carried out: (1) a 2.3 µm-thick GaAs layer with AlAs/AlGaAs nucleation layer was first grown on (100) Si substrate with 3 • off toward [011], and the in-situ TCA was applied; (2) rectangular mesa structures (800 × 700 µm 2 ) were achieved by chemical etching with H 2 SO 4 /H 2 O 2 /H 2 O (1:1:2) and KOH (40 wt. %) solutions in sequence; (3) a 1.7 µm-thick GaAs buffer layer was regrown, and the second in-situ TCA was performed. Then, GaAs-based Fabry-Perot filtering cavity with an InP-based p-i-n absorption structure was finally grown on the mid-patterned GaAs/Si platform. As shown in Figure 18a, no crack line is observed in the wet-etched epilayers grown on mid-patterned GaAs/Si. In contrast, for the sample without patterning, a high density of crack lines (~112 cm −1 ) parallel to the [011] or 011 direction was confirmed in Figure 18b. The crack-free and high-quality GaAs layer was attributed to the mid-patterned growth that enables the thermal stress to be consumed for reducing dislocation. In other words, the thermal energy was used to form the parallel dislocations, which alleviates the thermal stress. Recently, approaches using the Ge on the micropillar patterned Si(001) substrates were proposed [240][241][242][243][244][245]. For instance, Falub et al. [244] reported that the closely spaced Ge and GeSi crystals with arbitrary height were grown on the deeply etched micropillar patterned Si(001) substrates. In this work, the self-limiting lateral growth of Ge crystals on micropillar patterns (height, width, and spacing are 1.7~8 μm, 0.75~15 μm, and 0.2~50 μm, respectively) enables very thick Ge towers (up to, but not limited to, 50 μm) without cracking. The crack propagation was impeded by preventing a continuous growth of Ge, and the TDs are trapped at the sidewall of Ge crystals with ART process. In a similar way, Zhang et al. [243], who employed {113}-faceted Ge/Si (001) hollow substrate, showed a crack-free GaAs film up to 7 μm. To fabricate the template illustrated in Figure 19a, the U-shape grating pattern (period, ridge width, and depth were 360, 140, and 500 nm, respectively) was defined on an on-axis Si (001) substrate by using deep ultraviolet lithography and reactive ion etching. After the deposition of 60 nm Si buffer on the patterned substrate, a 600 nm Ge layer was grown to achieve the {113}-faceted Ge hollow structures, as shown in Figure 19b. Then, the typical two-step GaAs and InAs/GaAs dot-in-a-well structure were grown on the template for the characterization of epitaxial layer. To characterize the thermal strain issue, a high-resolution XRD reciprocal space mapping was performed around (004) and (2(-)2(-)4) reflections. From peak positions in Figure 19c,d, the in-plane and out-of-plane lattice constants for GaAs (Ge) were measured to be 5.660 Å (5.659 Å) and 5.648 Å (5.654 Å), respectively. The in-plane strain ∥ of GaAs (Ge) was calculated to be 1.13 × 10 −3 (1.68 × 10 −4 ) by comparing the measured lattice constants with the lattice constant of bulk GaAs (5.653 Å) and Ge (5.658 Å). It was revealed that the residual thermal strain of Ge layer on the hollow Si substrate (1.68 × 10 −4 ) was 89.8% lower than that of a Ge layer on normal Si substrates (1.65 × 10 −3 ) [241]. The residual thermal strain of GaAs layer in this work (1.13 × 10 −3 ) was 29.4% lower than that of GaAs layer on the conventional Ge/Si substrates (1.6 × 10 −3 ) [246]. The reduction of thermal strain was ascribed to the presence of extra free surface. As a result, the 7 μm-thick GaAs layer, which is far beyond the typical value of the cracking thickness, can be grown on {113}-faceted Ge/Si hollow substrate. Recently, approaches using the Ge on the micropillar patterned Si(001) substrates were proposed [240][241][242][243][244][245]. For instance, Falub et al. [244] reported that the closely spaced Ge and GeSi crystals with arbitrary height were grown on the deeply etched micropillar patterned Si(001) substrates. In this work, the self-limiting lateral growth of Ge crystals on micropillar patterns (height, width, and spacing are 1.7~8 µm, 0.75~15 µm, and 0.2~50 µm, respectively) enables very thick Ge towers (up to, but not limited to, 50 µm) without cracking. The crack propagation was impeded by preventing a continuous growth of Ge, and the TDs are trapped at the sidewall of Ge crystals with ART process. In a similar way, Zhang et al. [243], who employed {113}-faceted Ge/Si (001) hollow substrate, showed a crack-free GaAs film up to 7 µm. To fabricate the template illustrated in Figure 19a, the U-shape grating pattern (period, ridge width, and depth were 360, 140, and 500 nm, respectively) was defined on an on-axis Si (001) substrate by using deep ultraviolet lithography and reactive ion etching. After the deposition of 60 nm Si buffer on the patterned substrate, a 600 nm Ge layer was grown to achieve the {113}-faceted Ge hollow structures, as shown in Figure 19b. Then, the typical two-step GaAs and InAs/GaAs dot-in-a-well structure were grown on the template for the characterization of epitaxial layer. To characterize the thermal strain issue, a high-resolution XRD reciprocal space mapping was performed around (004) and (2(-)2(-)4) reflections. From peak positions in Figure 19c,d, the in-plane and out-of-plane lattice constants for GaAs (Ge) were measured to be 5.660 Å (5.659 Å) and 5.648 Å (5.654 Å), respectively. The in-plane strain ε of GaAs (Ge) was calculated to be 1.13 × 10 −3 (1.68 × 10 −4 ) by comparing the measured lattice constants with the lattice constant of bulk GaAs (5.653 Å) and Ge (5.658 Å). It was revealed that the residual thermal strain of Ge layer on the hollow Si substrate (1.68 × 10 −4 ) was 89.8% lower than that of a Ge layer on normal Si substrates (1.65 × 10 −3 ) [241]. The residual thermal strain of GaAs layer in this work (1.13 × 10 −3 ) was 29.4% lower than that of GaAs layer on the conventional Ge/Si substrates (1.6 × 10 −3 ) [246]. The reduction of thermal strain was ascribed to the presence of extra free surface. As a result, the 7 µm-thick GaAs layer, which is far beyond the typical value of the cracking thickness, can be grown on {113}-faceted Ge/Si hollow substrate. In addition, Oh et al. [83] proposed a new scheme which controls the crack formation by using notch patterns. The periodic notches, lying along parallel or perpendicular lines, were formed on Si substrate. Because the cracks were preferentially formed at the edges of the notches acting as stress concentrators, the periodic crack arrays could be achieved, resulting in a crack-free region (2 × 2 mm 2 ) where 5.8 µm-thick GaAs-based solar cell structures were grown. Recently, instead of a thick GaAs buffer layer, growing a thin Ge layer on Si was proposed [143,247]. For example, Yang et al. [143] demonstrated that although a 300 nm-thick thin Ge layer replaced the conventional 1 µm-thick GaAs buffer layer for InAs/GaAs QD lasers on Si, the fabricated lasers with thin Ge buffer showed comparable performances, in terms of TDD and lasing behavior, to the conventional QD lasers with thick GaAs buffer. This indicates that the use of thin Ge buffer is beneficial for reducing the total thickness of epitaxial layer and, therefore, minimizing of crack formation.

Summary and Conclusions
We reviewed the recent progress on the monolithic growth of III-V on Si substrates, focusing on the GaAs and InP. The discrepancies of material property between III-V and Si lead to three major challenges: (1) antiphase (inversion) boundaries; (2) TDs; and (3) thermal cracks. In order to tackle each issue, a wide variety of strategies are discussed. For the APB-free III-V growth on Si, the offcut Si substrates, which can easily suppress the formation of APBs, were typically used before. However, together with the emerging importance of CMOS-compatibility towards monolithic integration, the use of on-axis (001) Si substrates has become a paramount issue in III-V-on-Si heteroepitaxy. Accordingly, a few novel approaches, including V-grooved Si, MOCVD-grown GaAs or GaP on Si template, and MBE-grown Si buffer on Si, have been extensively demonstrated in recent years. To reduce the TDDs, a lot of methods, including various nucleation layer, multi-step growth buffer layer, defect filter layers, and so on, have been developed, resulting in the low TDD (~low 10 6 cm −2 for GaAs). However, the InP-on-Si produces higher TDD (~10 7 cm −2 ) than GaAs-on-Si, mainly due to larger lattice mismatch (~8%) between InP and Si. For the thermal crack issue, reducing the total thickness of epitaxial layer and minimizing the crystal imperfections (crack nucleation sites) are basic solution for hindering crack formation. However, because the crystal imperfections and thick buffer layers are inevitable in III-V/Si heteroepitaxy, various approaches using patterned substrates, Ge on patterned Si, and thin Ge buffer have been investigated.
Even though major obstacles for III-V-on-Si heteroepitaxy, such as APBs and thermal cracks, are resolved now, the quality of III-V layers on on-axis Si is still unsatisfactory for the deployment on the PICs or ICs. Compared with III-V devices on native substrates showing very low TDD (~10 4 cm −2 ), it is particularly challenging to reduce the TDD of III-V devices on Si below the order of 10 6 cm −2 . In addition, most of III-V/Si heteroepitaxy essentially require thick buffer layers, which reduces the integration compatibility of III-V devices with other components in PICs and ICs.
Therefore, further efforts should be devoted to improving the quality of the III-V layer on Si in an integration-compatible way, in order to fully exploit the potential benefits of monolithically integrated III-V on Si-based platform. Nevertheless, an unprecedented rate of the recent development in III-V-on-Si heteroepitaxy, driven by the emerging issue of monolithic integration in Si photonics, implies that the monolithic integration of III-V on Si is likely to be realized in the near future.

Conflicts of Interest:
The authors declare no conflict of interest.