Experimental and Modeling Study on the High-Performance p++-GaAs/n++-GaAs Tunnel Junctions with Silicon and Tellurium Co-Doped InGaAs Quantum Well Inserted

The development of high-performance tunnel junctions is critical for achieving high efficiency in multi-junction solar cells (MJSC) that can operate at high concentrations. We investigate silicon and tellurium co-doping of InGaAs quantum well inserts in p++-GaAs/n++-GaAs tunnel junctions and report a peak current density as high as 5839 A cm−2 with a series resistance of 5.86 × 10−5 Ω cm2. In addition, we discuss how device performance is affected by the growth temperature, thickness, and V/III ratio in the InGaAs layer. A simulation model indicates that the contribution of trap-assisted tunneling enhances carrier tunneling.


Introduction
Solar energy is a renewable and environmentally friendly source of energy. Efforts to generate greater electric power from solar energy have benefited from the high efficiency of solar-cell technology [1]. Tunnel junctions are an important component of multi-junction solar cells because they connect the subcells, where each subcell is designed to absorb a specific range within the solar spectrum. Therefore, as the number of subcells increases, the overall absorption of the solar spectrum is enhanced and the thermalization losses are reduced, resulting in a 6-junction solar cell with an efficiency as high as 47.1% [2]. The peak tunneling current density of tunnel junctions must be greater than the photocurrent density of the devices, and the tunnel junctions should have low electrical resistivity and high optical transparency [3].
The peak tunneling current is described below [4]: where E g is the energy bandgap of the depletion region, and N eff = (N p++ N n++ )/(N p++ + N n++ ) is the effective doping concentration, where N p++ and N n++ are the doping concentrations of the p++and n++ regions, respectively. Equation (1) implies that increased effective doping concentration or a A promising way to improve the electrical performance of the tunnel junction is to insert a quantum well (QW) in the p-n interface [8,9]. The band structure of the tunnel junctions with and without quantum well were calculated by solving Poisson's equation, taking the bandgap narrow into account. As shown in Figure 1, the tunneling distance is shortened with the In0.07GaAs quantum well inserted due to the band offset, so a higher peak tunneling current density can be obtained. However, K. Louarn et al. obtained a peak tunneling current of 30 A cm −2 by using a silicon-doped InGaAs quantum well inserted in a GaAs tunnel junction, which does not satisfy the requirements for the HCPV system [10]. Band structure of (1) p ++ -GaAs//n ++ -In0.07GaAs/n ++ -GaAs (solid line) and (2) p ++ -GaAs/n ++ -GaAs (dashed line) tunnel junctions. The differences in band bending shorten the tunneling distance for the InGaAs quantum well inserted in the GaAs tunnel junction structure. Band structure of (1) p ++ -GaAs//n ++ -In 0.07 GaAs/n ++ -GaAs (solid line) and (2) p ++ -GaAs/n ++ -GaAs (dashed line) tunnel junctions. The differences in band bending shorten the tunneling distance for the InGaAs quantum well inserted in the GaAs tunnel junction structure.
In this work, we proposed the silicon (Si) and tellurium (Te) co-doped InGaAs quantum well inserts in a p ++ -GaAs/n ++ -GaAs tunnel junction. Te likely acts as a surfactant that helps the incorporation of Si [11], and Si compensates for the delay time between the injection of DeTe into the reactor and the onset of Te incorporation into the epitaxial layer [12], resulting in a higher doping level in this layer.
The present study investigates the performance of the tunnel junction device, which is affected by the growth conditions of the co-doped InGaAs layer, including the temperature, thickness, and V/III ratio. A peak tunneling current density of 5839 A cm −2 with a resistance of 5.86 × 10 −5 Ω cm 2 is Crystals 2020, 10, 1092 3 of 10 achieved in this study. In addition, a simulation model was proposed to investigate the high peak tunneling current density.

Materials and Methods
By using metal-organic chemical vapor deposition (MOCVD), a series of tunnel junctions were grown on (100) n-type GaAs substrates misoriented 6 • toward the <111> A direction. We used C (CBr 4 source) and Si (Si 2 H 6 source) as p-and n-type dopants, respectively, and the InGaAs quantum well layer was doped with Si and Te (DeTe source). Figure 2 shows a typical tunnel junction structure, which consists of a 30 nm thick n ++ (1 × 10 19 cm −3 ) GaAs layer and a 20 nm thick p ++ (1 × 10 20 cm −3 ) GaAs layer, with an InGaAs quantum well layer embedded at the p ++ -n ++ junction interface. The doping level was assessed by using the electrical capacitance-voltage (ECV) profile and secondary ion mass spectroscopy (SIMS). The tunnel junction was surrounded by a 150 nm n-type (2 × 10 18 cm −3 ) GaAs buffer layer and a 100 nm p-type (5 × 10 19 cm −3 ) GaAs cap layer on the top to ensure good ohmic contact. The growth conditions of the InGaAs quantum well layer were varied, as summarized in Table 1.

Materials and Methods
By using metal-organic chemical vapor deposition (MOCVD), a series of tunnel junctions were grown on (100) n-type GaAs substrates misoriented 6° toward the <111> A direction. We used C (CBr4 source) and Si (Si2H6 source) as p-and n-type dopants, respectively, and the InGaAs quantum well layer was doped with Si and Te (DeTe source). Figure 2 shows a typical tunnel junction structure, which consists of a 30 nm thick n ++ (1 × 10 19 cm −3 ) GaAs layer and a 20 nm thick p ++ (1 × 10 20 cm −3 ) GaAs layer, with an InGaAs quantum well layer embedded at the p ++ -n ++ junction interface. The doping level was assessed by using the electrical capacitance-voltage (ECV) profile and secondary ion mass spectroscopy (SIMS). The tunnel junction was surrounded by a 150 nm n-type (2 × 10 18 cm −3 ) GaAs buffer layer and a 100 nm p-type (5 × 10 19 cm −3 ) GaAs cap layer on the top to ensure good ohmic contact. The growth conditions of the InGaAs quantum well layer were varied, as summarized in Table 1.  Table 1. The tunnel junction devices were patterned to different sizes, and chemical etching was used to form square mesa structures of 50 × 50, 100 × 100, 200 × 200, 500 × 500, 1000 × 1000, and 1500 × 1500 µm 2 . Figure 3 schematically illustrates the device structure. A AuGe/Ni/Au alloyed metal was sputtered onto the backside of the thinned substrates. The devices were fabricated by using conventional photolithographic and wet-etching techniques, and 100 nm SiOx was deposited by plasma-enhanced chemical vapor deposition (PECVD) to isolate the mesa sidewalls. A Ti/Pt/Au top contact metal was deposited by thermal evaporation. To ensure accurate resistance measurements, the four-probe technique was used to measure the J-V curve.  Table 1. The tunnel junction devices were patterned to different sizes, and chemical etching was used to form square mesa structures of 50 × 50, 100 × 100, 200 × 200, 500 × 500, 1000 × 1000, and 1500 × 1500 µm 2 . Figure 3 schematically illustrates the device structure. A AuGe/Ni/Au alloyed metal was sputtered onto the backside of the thinned substrates. The devices were fabricated by using conventional photolithographic and wet-etching techniques, and 100 nm SiO x was deposited by plasma-enhanced chemical vapor deposition (PECVD) to isolate the mesa sidewalls. A Ti/Pt/Au top contact metal was deposited by thermal evaporation. To ensure accurate resistance measurements, the four-probe technique was used to measure the J-V curve.

Devices Performance of the Tunnel Junctions
We investigated how device performance is affected by growth temperature, thickness, and V/III ratio of the In0.07GaAs layer.

Influence of Growth Temperature
As shown in Figure 4, the J-V curve depends on the growth temperature, with both the peak current density and resistance changes. The results are summarized in rows a-1 to a-3 of Table 2. As the growth temperature decreases from 600 to 550 °C, the peak current density increases from 16 to 2130 A cm −2 , and the resistance decreases from 1.25 × 10 −2 to 1.17 × 10 −4 Ω cm 2 .

Devices Performance of the Tunnel Junctions
We investigated how device performance is affected by growth temperature, thickness, and V/III ratio of the In 0.07 GaAs layer.

Influence of Growth Temperature
As shown in Figure 4, the J-V curve depends on the growth temperature, with both the peak current density and resistance changes. The results are summarized in rows a-1 to a-3 of Table 2. As the growth temperature decreases from 600 to 550 • C, the peak current density increases from 16 to 2130 A cm −2 , and the resistance decreases from 1.25 × 10 −2 to 1.17 × 10 −4 Ω cm 2 .  The growth temperature is a critical factor for Te incorporation, which occupies the arsenic sublattice, especially when aiming for high doping levels. The decrease in carrier concentration with increasing growth temperature can be explained as follows: As the growth temperature increases, the degree of thermal cracking of arsine increases, arsenic overpressure occurs, and the concentration of arsenic vacancies decreases, which reduces the concentration of substitutional vacancies for tellurium [13].

Influence of Thickness
Consider the results shown in Figure 5 and in rows b-1 and a-3 of Table 2. As the In0.07GaAs  The growth temperature is a critical factor for Te incorporation, which occupies the arsenic sublattice, especially when aiming for high doping levels. The decrease in carrier concentration with increasing growth temperature can be explained as follows: As the growth temperature increases, the degree of thermal cracking of arsine increases, arsenic overpressure occurs, and the concentration of arsenic vacancies decreases, which reduces the concentration of substitutional vacancies for tellurium [13].

Influence of Thickness
Consider the results shown in Figure 5 and in rows b-1 and a-3 of Table 2. As the In 0.07 GaAs thickness increases from 11 to 16 nm, the peak current density increases from 1222 to 2130 A cm −2 , and the resistance decreases from 1.94 × 10 −4 to 1.17 × 10 −4 Ω cm 2 . The growth temperature is a critical factor for Te incorporation, which occupies the arsenic sublattice, especially when aiming for high doping levels. The decrease in carrier concentration with increasing growth temperature can be explained as follows: As the growth temperature increases, the degree of thermal cracking of arsine increases, arsenic overpressure occurs, and the concentration of arsenic vacancies decreases, which reduces the concentration of substitutional vacancies for tellurium [13].

Influence of Thickness
Consider the results shown in Figure 5 and in rows b-1 and a-3 of Table 2. As the In0.07GaAs thickness increases from 11 to 16 nm, the peak current density increases from 1222 to 2130 A cm −2 , and the resistance decreases from 1.94 × 10 −4 to 1.17 × 10 −4 Ω cm 2 . According to K. Louarn et al. [3], with a thick InGaAs layer, the depletion region expands because the p-side doping concentration exceeds that of the n side. Increasing the thickness of the nside InGaAs layer reduces the band bending that extends up to the n-GaAs layer and increases the density of states of the direct band-to-band tunneling (DBBT) process [14], resulting in an increased peak tunneling current density because the tunneling probability is increased. With a thin InGaAs According to K. Louarn et al. [3], with a thick InGaAs layer, the depletion region expands because the p-side doping concentration exceeds that of the n side. Increasing the thickness of the n-side InGaAs layer reduces the band bending that extends up to the n-GaAs layer and increases the density of states of the direct band-to-band tunneling (DBBT) process [14], resulting in an increased peak tunneling current density because the tunneling probability is increased. With a thin InGaAs layer, a significant band offset occurs at the n ++ -GaAs/n ++ -InGaAs interface due to band misalignment, resulting in a quantized energy level due to the potential drop near the tunneling area. Quantum confinement reduces the density of states during the DBBT process, resulting in the reduction of the tunneling probability. Increasing the thickness of the InGaAs quantum well layer reduces the quantum confinement and weakens the discretization of states in the tunnel junction area.

Influence of V/III Ratio
Consider the results shown in Figure 6 and in rows c-1, c-2, and a-3 of Table 2. As the V/III ratio decreases from 74 to 5, the peak current density increases from 2130 to 5839 A cm −2 , and the resistance decreases from 1.17 × 10 −4 to 5.86 × 10 −5 Ω cm 2 .
layer, a significant band offset occurs at the n ++ -GaAs/n ++ -InGaAs interface due to band misalignment, resulting in a quantized energy level due to the potential drop near the tunneling area. Quantum confinement reduces the density of states during the DBBT process, resulting in the reduction of the tunneling probability. Increasing the thickness of the InGaAs quantum well layer reduces the quantum confinement and weakens the discretization of states in the tunnel junction area.

Influence of V/III Ratio
Consider the results shown in Figure 6 and in rows c-1, c-2, and a-3 of Table 2. As the V/III ratio decreases from 74 to 5, the peak current density increases from 2130 to 5839 A cm −2 , and the resistance decreases from 1.17 × 10 −4 to 5.86 × 10 −5 Ω cm 2 . Decreasing the V/III ratio in the arsine flow at a fixed dopant flow rate increases the probability of the Te substitution into arsenic vacancies due to the fact that Te atoms are n dopants. As shown in Table 2, a higher V/III ratio leads to a lower doping concentration in this layer, we see that lowest V/III ratio used (5), corresponding to a doping concentration up to 5.09 × 10 19 cm −3 is reached, which is already above the maximum doping level of 1 × 10 19 cm −3 achievable with Si dopant.

Role of Trap-Assisted Tunneling
The high peak tunneling current of this study cannot be explained as the usual carrier tunneling due to the doping levels and materials [15]. The contribution of the trap-assisted tunneling mechanism must be considered, which may enhance the carrier tunneling. The heavy doping of the InGaAs layer tends to create clusters [16], and the relaxation of the lattice mismatch between the InGaAs and GaAs layers promotes the formation of defects, which can act as traps in the trap-assisted tunneling (TAT) process [17].
The high peak current density is investigated by using a simulation model implemented in Crosslight APSYS software and that includes a direct band-to-band tunneling [18], bandgap narrowing, and trap-assisted tunneling. In the APSYS simulator, the tunneling probability is solved by Wenzel-Kramers-Brillouin (WKB) approximation and described as following [19]: (3) Decreasing the V/III ratio in the arsine flow at a fixed dopant flow rate increases the probability of the Te substitution into arsenic vacancies due to the fact that Te atoms are n dopants. As shown in Table 2, a higher V/III ratio leads to a lower doping concentration in this layer, we see that lowest V/III ratio used (5), corresponding to a doping concentration up to 5.09 × 10 19 cm −3 is reached, which is already above the maximum doping level of 1 × 10 19 cm −3 achievable with Si dopant.

Role of Trap-Assisted Tunneling
The high peak tunneling current of this study cannot be explained as the usual carrier tunneling due to the doping levels and materials [15]. The contribution of the trap-assisted tunneling mechanism must be considered, which may enhance the carrier tunneling. The heavy doping of the InGaAs layer tends to create clusters [16], and the relaxation of the lattice mismatch between the InGaAs and GaAs layers promotes the formation of defects, which can act as traps in the trap-assisted tunneling (TAT) process [17].
The high peak current density is investigated by using a simulation model implemented in Crosslight APSYS software and that includes a direct band-to-band tunneling [18], bandgap narrowing, and trap-assisted tunneling. In the APSYS simulator, the tunneling probability is solved by Wenzel-Kramers-Brillouin (WKB) approximation and described as following [19]: Crystals 2020, 10, 1092 where E ⊥ and E are the electron kinetic energies in perpendicular and parallel to the tunneling direction, respectively, E is a measure of the significance of perpendicular momentum, P 0 is the tunneling probability with zero perpendicular momentum, m * is the effective tunneling mass. With a highly doped InGaAs quantum well inserted in the GaAs tunnel junction, bandgap narrowing should be considered in the model [20]. The bandgap narrowing is expressed as where A and B are constants taken from Slotboom [21], and N is the dopant concentration.
The TAT model is based on the assumption that the traps are able to emit carriers and thus generate a current flux, which is expressed as [22]: where S TAT is the emission rate, N trap is the bulk trap density, F is the electrical field, f T is a correction factor due to temperature, related to thermal activation of trapped carriers. The Poole-Frenkel model of field dependence is implemented [22], where the Poole-Frenkel shift of the trap level is expressed as: To adapt the high peak tunneling current of the sample c-2, two free changeable parameters: the trap carrier lifetimes (t n , t p ) and the Poole-Frenkel shift (∆E PF ) are used to calibrate the simulation model. Figure 7 shows how the model be tuned to get a good agreement between the simulated and experimental results, including peak tunneling current values and the secondary peak values. With lower t p and higher Poole-Frenkel shifts, the peak tunneling current values and secondary peak values increase. The simulation results are consistent with experimental data for trap carrier lifetimes of t n = 0.45 × 10 −4 s and t p = 4 × 10 −2 s, and with a Poole-Frenkel shift in the trap level of 1.41 eV, respectively. However, the simulation results are not consistent with the experimental data in the region of negative differential resistance (NDR) because of the instability of the secondary peak [23], which is probably caused by the "two-step" tunneling through the trap states [24]. However, Figure 8 shows that the peak tunneling current density decreases if the TAT effect is not taken into account, which indicates that the trap-assisted tunneling enhances the peak tunneling current values. Crystals 2020, 10

Conclusions
We implement Si and Te co-doped InGaAs quantum well inserts in a GaAs tunnel junction and obtain the result with a peak current density as high as 5839 A cm −2 and a series resistance of 5.86 × 10 −5 Ω cm 2 . The performance of the devices is investigated at various growth conditions of the InGaAs layer, including the growth temperature, thickness, and V/III ratio. A simulation model is used to investigate the performance of the devices, and the results indicate that the trap-assisted tunneling contributes to increasing the peak tunneling current.

Conclusions
We implement Si and Te co-doped InGaAs quantum well inserts in a GaAs tunnel junction and obtain the result with a peak current density as high as 5839 A cm −2 and a series resistance of 5.86 × 10 −5 Ω cm 2 . The performance of the devices is investigated at various growth conditions of the InGaAs layer, including the growth temperature, thickness, and V/III ratio. A simulation model is used to investigate the performance of the devices, and the results indicate that the trap-assisted tunneling contributes to increasing the peak tunneling current.