A High-Frequency-Compatible Miniaturized Bandpass Filter with Air-Bridge Structures Using GaAs-Based Integrated Passive Device Technology

This paper reports on the use of gallium arsenide-based integrated passive device technology for the implementation of a miniaturized bandpass filter that incorporates an intertwined circle-shaped spiral inductor and an integrated center-located capacitor. Air-bridge structures were introduced to the outer inductor and inner capacitor for the purpose of space-saving, thereby yielding a filter with an overall chip area of 1178 μm × 970 μm. Thus, not only is the chip area minimized, but the magnitude of return loss is also improved as a result of selective variation of bridge capacitance. The proposed device possesses a single passband with a central frequency of 1.71 GHz (return loss: 32.1 dB), and a wide fractional bandwidth (FBW) of 66.63% (insertion loss: 0.50 dB). One transmission zero with an amplitude of 43.42 dB was obtained on the right side of the passband at 4.48 GHz. Owing to its miniaturized chip size, wide FBW, good out-band suppression, and ability to yield high-quality signals, the fabricated bandpass filter can be implemented in various L-band applications such as mobile services, satellite navigation, telecommunications, and aircraft surveillance.


Introduction
With the rapid development of modern wireless and telecommunication systems, microwave filters have come to play an important role in various radio frequency (RF)/microwave applications because they allow frequency selection. Among the various types of microwave filters, bandpass filters (BPFs) have been extensively studied as a key building block in the design of RF/microwave integrated circuits and systems. However, emerging applications continue to challenge BPF efficacy with increasingly rigorous demands for lower cost, smaller size, higher performance, etc. [1][2][3].
To satisfy the increasingly stringent requirements of RF and microwave systems, a wide range of materials and techniques that can be used to modify existing lumped passive components have been incorporated into recently developed fabrication processes [4]. Recent advances in novel fabrication techniques, including the implementation of low-temperature co-fired ceramics (LTCC), high-temperature superconductor (HTS), micro-electromechanical system (MEMS), monolithic microwave integrated circuit (MMIC), and micro-fabrication techniques, have accelerated the rapid development of filters for various RF/microwave applications [5]. With LTCC technology, a variety of passive components such as strip lines, filters, antennas, and resonators, which are manufactured by using inexpensive yet highly conductive metals with low electrical resistance and low conductor loss

Equivalent Circuit
As illustrated in Figure 1, a quasi-interdigital capacitor was fabricated between the two divisions of a circle-shaped spiral inductor to build up a compact RF resonator. The proposed BPF was constructed with three copper layers, which, from bottom to top, are the Bond layer, Text layer, and Leads layer, having thicknesses of 5 µm, 1.8 µm, and 5 µm, respectively. Figure 2a-c illustrates the configurations of each of these three layers; their geometric parameters are respectively listed in Tables 1-3. A schematic diagram showing the cross-sectional view of the fabricated chip for the IPD is presented in Figure 2d.

Equivalent Circuit
As illustrated in Figure 1, a quasi-interdigital capacitor was fabricated between the two divisions of a circle-shaped spiral inductor to build up a compact RF resonator. The proposed BPF was constructed with three copper layers, which, from bottom to top, are the Bond layer, Text layer, and Leads layer, having thicknesses of 5 μm, 1.8 μm, and 5 μm, respectively. Figure 2a-c illustrates the configurations of each of these three layers; their geometric parameters are respectively listed in Tables 1-3. A schematic diagram showing the cross-sectional view of the fabricated chip for the IPD is presented in Figure 2d.     The proposed BPF can be simplified as an LC resonant circuit, where an inductor (L) and a capacitor (C) are connected and have a resonant frequency, which is determined by the equation below: (1) where L and C denote the inductance and capacitance, respectively. Moreover, the transmission zero can be derived using: where mid is the midband frequency, Ω c is the passband cut-off frequency of the higher frequency area, and is the fractional bandwidth, which can be calculated using: and where 1 and 2 indicate the passband-edge angular frequency, and 0 denotes the center frequency. Figure 3 illustrates the complex equivalent circuit model with three laminated layers; R0 and L0 represent the resistance and inductance, respectively, of the electrodes and terminations. Because of parasitic effects, the capacitance and resistance of the substrate between the planar pattern and The proposed BPF can be simplified as an LC resonant circuit, where an inductor (L) and a capacitor (C) are connected and have a resonant frequency, which is determined by the equation below: where L and C denote the inductance and capacitance, respectively. Moreover, the transmission zero can be derived using: where ω mid is the midband frequency, Ω c is the passband cut-off frequency of the higher frequency area, and FBW is the fractional bandwidth, which can be calculated using: and where ω 1 and ω 2 indicate the passband-edge angular frequency, and ω 0 denotes the center frequency. Figure 3 illustrates the complex equivalent circuit model with three laminated layers; R 0 and L 0 represent the resistance and inductance, respectively, of the electrodes and terminations. Because of parasitic effects, the capacitance and resistance of the substrate between the planar pattern and ground take the form of C G and R G , respectively [23]. R i , L i , and C i (i = 1, 2, 3) are the resistance, inductance, and coupling capacitance between neighboring turns of the Bond layer, Text layer, and Leads layer, respectively. In addition, C inter is the capacitance of the inner quasi-interdigital capacitor of the bottom Bond layer. Moreover, C SiN is the capacitance of the SiN x layer between the substrate and the pattern.
Micromachines 2018, 9, x 5 of 10 ground take the form of CG and RG, respectively [23]. Ri, Li, and Ci (i = 1, 2, 3) are the resistance, inductance, and coupling capacitance between neighboring turns of the Bond layer, Text layer, and Leads layer, respectively. In addition, Cinter is the capacitance of the inner quasi-interdigital capacitor of the bottom Bond layer. Moreover, CSiN is the capacitance of the SiNx layer between the substrate and the pattern. The proposed BPF has a multilayer structure, which induces various parasitic effects at high frequencies [24]. The second-order coupling capacitance Cp2 represents the parasitic effect between two adjacent layers and was implemented at high frequencies. The coupling capacitance between these layers is related to the number of layers, the overlay area, and the relative dielectric constant of the materials.
The above-listed parameters CG, RG, CSiN, Ri, Li, Ci, and Cinter were calculated as follows: where sub and sub are the capacitance and conductance per unit area of the gallium arsenide substrate, and SiN and SiN are the dielectric constant and thickness of the SiNx layer separating the pattern and substrate, respectively. Then, where is the resistance coefficient, is the total circle length, is the conductor width, is the skin depth, is the thickness of the metal line, 0 is the resonance frequency, is the dielectric constant, ′ is the finger length, and ′ is the finger width [25]. The proposed BPF has a multilayer structure, which induces various parasitic effects at high frequencies [24]. The second-order coupling capacitance C p2 represents the parasitic effect between two adjacent layers and was implemented at high frequencies. The coupling capacitance between these layers is related to the number of layers, the overlay area, and the relative dielectric constant of the materials.

Current Density
The above-listed parameters C G , R G , C SiN , R i , L i , C i , and C inter were calculated as follows: where C sub and G sub are the capacitance and conductance per unit area of the gallium arsenide substrate, and ε SiN and t SiN are the dielectric constant and thickness of the SiN x layer separating the pattern and substrate, respectively. Then, where ρ is the resistance coefficient, l is the total circle length, W is the conductor width, δ is the skin depth, t is the thickness of the metal line, f 0 is the resonance frequency, ε r is the dielectric constant, l is the finger length, and W is the finger width [25].

Current Density
Advanced Design System (ADS) software (Version 2016.01, Keysight Technologies, Inc., Santa Rosa, CA, USA) was employed as a unified interface to simulate momentum in an electromagnetic simulation purpose to evaluate the system design in terms of S-parameter calculation accuracy, surface current, and fields of various planar circuits, including microstrip, stripline, coplanar waveguide, slotline, and other topologies. Interlayer topologies such as air-bridges and vias were incorporated to enable the simulation of multilayer RF/microwave-based printed circuit boards (PCBs), integrated circuits, and multichip modules. Additionally, the simulation was performed in 3D in order to yield a more comprehensive representation of the current flow through slots and conductors through varying degrees of shading, arrows, and contours. The simulated frequency points were selected adaptively for the computation performed through a wide frequency domain that will require a large amount of CPU hardware resources and disk space. Thus, although the frequency range for the electromagnetic (EM) simulation setup was set as 0.1 GHz to 10 GHz, the following 10 frequency points were selected and implemented in the simulation: 0.1 GHz, 1.2 GHz, 1.75 GHz, 3.4 GHz, 5.05 GHz, 6.7 GHz, 7.525 GHz, 8.35 GHz,9.175 GHz, and 10 GHz. Figure 4a shows the variation of current density under different frequencies with the effects of 1.75 GHz on the simulated current density throughout the proposed BPF illustrated in Figure 4b, which shows that the current flowed through most segments of the simulated BPF with a relatively high density when the frequency was 1.75 GHz, which is within the passband. Advanced Design System (ADS) software (Version 2016.01, Keysight Technologies, Inc., Santa Rosa, CA, USA) was employed as a unified interface to simulate momentum in an electromagnetic simulation purpose to evaluate the system design in terms of S-parameter calculation accuracy, surface current, and fields of various planar circuits, including microstrip, stripline, coplanar waveguide, slotline, and other topologies. Interlayer topologies such as air-bridges and vias were incorporated to enable the simulation of multilayer RF/microwave-based printed circuit boards (PCBs), integrated circuits, and multichip modules. Additionally, the simulation was performed in 3D in order to yield a more comprehensive representation of the current flow through slots and conductors through varying degrees of shading, arrows, and contours. The simulated frequency points were selected adaptively for the computation performed through a wide frequency domain that will require a large amount of CPU hardware resources and disk space. Thus, although the frequency range for the electromagnetic (EM) simulation setup was set as 0.1 GHz to 10 GHz, the following 10 frequency points were selected and implemented in the simulation: 0.1 GHz, 1.2 GHz, 1.75 GHz, 3.4 GHz, 5.05 GHz, 6.7 GHz, 7.525 GHz, 8.35 GHz, 9.175 GHz, and 10 GHz. Figure 4a shows the variation of current density under different frequencies with the effects of 1.75 GHz on the simulated current density throughout the proposed BPF illustrated in Figure 4b, which shows that the current flowed through most segments of the simulated BPF with a relatively high density when the frequency was 1.75 GHz, which is within the passband.  GHz on the simulated current density throughout the proposed BPF.

Results and Discussion
The influence of the inner radius of the outer inductor on performance was experimentally explored, as this parameter was varied from 250 μm to 350 μm in intervals of 25 μm. Figure 5 illustrates the variation of S-parameter and other lumped parameters as functions of BPF frequency and inner radius. Figure 5a indicates that the positions of the resonant mode and transmission zero tended to shift to areas of lower frequency in response to a larger inner radius. Because the inductance will increase with a bigger inner radius, thus, according to Equation (1), the bigger the inductance, the smaller the resonant frequency. It should also be noted that the impact on S21 is more prominent. According to Equations (2)-(4), there are many terms that need to be calculated; we therefore calculated them and tabulated them all in Table 4, which shows that the location of transmission zero definitely moves to areas of lower frequency with the increase of inner radius. Furthermore, inductance, capacitance, and resistance were derived based on the Y-parameters by using the following equations:

Results and Discussion
The influence of the inner radius of the outer inductor on performance was experimentally explored, as this parameter was varied from 250 µm to 350 µm in intervals of 25 µm. Figure 5 illustrates the variation of S-parameter and other lumped parameters as functions of BPF frequency and inner radius. Figure 5a indicates that the positions of the resonant mode and transmission zero tended to shift to areas of lower frequency in response to a larger inner radius. Because the inductance will increase with a bigger inner radius, thus, according to Equation (1), the bigger the inductance, the smaller the resonant frequency. It should also be noted that the impact on S 21 is more prominent. According to Equations (2)-(4), there are many terms that need to be calculated; we therefore calculated them and tabulated them all in Table 4, which shows that the location of transmission zero definitely moves to areas of lower frequency with the increase of inner radius. Furthermore, inductance, capacitance, and resistance were derived based on the Y-parameters by using the following equations: where Y is the admittance, f is the frequency of operation, and imag and real represent the imaginary and real parts, respectively. As illustrated in Figure 5b-d, the first self-resonant frequency tended to decrease as the inner radius was increased. Furthermore, it was confirmed that, at high frequencies, the substrate capacitance reduced the self-resonant frequency (Figure 5c).
(Ω) = ( 1 (1,1) ) (14) where Y is the admittance, f is the frequency of operation, and imag and real represent the imaginary and real parts, respectively. As illustrated in Figure 5b-d, the first self-resonant frequency tended to decrease as the inner radius was increased. Furthermore, it was confirmed that, at high frequencies, the substrate capacitance reduced the self-resonant frequency (Figure 5c).  As previously mentioned, the proposed BPF was designed and simulated by using ADS software. In the design of the experimental BPF, the input and output ports were both connected to 50-Ω impedance-matching transmission lines of the PCB by golden wire bonding; the results were subsequently measured and recorded by using an Agilent 8510C vector network analyzer (VNA) (Agilent Technologies, Santa Clara, CA, USA). The experimental setup for the proposed BPF is  As previously mentioned, the proposed BPF was designed and simulated by using ADS software. In the design of the experimental BPF, the input and output ports were both connected to 50-Ω impedance-matching transmission lines of the PCB by golden wire bonding; the results were subsequently measured and recorded by using an Agilent 8510C vector network analyzer (VNA) (Agilent Technologies, Santa Clara, CA, USA). The experimental setup for the proposed BPF is illustrated in Figure 6 with enlarged views of various parts. The simulated and measured results for the BPF are depicted in Figure 7 along with photographs of the fabricated onboard chip. The results demonstrate that the proposed IPD BPF possesses a single passband with a central frequency of 1.71 GHz (return loss: 32.1 dB, insertion loss: 0.50 dB), and a wide FBW of 66.63%. One transmission zero with an amplitude of 43.42 dB was obtained on the right side of the passband at 4.48 GHz. The results of a comparison between the proposed IPD BPF and four previously developed IPD BPFs, as tabulated in Table 5, show that our device features a relatively small chip area and wide FBW.  Table 5, show that our device features a relatively small chip area and wide FBW.     Table 5, show that our device features a relatively small chip area and wide FBW.      [27] Glass-IPD <1.00 2.60 49.62 (3-dB) [28] Si-IPD 11.6 0.9/2.6 N/A [29] Si-IPD 3.9 1.7 16 (10-dB) This work GaAs-IPD 1.14 1.71 66.63 (3-dB)

Conclusions
In this paper, we reported on the design of an IPD technology-based BPF that was fabricated onto a gallium arsenide substrate, and was able to realize a small footprint, a wide FBW, a good out-band suppression, and high-frequency operational capability. The chip was fabricated onto a 6-in. gallium arsenide substrate with a dielectric constant of 12.85, loss tangent of 0.006, and thickness of 200.1 µm. Additionally, an equivalent circuit that considers the second-order parasitic effect was modeled in order to simulate device behavior under high-frequency operation. Furthermore, the current distributions were simulated for four different frequencies by using the 3D EM current simulator in ADS software. The influence of the geometric structure was also explored by varying the inner radius. The theoretical predictions and measurements performed on the fabricated bandpass filter were found to be in agreement, thus indicating that the proposed IPD BPF is a good candidate for RF/Microwave applications.