Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.


CMOS/MEMS Accelerometer
In this work, the application-specific integrated circuit (ASIC) compatible 1P6M process of UMC 0.18 µm mixed-signal/RF CMOS process is adopted. The micromachining process is performed on the wafer of standard CMOS process. Figure 1a shows the top view of the proposed accelerometer. The proposed CMOS/MEMS accelerometer consists of proof mass, sensing fingers, single-folded springs, and a curl-matching frame. It is equivalent to a second-order mass-spring-damper mechanical model, as in Figure 1b. The displacement is transformed into capacitance ∆C by sensing fingers. The circuit model in Figure 1c is simulated with readout circuit. The circuit is simulated in Cadence design environment by Spectre simulator. The side view of the CMOS process with micromachining post process is shown in Figure 1d.
Micromachines 2018, 9, x FOR PEER REVIEW 2 of 13 to analog converter (DAC). A capacitor array is used to apply a signal correction by placing digitally controlled capacitors in parallel to the sensor capacitors. The second part consists of a current DAC placed within a differential amplifier to balance out asymmetric currents caused by the signal offset. Standard CMOS process is suitable for implementing digital offset trimming. Hence, the offset trimming mechanism is presented to overcome the offset from sensor and interface circuit.
The design target refers to ADXL103. ADXL103 is a high precision, low power single-axis accelerometer with a signal conditioned voltage outputs from Analog Devices. ADXL103 measures acceleration with a full-scale range of ±1.7 g, sensitivity of 1000 mV/g, noise floor of 110 μg/√Hz, and power of 3.5 mW. ADXL103 can measure both dynamic acceleration and static acceleration. The main application is for navigation and motion detection [10].
The design target of our readout circuit is ±1 g sensing range, noise floor of 10 μg/√Hz, and power of milli-watt scale, which is suitable for navigation and motion detection. Based on our previous work [11], the UMC 0.18 μm CMOS/MEMS process is adopted for sensor and circuit implementation. This paper presents a low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme. Section 2 describes the CMOS/MEMS accelerometer and the circuit design of the low noise and low zero-g offset readout. In Section 3, describes the measurement results of the proposed readout scheme. Section 4 presents the discussion of the proposed readout scheme by comparison of performance with the state-of-the-art and presents the conclusions of this work.

CMOS/MEMS Accelerometer
In this work, the application-specific integrated circuit (ASIC) compatible 1P6M process of UMC 0.18 μm mixed-signal/RF CMOS process is adopted. The micromachining process is performed on the wafer of standard CMOS process. Figure 1a shows the top view of the proposed accelerometer. The proposed CMOS/MEMS accelerometer consists of proof mass, sensing fingers, single-folded springs, and a curl-matching frame. It is equivalent to a second-order mass-spring-damper mechanical model, as in Figure 1b. The displacement is transformed into capacitance ΔC by sensing fingers. The circuit model in Figure 1c is simulated with readout circuit. The circuit is simulated in Cadence design environment by Spectre simulator. The side view of the CMOS process with micromachining post process is shown in Figure 1d.

Readout Circuit Design
The readout circuit has two main parts. The first part is a low noise unit and contains the main amplifier and pre-amplifier. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The second part is a sensor-trimming unit that is an 8-bit trimming capacitor.
The architecture is shown in Figure 2. The sensing signal is modulated to 333 kHz and passes through amplification stages, track-and-hold amplifier (THA), output stage, and band limiting RC filter. The overall performance summery is listed in Table 1.   Figure 3 shows the working principle of the sensor readout with the simplified modulation signal, which can be found in Figure 3b. The modulation frequency is 333.33 kHz. The sensing signal in Figure 3a is modulated by modulation clock signal and passes through amplifier stages in Figure  3c,d. The demodulation is achieved by track-and-hold stage, which is equivalent to multiply the

Readout Circuit Design
The readout circuit has two main parts. The first part is a low noise unit and contains the main amplifier and pre-amplifier. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The second part is a sensor-trimming unit that is an 8-bit trimming capacitor.
The architecture is shown in Figure 2. The sensing signal is modulated to 333 kHz and passes through amplification stages, track-and-hold amplifier (THA), output stage, and band limiting RC filter. The overall performance summery is listed in Table 1.

Readout Circuit Design
The readout circuit has two main parts. The first part is a low noise unit and contains the main amplifier and pre-amplifier. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The second part is a sensor-trimming unit that is an 8-bit trimming capacitor.
The architecture is shown in Figure 2. The sensing signal is modulated to 333 kHz and passes through amplification stages, track-and-hold amplifier (THA), output stage, and band limiting RC filter. The overall performance summery is listed in Table 1.   Figure 3 shows the working principle of the sensor readout with the simplified modulation signal, which can be found in Figure 3b. The modulation frequency is 333.33 kHz. The sensing signal in Figure 3a is modulated by modulation clock signal and passes through amplifier stages in Figure  3c,d. The demodulation is achieved by track-and-hold stage, which is equivalent to multiply the   Figure 3 shows the working principle of the sensor readout with the simplified modulation signal, which can be found in Figure 3b. The modulation frequency is 333.33 kHz. The sensing signal in Figure 3a is modulated by modulation clock signal and passes through amplifier stages in Figure 3c,d. The demodulation is achieved by track-and-hold stage, which is equivalent to multiply the demodulation signal in Figure 3e. The demodulated signal in Figure 3f passes through the zero-order hold and the signal in Figure 3g is obtained.

Low Noise Chopper Architecture
Since flicker noise is inversely proportional to frequency, the operation frequency determines the noise performance. The chopper architecture modulates the signal to chopping frequency to suppress flicker noise. The quantitative analysis is carried out at the transistor level to verify the effectiveness of the proposed architecture.
The sensing signal is modulated to 333.33 kHz by the switches (ϕA, ϕZ and ϕB), which is known as signal chopping. In this work, both the main amplifier and pre-amplifier are working at high frequency (at 333.33 kHz chopping frequency). For the conventional design in Reference [1], the sensing signal is demodulated using ϕH (at 1 MHz chopping frequency) in Figure 4. After demodulation by ϕH, the signal is further boosted by an amplifier.
The proposed low noise interface circuit is presented in Figure 5. The modulated sensing signal is first amplified by main amplifier and further boosted by the pre-amplifier. The amplified signal is demodulated by ϕA.

Low Noise Chopper Architecture
Since flicker noise is inversely proportional to frequency, the operation frequency determines the noise performance. The chopper architecture modulates the signal to chopping frequency to suppress flicker noise. The quantitative analysis is carried out at the transistor level to verify the effectiveness of the proposed architecture.
The sensing signal is modulated to 333.33 kHz by the switches (φ A , φ Z and φ B ), which is known as signal chopping. In this work, both the main amplifier and pre-amplifier are working at high frequency (at 333.33 kHz chopping frequency). For the conventional design in Reference [1], the sensing signal is demodulated using φ H (at 1 MHz chopping frequency) in Figure 4. After demodulation by φ H , the signal is further boosted by an amplifier.  The proposed low noise interface circuit is presented in Figure 5. The modulated sensing signal is first amplified by main amplifier and further boosted by the pre-amplifier. The amplified signal is demodulated by φ A .

Main Amp
Pre-amp

Modulation ϕM
Demodulation ϕL Figure 4. The simplified architecture in Reference [1]. The noise figure F of the network is defined as the ratio of the available signal-to-noise ratio at the signal-generator terminals to the available signal-to-noise ratio at its output terminals as the following equation [12].
where Fn is the noise figure for the n-th device and Gn is the power gain (linear, not in dB) of the n-th device. The design target is lower than the whole system Fsys. For the two amplifier stages, the noise of main amplifier is F1, the power gain of main amplifier is G1, and the noise of pre-amplifier is F2. The noise figure of the third stage F3 will be divided by the gain of the first two stages (the G1G2 term). Thus, the noise figures of the first two stages must be considered [12]. The simplified noise figure is given by: Two strategies are applied to lower the noise figure Fsys. The proposed circuit architecture minimize the F1 and F2 terms. First, modified the circuit architecture operates the second stage amplifier at 333.33 kHz to lower the F2 term, which reduces noise contribution from the second stage amplifier. Second, the noise factor of the first amplifier F1 is significant for the readout circuit since the F1 term is directly added to Fsys. The gain G1 is determined by the overall sensitivity. G1 is around 7.88 V/V. The noise figure F of the network is defined as the ratio of the available signal-to-noise ratio at the signal-generator terminals to the available signal-to-noise ratio at its output terminals as the following equation [12].
Total noise figure of the whole system can be expressed by Friis' Formula: where F n is the noise figure for the n-th device and G n is the power gain (linear, not in dB) of the n-th device. The design target is lower than the whole system F sys . For the two amplifier stages, the noise of main amplifier is F 1 , the power gain of main amplifier is G 1 , and the noise of pre-amplifier is F 2 . The noise figure of the third stage F 3 will be divided by the gain of the first two stages (the G 1 G 2 term). Thus, the noise figures of the first two stages must be considered [12]. The simplified noise figure is given by: Two strategies are applied to lower the noise figure F sys . The proposed circuit architecture minimize the F 1 and F 2 terms. First, modified the circuit architecture operates the second stage amplifier at 333.33 kHz to lower the F 2 term, which reduces noise contribution from the second stage amplifier. Second, the noise factor of the first amplifier F 1 is significant for the readout circuit since the F 1 term is directly added to F sys . The gain G 1 is determined by the overall sensitivity. G 1 is around 7.88 V/V.
The telescopic amplifier is shown in Figure 6a, Q 1 and Q 2 form the input differential pair, and Q 3 -Q 6 are the cascode transistors. Cascading transistors increase the voltage gain at the cost of output voltage headroom. Since the output swing requirements are very small at the first stage, on the order of several millivolts, a telescope may be used. For telescopic topology, the Q 1 , Q 2 , Q 7 , and Q 8 are the primary noise sources. The folded-cascode topology is a popular amplifier architecture as in Figure 6b. Q 1 and Q 2 form the input differential pair, and Q 5 and Q 6 are the cascode transistors, which are folded, as compared to telescopic topology. For folded-cascode topology, the Q 1 , Q 2 , Q 7 , Q 8 , Q 9 , and Q 10 are the primary noise sources. Assuming the transistors exhibit similar noise levels, folded-cascode topology suffers from greater noise than its telescopic counterpart. The telescopic topology is desirable since it has fewer noise-contributing transistors, and hence F 1 is reduced.
The telescopic amplifier is shown in Figure 6a, Q1 and Q2 form the input differential pair, and Q3-Q6 are the cascode transistors. Cascading transistors increase the voltage gain at the cost of output voltage headroom. Since the output swing requirements are very small at the first stage, on the order of several millivolts, a telescope may be used. For telescopic topology, the Q1, Q2, Q7, and Q8 are the primary noise sources. The folded-cascode topology is a popular amplifier architecture as in Figure 6b. Q1 and Q2 form the input differential pair, and Q5 and Q6 are the cascode transistors, which are folded, as compared to telescopic topology. For folded-cascode topology, the Q1, Q2, Q7, Q8, Q9, and Q10 are the primary noise sources. Assuming the transistors exhibit similar noise levels, folded-cascode topology suffers from greater noise than its telescopic counterpart. The telescopic topology is desirable since it has fewer noise-contributing transistors, and hence F1 is reduced. Spectre PNoise simulation is used for noise characterization. The PNoise simulation gives the noise response of main amplifier and pre-amplifier. Table 2 shows the comparison of noise and power at each stage. For main amplifier, Reference [1] modulates the sensing signal to 1 MHz, while the proposed architecture modulates to 333.33 kHz. For pre-amplifier, Reference [1] demodulates the sensing signal to 20 kHz, while the proposed architecture is still working at 333.33 kHz. Comparing the two frequency arrangements, the proposed architecture has 8% less noise than Reference [1] at the cost of 10% more power consumption. The simulation results verify the effectiveness of the proposed reduction architecture.

Low Zero-g Offset Design
The sensing capacitive mismatch needs to be compensated. Small capacitor in sub femto farad scale is placed in parallel with the sensing capacitors to cancel the sensor offsets. A segmented split capacitor structure is proposed to realize small capacitor, as in Figure 7. Figure 7b shows the 7-bit trimming capacitance. The most significant bit (MSB) C [7] controls the switch in Figure 7a, which determines adding trimming capacitance to the upper plane or lower plane of the accelerometer. Spectre PNoise simulation is used for noise characterization. The PNoise simulation gives the noise response of main amplifier and pre-amplifier. Table 2 shows the comparison of noise and power at each stage. For main amplifier, Reference [1] modulates the sensing signal to 1 MHz, while the proposed architecture modulates to 333.33 kHz. For pre-amplifier, Reference [1] demodulates the sensing signal to 20 kHz, while the proposed architecture is still working at 333.33 kHz. Comparing the two frequency arrangements, the proposed architecture has 8% less noise than Reference [1] at the cost of 10% more power consumption. The simulation results verify the effectiveness of the proposed reduction architecture.

Low Zero-g Offset Design
The sensing capacitive mismatch needs to be compensated. Small capacitor in sub femto farad scale is placed in parallel with the sensing capacitors to cancel the sensor offsets. A segmented split capacitor structure is proposed to realize small capacitor, as in Figure 7. Figure 7b shows the 7-bit trimming capacitance. The most significant bit (MSB) C [7] controls the switch in Figure 7a, which determines adding trimming capacitance to the upper plane or lower plane of the accelerometer. The C tm1 and C tm2 are the 7-bit trimming capacitance in Figure 7b. Trimming capacitance is estimated by using the equation below: The Ctm1 and Ctm2 are the 7-bit trimming capacitance in Figure 7b. Trimming capacitance is estimated by using the equation below: The ratio of capacitance Ct2 and Ct3 make the overall capacitance C smaller to get sub femto farad scale capacitance.

Results
The circuit is implemented in UMC 0.18 μm process. In this work, low noise readout scheme is presented. The trimming capacitor is added for zero-g offset compensation. The die photo and chip layout is shown in Figure 8.  The ratio of capacitance C t2 and C t3 make the overall capacitance C smaller to get sub femto farad scale capacitance.

Results
The circuit is implemented in UMC 0.18 µm process. In this work, low noise readout scheme is presented. The trimming capacitor is added for zero-g offset compensation. The die photo and chip layout is shown in Figure 8. The Ctm1 and Ctm2 are the 7-bit trimming capacitance in Figure 7b. Trimming capacitance is estimated by using the equation below: The ratio of capacitance Ct2 and Ct3 make the overall capacitance C smaller to get sub femto farad scale capacitance.

Results
The circuit is implemented in UMC 0.18 μm process. In this work, low noise readout scheme is presented. The trimming capacitor is added for zero-g offset compensation. The die photo and chip layout is shown in Figure 8.

CMOS/MEMS Accelerometer
The dry-etch-based post-process are used after standard CMOS process for microstructure fabrication. Figure 9 shows the cross section of the CMOS/MEMS accelerometer. The curl matching frame and the proof mass of accelerometer have the same curling.

CMOS/MEMS Accelerometer
The dry-etch-based post-process are used after standard CMOS process for microstructure fabrication. Figure 9 shows the cross section of the CMOS/MEMS accelerometer. The curl matching frame and the proof mass of accelerometer have the same curling.  Figure 10 shows the evaluation board schematic for acceleration readout measurement. The fabricated chip directly mounts on the printed circuit boards. On board oscillator generates 1 MHz clock for acceleration readout. The 1.8 V supply is generated by regulator for digital power (VddD) and analog power (VddA). The calibration readout is controlled by on-board switches. The fabricated chip directly mounts on the printed circuit boards, as shown in Figure 11.  Figure 10 shows the evaluation board schematic for acceleration readout measurement. The fabricated chip directly mounts on the printed circuit boards. On board oscillator generates 1 MHz clock for acceleration readout. The 1.8 V supply is generated by regulator for digital power (V ddD ) and analog power (V ddA ). The calibration readout is controlled by on-board switches. The fabricated chip directly mounts on the printed circuit boards, as shown in Figure 11.

Noise Considerations in Board Design
A digital circuit can produce noise at 1 MHz. Circuit noise decoupling capacitors are added at power line for digital noise reduction (1 MHz) (power line filter). Since the power line is 60 Hz, which is near 100 Hz of the sensing signal and cannot be easily filter by conventional filter. Power line noise is isolated by using battery power. The battery power passes though voltage regulator into readout circuit. The voltage regulator LM1117 is adopted, which reported RMS output noise is 0.003% of V OUT at frequency 10 Hz ≤ f ≤ 10 kHz, where V OUT is 1.8 V.
The evaluation board is placed on the LDS V408 shaker, as shown in Figure 12 for noise and sensitivity measurement. The shaker generates 1 g signal 1 kHz acceleration input. Figure 13 shows the spectrum of output voltage at the excitation. The noise floor is 421.70 µg/ √ Hz. The signal-to-noise ratio (SNR) is around 67.5 dB. Figure 10 shows the evaluation board schematic for acceleration readout measurement. The fabricated chip directly mounts on the printed circuit boards. On board oscillator generates 1 MHz clock for acceleration readout. The 1.8 V supply is generated by regulator for digital power (VddD) and analog power (VddA). The calibration readout is controlled by on-board switches. The fabricated chip directly mounts on the printed circuit boards, as shown in Figure 11.

Noise Considerations in Board Design
A digital circuit can produce noise at 1 MHz. Circuit noise decoupling capacitors are added at power line for digital noise reduction (1 MHz) (power line filter). Since the power line is 60 Hz, which is near 100 Hz of the sensing signal and cannot be easily filter by conventional filter. Power line noise is isolated by using battery power. The battery power passes though voltage regulator into readout circuit. The voltage regulator LM1117 is adopted, which reported RMS output noise is 0.003% of VOUT at frequency 10 Hz ≤ f ≤ 10 kHz, where VOUT is 1.8 V.
The evaluation board is placed on the LDS V408 shaker, as shown in Figure 12 for noise and sensitivity measurement. The shaker generates 1 g signal 1 kHz acceleration input. Figure 13 shows the spectrum of output voltage at the excitation. The noise floor is 421.70 μg/√Hz. The signal-to-noise ratio (SNR) is around 67.5 dB.
The sensitivity of the system is characterized for the two aspects, linearity and frequency response. The shaker generates 0.25 g signal to characterize the frequency response of the system as in Figure 14. The frequency range from 10 Hz to 1333.33 Hz is limited by the shaker. For the frequency around 1 kHz, the sensitivity increases due to the resonance of accelerometer.
The sensing range of readout circuit is designed for ±1 g. The readout circuit is characterized using 1 kHz signal from zero to 1.5 g as in Figure 15. The linear regression is performed for zero to 1 g input signal. For a signal larger than 1 g, the output saturates and deviates from linear operation.

Noise Considerations in Board Design
A digital circuit can produce noise at 1 MHz. Circuit noise decoupling capacitors are added at power line for digital noise reduction (1 MHz) (power line filter). Since the power line is 60 Hz, which is near 100 Hz of the sensing signal and cannot be easily filter by conventional filter. Power line noise is isolated by using battery power. The battery power passes though voltage regulator into readout circuit. The voltage regulator LM1117 is adopted, which reported RMS output noise is 0.003% of VOUT at frequency 10 Hz ≤ f ≤ 10 kHz, where VOUT is 1.8 V.
The evaluation board is placed on the LDS V408 shaker, as shown in Figure 12 for noise and sensitivity measurement. The shaker generates 1 g signal 1 kHz acceleration input. Figure 13 shows the spectrum of output voltage at the excitation. The noise floor is 421.70 μg/√Hz. The signal-to-noise ratio (SNR) is around 67.5 dB.
The sensitivity of the system is characterized for the two aspects, linearity and frequency response. The shaker generates 0.25 g signal to characterize the frequency response of the system as in Figure 14. The frequency range from 10 Hz to 1333.33 Hz is limited by the shaker. For the frequency around 1 kHz, the sensitivity increases due to the resonance of accelerometer.
The sensing range of readout circuit is designed for ±1 g. The readout circuit is characterized using 1 kHz signal from zero to 1.5 g as in Figure 15. The linear regression is performed for zero to 1 g input signal. For a signal larger than 1 g, the output saturates and deviates from linear operation.      Figure 13. The output noise spectrum.

Low Zero-g Offset Design
The sensitivity of the system is characterized for the two aspects, linearity and frequency response. The shaker generates 0.25 g signal to characterize the frequency response of the system as in Figure 14. The frequency range from 10 Hz to 1333.33 Hz is limited by the shaker. For the frequency around 1 kHz, the sensitivity increases due to the resonance of accelerometer.    The sensing range of readout circuit is designed for ±1 g. The readout circuit is characterized using 1 kHz signal from zero to 1.5 g as in Figure 15. The linear regression is performed for zero to 1 g input signal. For a signal larger than 1 g, the output saturates and deviates from linear operation.

Low Zero-g Offset Design
The trimming capacitor is controlled by the digital value from the evaluation board to eliminate the zero g offset. The zero-g offset of the system is characterized for the two aspects, static and dynamic operation.
For static operation, the system output measured without external excitation that is the zero g output. For the ideal case, the zero-g output should be zero. The difference of positive output (VOP) and negative output (VON) represents the accelerometer readout. The differential output of the sensing signal VOP and VON should be the same. Figure 16 shows the output voltage with different configurations of the trimming capacitor. For the 8'b0000_0000 configuration, the 0 fF trimming capacitor is in parallel to the sensor capacitors, which stands for zero g offset value without trimming. The circuit output is saturated. The zero-g offset is 745.06 mV, as in Figure 16a. For the 8'b1111_1111 configuration, the maximum trimming capacitance is in parallel to the sensor capacitors. The offset is 77.08 mV, as in Figure 16b. For the 8'b1001_0000 configuration, the trimming capacitance is in parallel to eliminate the zero g offset. The offset is reduced from 745.06 mV to 1.38 mV. That is, the zero g offset is reduced from 1242.63 mg to 2.30 mg, as in Figure 16c.   The trimming capacitor is controlled by the digital value from the evaluation board to eliminate the zero g offset. The zero-g offset of the system is characterized for the two aspects, static and dynamic operation.

Low Zero-g Offset Design
For static operation, the system output measured without external excitation that is the zero g output. For the ideal case, the zero-g output should be zero. The difference of positive output (VOP) and negative output (VON) represents the accelerometer readout. The differential output of the sensing signal VOP and VON should be the same. Figure 16 shows the output voltage with different configurations of the trimming capacitor. For the 8'b0000_0000 configuration, the 0 fF trimming capacitor is in parallel to the sensor capacitors, which stands for zero g offset value without trimming. The circuit output is saturated. The zero-g offset is 745.06 mV, as in Figure 16a. For the 8'b1111_1111 configuration, the maximum trimming capacitance is in parallel to the sensor capacitors. The offset is 77.08 mV, as in Figure 16b. For the 8'b1001_0000 configuration, the trimming capacitance is in parallel to eliminate the zero g offset. The offset is reduced from 745.06 mV to 1.38 mV. That is, the zero g offset is reduced from 1242.63 mg to 2.30 mg, as in Figure 16c. For dynamic operation, the excitation of 1 g 1 kHz is applied with different configurations of the trimming capacitor. For the 8'b0000_0000 configuration, the circuit output is saturated. Sensitivity is degraded to 1.61 mV/g, as in Figure 17a. For the 8'b1111_1111 configuration, the sensitivity is around 706.32 mV/g. The output exhibits nonlinear distortion, which is obviously undesirable, as in Figure 17b. For the 8'b1001_0000 configuration, the trimming capacitance is in For dynamic operation, the excitation of 1 g 1 kHz is applied with different configurations of the trimming capacitor. For the 8'b0000_0000 configuration, the circuit output is saturated. Sensitivity is degraded to 1.61 mV/g, as in Figure 17a. For the 8'b1111_1111 configuration, the sensitivity is around 706.32 mV/g. The output exhibits nonlinear distortion, which is obviously undesirable, as in Figure 17b. For the 8'b1001_0000 configuration, the trimming capacitance is in parallel to eliminate the zero g offset. The measurement shows sensitivity around 599.58 mV/g, as in Figure 17c.

Discussion and Conclusions
A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. For 1 g 100 Hz acceleration input, the whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. Table 3 compares the performance of the work proposed here to the state-of-the-art. Comparing with Reference [2], using the same 0.18 μm process node, the noise floor and zero g offset is reduced, while the overall power consumption is increased.

Discussion and Conclusions
A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 µm CMOS mixed signal UMC process is presented. For 1 g 100 Hz acceleration input, the whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. Table 3 compares the performance of the work proposed here to the state-of-the-art. Comparing with Reference [2], using the same 0.18 µm process node, the noise floor and zero g offset is reduced, while the overall power consumption is increased.