Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell–Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10−15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10−11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.


Introduction
Silicon oxide has been used as a gate dielectric material on thin film transistors for over 40 years, but as dimensions shrink, alternatives with higher dielectric constants are necessary to reduce leakage currents.While high-κ dielectrics have been investigated for their thermal stability and compatibility with Si, FinFET technology, with 3D doublegate and triple-gate transistors, has further advanced, leading to smaller, more efficient transistors with reduced power consumption [1][2][3][4][5].
The continuous downscaling of MOS devices is indispensable for increasing the transistor density and performance, leading to efficient chip functionality at higher speeds.However, this scaling poses challenges such as severe short channel effects (SCEs), increased fabrication costs, and difficulties in device processing [6][7][8].Multi-gate MOS device structures like FinFETs, which use multiple gate electrodes and an ultrathin body, have been developed to address these challenges, showing an excellent device performance at The permittivity matching TFT designs appeared [42][43][44] when the SiO 2 and SiN x gate insulators were discovered to be behaving well when neighboring the Si channel [44], and designers frequently used the Equivalent Oxide Thickness (EOT) convention [41,[45][46][47] for the determination of the thickness of hi-κ gate oxide to replace the SiO 2 or SiN x .But EOT also had its disadvantages, like its invalidity for non-planar devices due to the impact of device geometry on capacitance behavior [48] and a gate-leakage current increase when the gate oxide layer is scaled down below 2 nm [49].
With κ-grading (also called as "epsilon grading" (ε-grading), so that dielectric permittivity changes through device depth is interchangeably designated as "ε" or "κ" in different references), our aim is to match the dielectric permittivity of stages; i.e., the Si channel is followed by a dielectric material with the lowest bulk dielectric constant κ b , followed by a material with a higher κ b , then followed by a material with a higher κ b again, until the gate is reached.κ-grading together with an effective dielectric constant (κ EFF ) calculation of the staged/graded gate oxide structure is proposed for the better effectivity of gate oxide.We highlight three steps in the incorporation of this technique as follows: 1.
κ-grading is employed for stacked gate oxide.This is detailed in Section 3.1.1.

2.
Even when a single material gate dielectric is used, the Penn model [50,51] can be utilized for the calculation of effective dielectric constants of the gate oxide layer, κ EFF , as the bulk dielectric constant usage will be misleading for gate oxides with thicknesses of a few nanometers.This is detailed in Section 3.1.2.

3.
With each addition of a new laminate material, the overall effective dielectric constant of the gate oxide layer, κ EFF , can be recalculated using the Maxwell-Garnett [52] mixing formula, so that a fair mechanism is established to compare the performance of FinFETs with respect to this κ EFF as the independent variable.The mentioned calculations are given in Section 3.1.3.
Our research work offers the most comprehensive simulation work in the investigation of stacked gate oxides on FinFETs with 41 different gate oxide combinations, all with a 3 nm total thickness, adding two-stage or three-stage κ-grading features and taking an effective dielectric constant (κ EFF ) calculation into account.In this paper, we present the simulation results obtained using SILVACO ATLAS for a 3D silicon on insulator (SOI) n-FinFET structure with κ-graded stacked gate oxides.
This manuscript is divided into several sections: In Section 2, the FinFET device structure, its geometry and gate dielectric combinations, and their designations are introduced.In Section 3, details of the κ-grading, effective dielectric constant κ EFF calculation, mathematical methods for FinFET modeling, simulation tool usage, and choice of performance metrics are presented.Our simulation results are exhibited and discussed with some analysis and insights that we derived in Sections 4-6.Finally, fabrication considerations and the conclusions are reported in Sections 7 and 8.

Device Structure 2.1. FinFET Geometric Model
The 3D Technology Computer-Aided Design (TCAD) structure for a FinFET with a gate oxide with graded dielectric permittivity is shown in Figure 1.Using SILVACO ATLAS for device simulation and with a gate oxide thickness (t ox ) of 3 nm, the buried oxide (BOX) material is kept as HfO 2 and never changed through all simulations.An equal doping concentration (N d ) of 5 × 10 19 cm −3 is the used source-drain channel region.Other FinFET properties are shown in Table 1.We call this FinFET type "FinFET with κ-graded gate oxide" or "gκ-FinFET" throughout the paper.The device structure is of an n-type FinFET, comprising three gates, one on top and two at the sides of the fin-shaped channel, not isolated, but behaving as a single inversed U-shaped gate.Metal with a work function (ϕ w ) of 5 eV is applied at the gate, common for n+-doped Si channel junctionless architectures [7,27,28].Ni or CrAu alloy is suitable for this work function value, common for junctionless n-TFTs.
not isolated, but behaving as a single inversed U-shaped gate.Metal with a work function (φw) of 5 eV is applied at the gate, common for n+-doped Si channel junctionless architectures [7,27,28].Ni or CrAu alloy is suitable for this work function value, common for junctionless n-TFTs.

Gate Dielectrics
Six base dielectric materials, SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2, bulk dielectric constants of which are shown in Table 2, are selected as single-layer gate dielectrics of a 3 nm thickness (tox) for a 14 nm channel length (LFET) gκ-FinFET structure.These six materials are used one-by-one for first six simulations to form the control group.
Then 15 different two-stage and 20 different three-stage κ-graded material combinations composed of these six base dielectrics, as designated in Table 3, are devised between the Si channel and the gate.The AHT case consists of Al2O3: HfO2: TiO2 gate oxides, as shown in Figure 1.

Dielectric Material
         2, are selected as single-layer gate dielectrics of a 3 nm thickness (t ox ) for a 14 nm channel length (L FET ) gκ-FinFET structure.These six materials are used one-by-one for first six simulations to form the control group.
Then 15 different two-stage and 20 different three-stage κ-graded material combinations composed of these six base dielectrics, as designated in Table 3, are devised between the Si channel and the gate.The AHT case consists of Al 2 O 3 : HfO 2 : TiO 2 gate oxides, as shown in Figure 1.

HLT
In Table 3, we introduce reference designators in the last column for gκ-FinFET equipped with each gate oxide material for the easy reading of the figures incorporated in the results.The designator consists of two to four alphanumeric characters, including the first character of each gate oxide it consists of.Since SiO 2 and Si 3 N 4 have the same first character, gκ-FinFETs with their respective gate oxides were designated as S1 and S2, respectively.All the parameters for gκ-FinFET were kept the same at each simulation, only the gate oxide layer material combination was changed, making a total of 41 simulations.The performances of the FinFETs with these gate oxide combinations, will be shown in subsequent pages and can be followed with these designations which appear in boldface throughout the paper and the individual stage thicknesses read from Table 4.For example, FinFET with a gate oxide of a single layer of SiO 2 is designated as S1, the same with a single layer of Si 3 N 4 as S2; for the Al 2 O 3 : TiO 2 gate oxide combination, the FinFET is designated as AT, and for a Si 3 N 4 : La 2 O 3 : TiO 2 combination, the same is designated as S2LT.

Methods
Our methods, mathematical derivations and modeling, choice of performance metrics, and usage of these figures of merit (FoM) for evaluation are presented herein with following main steps: κ-grading and calculation of effective κ of the gate oxide.Mathematical modeling in ATLAS Software v5.34.0.R. Choice of performance metrics for performance evaluation.

κ-Grading
Regarding κ-grading, we mean that, among selected dielectric materials to be used for stacking, Si channel deposition should be followed by dielectric material with lowest bulk dielectric constant κ b , followed by material with higher κ b , then followed by a material with higher κ b again, until gate is reached like in Figure 2. We mainly target dielectric permittivity matching of gate oxide at both ends of Si channel side and metal side.Thus, as permittivity matching at both ends of the gate oxide is considered, we implement this concept herein by κ-grading, keeping permittivity of neighboring materials as close as possible.
metrics, and usage of these figures of merit (FoM) for evaluation are presented herein with following main steps: Choice of performance metrics for performance evaluation.

κ-Grading
Regarding κ-grading, we mean that, among selected dielectric materials to be used for stacking, Si channel deposition should be followed by dielectric material with lowest bulk dielectric constant κ , followed by material with higher κ , then followed by a material with higher κ again, until gate is reached like in Figure 2. We mainly target dielectric permittivity matching of gate oxide at both ends of Si channel side and metal side.Thus, as permittivity matching at both ends of the gate oxide is considered, we implement this concept herein by κ-grading, keeping permittivity of neighboring materials as close as possible.are calculated dielectric constants of their respective nanolaminates with  , the volumetric filling factor for material A, and 1 −  is the volumetric filling factor for material B, in a two-phase dielectric system of Figure 3. Suppose κ bA , κ bB are bulk dielectric constants for materials A and B and κ A , κ B are calculated dielectric constants of their respective nanolaminates with f , the volumetric filling factor for material A, and 1 − f is the volumetric filling factor for material B, in a two-phase dielectric system of Figure 3.A theoretical foundation was first given by Penn's 1962 paper [50].For Si, it has been shown that for thicknesses greater than 200 Å (20 nm), bulk  can be considered to be unchanged and equivalent to  , and if  is less than 200 Å, one needs to consider using the wave number dependence equation for changing dielectric function.For practical purposes, this equation evolved into a modified model [54] by Tsu in 1997, and then into a generalized one [51] by Sharma in 2006, for calculation of size-dependent energy gap and dielectric permittivity of nanolaminated dielectric structures under quantum confinement effects, where  becomes less than  .A patent by Gealy [23] in 2012 incorporated similar equations to calculate the dielectric constant of thin nanolaminate, as stated in Equation (1).Our FinFET under consideration requires 1 nm, 1.5 nm, and 3 nm gate oxide nanolaminates; we chose to use Sharma's generalized Penn model.Calculation of effective κ, hereinafter κ , of this dielectric system in case of any narrowed individual thickness  or  below 200 Å is presented in two steps: First, nanolaminate dielectric constant  due to thickness  of nanometer order is to be calculated by Equation ( 1): where κ is the bulk dielectric constant, κ is the high-frequency dielectric constant, A theoretical foundation was first given by Penn's 1962 paper [50].For Si, it has been shown that for thicknesses greater than 200 Å (20 nm), bulk κ bA can be considered to be unchanged and equivalent to κ A , and if t A is less than 200 Å, one needs to consider using the wave number dependence equation for changing dielectric function.For practical purposes, this equation evolved into a modified model [54] by Tsu in 1997, and then into a generalized one [51] by Sharma in 2006, for calculation of size-dependent energy gap and dielectric permittivity of nanolaminated dielectric structures under quantum confinement effects, where κ A becomes less than κ bA .A patent by Gealy [23] in 2012 incorporated similar equations to calculate the dielectric constant of thin nanolaminate, as stated in Equation (1).Our FinFET under consideration requires 1 nm, 1.5 nm, and 3 nm gate oxide nanolaminates; we chose to use Sharma's generalized Penn model.Calculation of effective κ, hereinafter κ EFF , of this dielectric system in case of any narrowed individual thickness t A or t B below 200 Å is presented in two steps: First, nanolaminate dielectric constant κ A due to thickness t A of nanometer order is to be calculated by Equation (1): where κ bA is the bulk dielectric constant, κ ∞A is the high-frequency dielectric constant, K f A is Fermi wave vector, and t A is the planar thickness of the nano-scaled dielectric material A. Equation ( 1) can be numerically generalized and further fitted to Equation (2) as in [51], forming the generalized Penn Model which we utilize for our calculations of κ A for desired thickness t A : When we calculate the resultant κ A of material due to its nanolaminate thickness t A , we observe significant loss in dielectric effect.This numerical approximation is depicted in Figure 4 for TiO 2 material, showing that in orders of few nanometers, κ A reduction is significant.At 3 nm thickness, κ A becomes 77, at 1.5 nm it is 52.6, and at 1 nm it is 35.8 when compared to its bulk value of 95.

Maxwell-Garnett Model: Calculation of κ for Whole Gate Oxide
Dielectric constant  of system of nanolaminates due to thickness  =  +  and with volumetric filling factor is calculated by Maxwell-Garnett mixing formula.
Niklasson et.al.[55] used, in 1981, the Maxwell-Garnett and Bruggeman effective medium theories to derive average dielectric permeability of heterogeneous materials and estimated dielectric properties of a composite material composed of Cobalt and Alumina.Petrovsky [56] laid foundations of multi-material "effective dielectric constant" calculation with profound detail in 2012 mainly by Bruggeman equations with respect to volumetric filling factor . Markel [52] in 2016 issued a framework tutorial, surveying existing methods and restating the Maxwell-Garnett mixing formula for calculation of  for two-stage dielectrics.This formula gives the effective permittivity in terms of the permittivity and volume fractions of the individual constituents of the complex medium and is shown in Equation (3).
To extend this formula for a three-phase system, we denote the dielectric constants of the three materials as  ,  , and  and their respective volumetric filling factors as

Maxwell-Garnett Model: Calculation of κ for Whole Gate Oxide
Dielectric constant κ EFF of system of nanolaminates due to thickness t ox = t A + t B and with volumetric filling factor is calculated by Maxwell-Garnett mixing formula.
Niklasson et al. [55] used, in 1981, the Maxwell-Garnett and Bruggeman effective medium theories to derive average dielectric permeability of heterogeneous materials and estimated dielectric properties of a composite material composed of Cobalt and Alumina.Petrovsky [56] laid foundations of multi-material "effective dielectric constant" calculation with profound detail in 2012 mainly by Bruggeman equations with respect to volumetric filling factor f .Markel [52] in 2016 issued a framework tutorial, surveying existing methods and restating the Maxwell-Garnett mixing formula for calculation of κ EFF for two-stage dielectrics.This formula gives the effective permittivity in terms of the permittivity and volume fractions of the individual constituents of the complex medium and is shown in Equation (3).
To extend this formula for a three-phase system, we denote the dielectric constants of the three materials as κ A , κ B , and κ C and their respective volumetric filling factors as f A , f B , and f C where f A + f B + f C = 1, and we need to simply derive the same equation that considers all three materials.Thus, we can now: i.
Calculate the effective dielectric constant κ AB for materials A and B using the Maxwell-Garnett mixing formula.ii.Consider κ AB as single-material AB's dielectric constant and apply the Maxwell-Garnett formula again, with input variables κ AB and κ C , to find the overall effective dielectric constant κ EFF , with f AB + f C = 1, where f AB = f A + f B , and finally, our equation becomes Equation ( 4) for a complex medium of three phases, A, B, and C.
Therefore, using Equations ( 3) and ( 4), we calculated the κ EFF of two-stage and threestage dielectric materials denoted in last column of Table 4.

Mathematical Models in ATLAS
This section lays out modeling methods we utilize in ATLAS, Non-Equilibrium Green's Function, Hot Electron/Hole Injection Model and Direct Quantum Tunneling Model, equations of which are employed within simulations.

Quantum Transport: Non-Equilibrium Green's Function (NEGF) Approach
This fully quantum method treats such effects as source-to-drain tunneling, ballistic transport, and quantum confinement on equal footing.This situation is common to double gate and trigate transistors, FinFETs, and nanowire FETs.
By specifying the NEGF_MS and SCHRODINGER options on the MODELS statement, we can launch a NEGF solver to model ballistic quantum transport in such devices as double gate or surround gate MOSFET.An effective-mass Hamiltonian H o of a two-dimensional device is given by: when discretized in real space using a finite volume method.A corresponding expression in cylindrical coordinates is: Rather than solving a 2D or 3D problem, which may take vast amounts of computational time, a Mode Space (MS) approach is used.A Schrodinger equation is first solved in each slice of the device to find eigenenergies and eigenfunctions.Then, a transport equation of electrons moving in the sub-bands is solved.As only a few lowest eigen sub-bands are occupied and the upper sub-bands can be safely neglected, the size of the problem is reduced.In the devices where the cross-section does not change, the sub-bands are not quantum-mechanically coupled to each other, and the transport equations become essentially 1D for each sub-band.Therefore, we can further divide the method into Coupled (CMS) or Uncoupled Mode Space (UMS) approaches.ATLAS tool automatically decides on the minimum number of sub-bands required and the method to be used.It is possible, however, to set the number of sub-bands by using the EIGEN parameter on the MOD-ELS statement.To enforce either CMS or UMS approaches, we can use NEGF_CMS or NEGF_UMS instead of NEGF_MS on the MODELS statement.The transformation of a real space Hamiltonian H o to a mode space is done by taking a matrix element between m th and n th wave functions of k th and l th slices: Skipping some middle steps of derivation from [57], 2-dimensional carrier density and corresponding current density functions are laid as follows: Carrier density function: x-component of current density: y-component of current density: Total current density: Here, G < is the Green's function as a matrix, whose diagonal elements are carrier densities as function of energy.t ijkl is an off-diagonal element of real space Hamiltonian H o , which couples nodes (x i ,y k ) and (x j ,y l ).In our overall model, this current density J is to be integrated through the model geometry to yield the total current that will add up with the currents calculated by other models stated in next two sections.

Lucky-Electron Hot Carrier Injection Model
The Lucky-Electron Model (LEM), proposed in 1984 by Tam, Ko, and Hu, focuses on channel hot-electron injection in MOSFETs [58].This model was later challenged by the Energy-Driven Model (EDM) introduced in 2005, which emphasized the role of available energy over peak lateral electric field in predicting hot carrier effects in MOS devices.Furthermore, recent research has concentrated on electron-electron scattering-induced channel hot-electron injection in nanoscale n-MOSFETs with high-κ/metal gate stacks, highlighting the significance of trapping mechanisms in high-κ dielectric devices.Additionally, investigations on partially depleted SOI NMOSFETs revealed the impact of hot-electron injection on the back-gate threshold voltage and interface trap density, influencing the device's direct-current characteristics and radiation hardness performance [59].
In the Lucky-Electron Hot Carrier Injection Model, it is proposed that an electron is emitted into the oxide by first gaining enough energy from the electric field in the channel to surmount the insulator/semiconductor barrier.Once the required energy to surmount the barrier has been obtained, the electrons are redirected towards the insulator/semiconductor interface by some form of phonon scattering.When these conditions are met, the carrier travelling towards the interface will then have an additional probability that it will not suffer any additional collision through which energy could be lost.
The model implemented into ATLAS is a modified version of the model proposed by Tam [58] and is activated by the parameters of HEI and HHI, for electron and hole injection, respectively, on the MODELS statement.The gate electrode-insulator interface is subdivided into several discrete segments which are defined by the mesh.For each segment, the lucky electron model is used to calculate the injected current into that segment.The total gate current is then the sum of all the discrete values.
If we consider a discrete point on the gate's electrode-insulator boundary, we can write a mathematical formula for the current injected from the semiconductor.The formula calculates the injected gate current contribution from every node point within the semiconductor according to the injection current formula, stated as 2-dimensional integral of probability of hot electrons and holes, convolved with electron and current densities: → J n (x, y) dxdy + P P (x, y) → J P (x, y) dxdy (12)

Direct Quantum Tunneling Model
For deep submicron devices, the thickness of the insulating layers can be very small.For example, gate oxide thicknesses in MOS devices can be as low as several nanometers.In this case, the main assumptions of the Fowler-Nordheim approximation [60] are generally invalid and we need a more accurate expression for tunneling current.ATLAS used is based on a formula, which was introduced by Price and Radcliffe [61] and developed by later authors.It formulates the Schrödinger equation in the effective mass approximation and solves it to calculate the transmission probability, T(E), of an electron or hole through the potential barrier formed by the oxide layer.The incident (perpendicular) energy of the charge carrier, E, is a parameter.It is assumed that the tunneling process is elastic.After considering carrier statistics and integrating over lateral energy, the formula is obtained, which gives the current density J (A/m 2 ) though the barrier.The effective masses m y and m z are the effective masses in the lateral direction in the semiconductor.For example, for a direct bandgap material, where the Γ valley is isotropic, both m y and m z are the same as the density of states' effective mass.The logarithmic term includes the carrier statistics and E Fl and E Fr are the quasi-Fermi levels on either side of the barrier.The range of integration is determined according to the band edge shape at any given contact bias [17].

Employing the Computational Models in ATLAS
We model our gκ-FinFET using SILVACO ATLAS Deckbuild software tool.The family of such tools were used in vast amounts of research to design and simulate the MOSFET devices.ATLAS is actually a text-based language and takes an input file to be run to simulate the TFT devices.After building mesh and device geometry definitions, basic procedure for selecting mathematical models is adding the double line statement starting with keywords "MODELS" and "INTERFACE" to the ATLAS file, given in statement ( 14 By adding these within ATLAS file, researchers can employ direct quantum tunneling model (QTUNN.EL, QTUNN.HO) for both holes and electrons, hot-electron/hot-hole injection (HEI, HHI) model, non-equilibrium green function (NEGF_MS) model, and Schrodinger model [57] (SCHRODINGER), together with interface trap effect considerations simultaneously, to model complete current densities required for drain and gate leakage on any transistor with defined geometry, also defined in the ATLAS input (*.in) file.SP.FAST activates a fast product-space approach in a 2D Schrödinger solver.SP.GEOM = 2DYZ sets a dimensionality and direction of a Schrödinger solver.Value 2DYZ is default for mesh structure in ATLAS 3D.

Choice of Performance Metrics
Our performance metrics were selected, like in the paper by Nagy [31], for benchmarking of FinFETs, with DIBL added as the most researched short-channel effect, as follows: i.
I G , on-state gate leakage current, in Amperes, leaks from gate metal through dielectric into the channel, when V GS = 1 V.In our case, we favor to minimize.ii.I ON , on-state drain current, in Amperes, when V DS = V DD (= 1.25 V in our case) and V GS = V DD .We favor to maximize.iii.I OFF , off-state drain current, in Amperes, when V DS = V DD and V G = −1.5 V. We favor to minimize.iv.I ON /I OFF ratio, unitless, accepted and powerful measure of TFT design quality.We favor to maximize.v.
V TH , threshold voltage, in Volts, the minimum V GS voltage that drain current I D slightly exceeds a limit current (1 × 10 −7 A in our case) significant for the design.We favor to minimize.vi.SS, Subthreshold Slope, in mV/decade, change in the gate voltage required a decrease in the drain current I D by one decade, SS = ∆V GS /∆log (I D ).We favor to minimize.vii.DIBL, Drain-Induced Barrier Lowering, in mV/V, represents the drain voltage V DS influence on the threshold voltage V TH , defined as DIBL = |∆V TH |/|∆V DS |.We favor to minimize.
as these are the primary FoMs for evaluation of thin film transistors' performance, as also restated by Nowbahari [62] in his comprehensive review on junctionless transistors.

Results
We herein exhibit the performance of simulations carried out in ATLAS with the model given in Figure 1, of gκ-FinFET with gate oxide combinations tabulated in Table 4, in Figures 5-13 and Tables 5-12.

Drain Current Performance
First, our drain current modeling is verified by the results given in papers with FinFET fabrication examples [12,13,31,63].Figure 5 shows the drain current I D for all of single, twostage and three-stage graded gate oxides for the gκ-FinFET device we examined, depicting the single and compounded performances of the SiO 2 , Si 3 N 4 , Al 2 O 3 , HfO 2 , La 2 O 3 , and TiO 2 gate dielectrics.S1AL (SiO 2 : A 2 O 3 : La 2 O 3 ) has the highest I ON with 20.8 µA at (V G = 1.25 V) performance.AT (Al 2 O 3 : TiO 2 combination) has the lowest I OFF current of 6.45 × 10 −15 A. The I OFF current significantly changed with the changing dielectric combination; it varied between 4.73 × 10 −11 A and 6.45 × 10 −15 A, more than four orders of magnitude, just because of modifying the gate oxide layer.
If a single layer was used, this range would be in between 2.14 × 10 −12 A (for SiO 2 ) and 8.18 × 10 −14 A (for HfO 2 ).The I ON current would not be varying a great deal with changing gate oxides.However, gκ-FinFET S2T (Si 3 N 4 : TiO 2 gate oxide) has the highest I ON current of 2.08 × 10 −5 A, better than any other single gate oxides including FinFET H.For I ON /I OFF , S2T also performed the best at 2.4 × 10 9 , one order higher than that of FinFET H.
As depicted in Figure 9, the best I OFF performance gate oxides are AT, S2T, AHT, S2LT, and ALT, and from Figure 10, the best I ON performance gate oxides are S1AL, S1S2A, S1L, S1S2H, S1AH, and S1H.We can observe that no single-material gate oxide has performed better than the two-stage or three-stage gate oxides in the drain current performances.

Leakage Current Performance
First, we observed that our gate leakage current model is verified as Rudenko [64], Garduno [32], Khan [65], and Golosov [66] have similar trends for IG: starting from a negative VG, IG first decreases significantly around 6-14 orders of magnitude, depending on the gate oxide, takes a minimum at some VG value, and then it increases steeply again.
Figure 6 shows the IG leakage current characteristics [57] for the traditional singlematerial gate dielectrics together with the two-stage and three-stage -graded dielectrics, with the lowest gate leakage current of 2.04 × 10 −11 A (20.4 pA) at VG = 1.0 V for our specific FinFET under study.The leakage current curves generally show a similar trend and all tend to make local minimums at VG = 1 V, with the exception of that of TiO2 which has a local minimum around VG = 0.75 V and a leakage current of 4.0 × 10 −12 A (4 fA).Despite this low leakage current, TiO2 does not behave well, especially regarding its DIBL, ION, IOFF, and ION/IOFF performance; thus, the sole usage of TiO2 as a gate dielectric cannot be advised.

Leakage Current Performance
First, we observed that our gate leakage current model is verified as Rudenko [64], Garduno [32], Khan [65], and Golosov [66] have similar trends for I G : starting from a negative V G , I G first decreases significantly around 6-14 orders of magnitude, depending on the gate oxide, takes a minimum at some V G value, and then it increases steeply again.
Figure 6 shows the I G leakage current characteristics [57] for the traditional singlematerial gate dielectrics together with the two-stage and three-stage κ-graded dielectrics, with the lowest gate leakage current of 2.04 × 10 −11 A (20.4 pA) at V G = 1.0 V for our specific FinFET under study.The leakage current curves generally show a similar trend and all tend to make local minimums at V G = 1 V, with the exception of that of TiO 2 which has a local minimum around V G = 0.75 V and a leakage current of 4.0 × 10 −12 A (4 fA).Despite this low leakage current, TiO 2 does not behave well, especially regarding its DIBL, I ON , I OFF, and I ON /I OFF performance; thus, the sole usage of TiO 2 as a gate dielectric cannot be advised.The DIBL plot suggests that as the effective dielectric constant increases, the DIBL effect decreases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 35, and then increases back until κ EFF ≈ 77, point T (designates FinFET with TiO 2 as gate oxide).The DIBL performance of S2T with 41.9 mV/V is 37.4% lower than that of H. S2T, S2LT, AHT, AT, and S2HT, which are the five best-performing gκ-FinFETs in DIBL performance.5 for concise results.Figure 8 presents the Subthreshold Slope (SS) of gκ-FinFETs against their effective dielectric constants of gate oxides within.A lower SS means less change in the gate voltage is required to increase the drain current by a factor of ten.This is generally desirable as it indicates that the transistor can switch states more quickly and with less power consumption.Essentially, a lower subthreshold slope results in more efficient transistors that can operate effectively at lower voltages, which is especially beneficial in low-power and high-speed applications.

DIBL, SS, ION, IOFF, ION/IOFF, and VTH Performance
The SS plot suggests that as the effective dielectric constant increases, the SS effect decreases steeply and significantly from  ≈ 3.35 until  ≈ 25, just like DIBL's regime, then increases almost linearly back until  ≈ 77, point T (designates gκ-FinFET with TiO2 as the gate oxide).AHT, S1HT, HT, S2HT, ALT, HLT, and HT are the bestperforming FinFETs in SS performance.The SS performance of AHT with 152.0 mV/dec is 10.5% lower than that of H.  5 for concise results.Figure 8 presents the Subthreshold Slope (SS) of gκ-FinFETs against their effective dielectric constants of gate oxides within.A lower SS means less change in the gate voltage is required to increase the drain current by a factor of ten.This is generally desirable as it indicates that the transistor can switch states more quickly and with less power consumption.Essentially, a lower subthreshold slope results in more efficient transistors that can operate effectively at lower voltages, which is especially beneficial in low-power and high-speed applications.
The SS plot suggests that as the effective dielectric constant increases, the SS effect decreases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 25, just like DIBL's regime, then increases almost linearly back until κ EFF ≈ 77, point T (designates gκ-FinFET with TiO 2 as the gate oxide).AHT, S1HT, HT, S2HT, ALT, HLT, and HT are the best-performing FinFETs in SS performance.The SS performance of AHT with 152.0 mV/dec is 10.5% lower than that of H.  6 for concise results.Figure 9 plots the IOFF of gκ-FinFETs against the effective dielectric constant of gate oxides within.One of the primary advantages of a lower IOFF is the decrease in power consumption, especially important in battery-powered devices like smartphones and laptops.When transistors leak less current in their off state, the overall power efficiency of the device improves, leading to a longer battery life and less heat generation.Also, with lower IOFF values, it is possible to pack more transistors into a given area without significant overheating or power drain issues.This is critical for the ongoing trend of miniaturization in semiconductor technology.
The IOFF plot suggests that as the effective dielectric constant increases, the IOFF effect decreases steeply and significantly from  ≈ 3.35 until  ≈ 26 (that of AT), and then increases again until  ≈ 77.AT, S2T, AHT, S2LT, ALT, and S2HT are the bestperforming gκ-FinFETs in IOFF performance.The IOFF performance of AT with 6.45 × 10 −15 A is 92% lower than that of H.  6 for concise results.Figure 9 plots the I OFF of gκ-FinFETs against the effective dielectric constant of gate oxides within.One of the primary advantages of a lower I OFF is the decrease in power consumption, especially important in battery-powered devices like smartphones and laptops.When transistors leak less current in their off state, the overall power efficiency of the device improves, leading to a longer battery life and less heat generation.Also, with lower I OFF values, it is possible to pack more transistors into a given area without significant overheating or power drain issues.This is critical for the ongoing trend of miniaturization in semiconductor technology.
The I OFF plot suggests that as the effective dielectric constant increases, the I OFF effect decreases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 26 (that of AT), and then increases again until κ EFF ≈ 77.AT, S2T, AHT, S2LT, ALT, and S2HT are the best-performing gκ-FinFETs in I OFF performance.The I OFF performance of AT with 6.45 × 10 −15 A is 92% lower than that of H.  7 for concise results.Figure 10 plots the ION of gκ-FinFETs against their effective dielectric constants of gate oxides within.A higher ION implies that the transistor can deliver more current rapidly, which generally translates to faster switching speeds.With a higher ION, a transistor can drive larger currents through a circuit, which is essential for applications.The ION plot suggests that as the effective dielectric constant increases, the ION effect decreases steeply and significantly from  ≈ 3.35 until  ≈ 26 (that of AT), and then increases again until  ≈ 77, point T. S1AL, S1S2L, S1L, S1S2H, S1AH, and S1AH are the bestperforming gκ-FinFETs in ION performance.The ION performance of S1AL is 2.4 × 10 8 , which is 35% higher than that of H.  7 for concise results.Figure 10 plots the I ON of gκ-FinFETs against their effective dielectric constants of gate oxides within.A higher I ON implies that the transistor can deliver more current rapidly, which generally translates to faster switching speeds.With a higher I ON , a transistor can drive larger currents through a circuit, which is essential for applications.The I ON plot suggests that as the effective dielectric constant increases, the I ON effect decreases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 26 (that of AT), and then increases again until κ EFF ≈ 77, point T. S1AL, S1S2L, S1L, S1S2H, S1AH, and S1AH are the best-performing gκ-FinFETs in I ON performance.The I ON performance of S1AL is 2.4 × 10 8 , which is 35% higher than that of H.  8 for concise results.Figure 11 plots the IG of gκ-FinFETs against their effective dielectric constants of gate oxides within.The IG plot suggests that as the effective dielectric constant increases, the ION effect decreases steeply and significantly from  ≈ 3.35 until  ≈ 22 (that of S1T), and then increases again until  ≈ 77.A lower IG means the device has a better performance and less heating.A lower leakage current is preferable, especially for memory devices such as EEPROMs where a high IG can contribute to charge loss and memory degradation over time [67][68][69].With this fact in mind, AHL, S1, S2LT, AHT, S2HT, and S1S2H appear to be the best performers with respect to IG.Despite S1, all others are FinFETs with three-stage gate oxides, meaning -grading works properly in all cases.
We observe that no single-material gate oxide has performed better than the twostage or three-stage gate oxides in leakage current performances.We find that the use of κ-graded stacked gate oxide dielectrics has the potential to generate lower gate-to-channel  8 for concise results.Figure 11 plots the I G of gκ-FinFETs against their effective dielectric constants of gate oxides within.The I G plot suggests that as the effective dielectric constant increases, the I ON effect decreases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 22 (that of S1T), and then increases again until κ EFF ≈ 77.
A lower I G means the device has a better performance and less heating.A lower leakage current is preferable, especially for memory devices such as EEPROMs where a high I G can contribute to charge loss and memory degradation over time [67][68][69].With this fact in mind, AHL, S1, S2LT, AHT, S2HT, and S1S2H appear to be the best performers with respect to I G .Despite S1, all others are FinFETs with three-stage gate oxides, meaning κ-grading works properly in all cases.
We observe that no single-material gate oxide has performed better than the two-stage or three-stage gate oxides in leakage current performances.We find that the use of κ-graded stacked gate oxide dielectrics has the potential to generate lower gate-to-channel leakage currents, as stacked gate oxide AHL achieved a 76% lower I G than the FinFET with a single HfO 2 dielectric.
The performance of κ-graded gate oxides in terms of I G appears to be better than that of single-material dielectrics, suggesting that κ-grading in gate oxides may provide a significant advantage in reducing I G. Also, they do not tend to exhibit any deficiency in device reliability, within the scope of this study.
Micromachines 2024, 15, x FOR PEER REVIEW 20 of 27 leakage currents, as stacked gate oxide AHL achieved a 76% lower IG than the FinFET with a single HfO2 dielectric.The performance of κ-graded gate oxides in terms of IG appears to be better than that of single-material dielectrics, suggesting that κ-grading in gate oxides may provide a significant advantage in reducing IG.Also, they do not tend to exhibit any deficiency in device reliability, within the scope of this study.9 for concise results.Figure 12 plots the ION/IOFF of the gκ-FinFETs against their effective dielectric constants of gate oxides within.A higher ION/IOFF is mostly desirable in any transistor application and it indicates a distinct and clear differentiation between the "on" and "off" states of the transistor.With a higher ratio, the transistor leaks significantly less current in the "off" state compared to the current it conducts in the on state.As transistors are miniaturized further, maintaining a high ION/IOFF ratio becomes increasingly important to  9 for concise results.Figure 12 plots the I ON /I OFF of the gκ-FinFETs against their effective dielectric constants of gate oxides within.A higher I ON /I OFF is mostly desirable in any transistor application and it indicates a distinct and clear differentiation between the "on" and "off" states of the transistor.With a higher ratio, the transistor leaks significantly less current in the "off" state compared to the current it conducts in the on state.As transistors are miniaturized further, maintaining a high I ON /I OFF ratio becomes increasingly important to ensure that the devices operate reliably without interference from leakage currents.It enables the continued scaling down of semiconductor devices following Moore's Law, without performance degradation.
Our I ON /I OFF plot suggests that as the effective dielectric constant increases, the I OFF effect increases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 24.26 (point S2T), and then decreases again until κ EFF ≈ 77.S2T, AHT, S2LT, AT, ALT, and S2HT are the best-performing gκ-FinFETs in I ON /I OFF performance.The I ON /I OFF performance of S2T is 2.4 × 10 9 , which is 11.73 times higher than that of FinFET H.We observe that no singlematerial gate oxide has performed better than the two-stage or three-stage gate oxides in I ON /I OFF performance.
Micromachines 2024, 15, x FOR PEER REVIEW 21 of 27 ensure that the devices operate reliably without interference from leakage currents.It enables the continued scaling down of semiconductor devices following Moore's Law, without performance degradation.
Our ION/IOFF plot suggests that as the effective dielectric constant increases, the IOFF effect increases steeply and significantly from  ≈ 3.35 until  ≈ 24.26 (point S2T), and then decreases again until  ≈ 77.S2T, AHT, S2LT, AT, ALT, and S2HT are the best-performing gκ-FinFETs in ION/IOFF performance.The ION/IOFF performance of S2T is 2.4 × 10 9 , which is 11.73 times higher than that of FinFET H.We observe that no singlematerial gate oxide has performed better than the two-stage or three-stage gate oxides in ION/IOFF performance.10 for concise results.Figure 13 plots the V TH of the gκ-FinFETs against their effective dielectric constants of gate oxides within.Devices with a lower V TH can operate effectively at lower voltages.This is particularly advantageous in low-power applications such as mobile devices and wearable technology, where preserving battery life is crucial.A lower threshold voltage generally allows transistors to switch on and off more quickly.This can improve the overall speed of a processor and faster switching is beneficial for high-performance computing and digital circuits where rapid state changes are necessary.
The V TH plot suggests that as the effective dielectric constant increases, the V TH increases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 26 (that of AT), and then decreases until κ EFF ≈ 77.S2A, A, S2, S1AH, S1S2H, S1S2L, and S1AL are the best-performing gκ-FinFETs in the V TH performance.The V TH performance of S2A with 0.4731 V is 3.76% lower than that of A, 10.5% lower than that of S2, and 42% lower than that of H.This shows how graded oxide is better than any other single dielectric, including S2 and A individually, as shown in Table 6.
Micromachines 2024, 15, x FOR PEER REVIEW 22 of 27 This is particularly advantageous in low-power applications such as mobile devices and wearable technology, where preserving battery life is crucial.A lower threshold voltage generally allows transistors to switch on and off more quickly.This can improve the overall speed of a processor and faster switching is beneficial for high-performance computing and digital circuits where rapid state changes are necessary.
The VTH plot suggests that as the effective dielectric constant increases, the VTH increases steeply and significantly from  ≈ 3.35 until  ≈ 26 (that of AT), and then decreases until  ≈ 77.S2A, A, S2, S1AH, S1S2H, S1S2L, and S1AL are the bestperforming gκ-FinFETs in the VTH performance.The VTH performance of S2A with 0.4731 V is 3.76% lower than that of A, 10.5% lower than that of S2, and 42% lower than that of H.This shows how graded oxide is better than any other single dielectric, including S2 and A individually, as shown in Table 6.11 for concise results.11 for concise results.

Discussion
As seen in Figure 10, the minimum I OFF happens in gκ-FinFETs AT, S2T, AHT, S2LT, ALT, and S2HT.We observe that they have TiO 2 in common.We may safely conclude that TiO 2 matched perfectly with the metal side, better than others, and Al 2 O 3 and Si 3 N 4 matched (not so perfectly, but better than SiO 2 , HfO 2 , and La 2 O 3 ) with the Si channel side when the FinFET was in depletion mode.
As seen in Figure 11, the maximum I ON happens in gκ-FinFETs S1AL, S1S2L, S1L, S1S2H, S1AH, and S1H, and they all have SiO 2 in common.We may also conclude that SiO 2 matched perfectly with the Si channel side, better than the others and, La 2 O 3 and HfO 2 matched (not so perfectly, but better than Si 3 N 4 , Al 2 O 3 , and TiO 2 ) with the metal side when the gκ-FinFET was in inversion mode.
All these observations and optimal values for all FoMs (Table 4) happen between κ EFF values of 4.95-24.87.Observing Figure 5 to 13, according to our findings, for the n+ Si family gκ-FinFETs, seeking dielectrics of κ EFF higher than 25 might not be so efficient as favorable FoM values all appear in the mentioned range of κ EFF .
Therefore, it would be logical to infer, depending on the modes of the operation or the FoM we favor.In order to achieve this in a highly effective gate oxide layer, dielectric permittivity matching should be considered at both the neighboring Si channel side and neighboring gate metal side simultaneously.This is the reason why we actually employed κ-graded stacked gate oxides, as their least dielectric permittivity side would match that of the Si channel side and the highest dielectric permittivity side of the same would match that of metal side, yielding lesser interface problems to widen the limits for a better gate oxide and transistor performance, while we restate the facts presented in the works of Giustino,Peng,.We added below our insights which may lead to brief rules for designs in the future.

Analysis and Insights
Scanning throughout the 41 simulation results, we freely present our insights as follows:

•
No obvious linear or quadratic relationship exists between composite gate oxide κ EFF and any of the FoMs examined; thus, a curve fitting was not possible.• According to Table 7, the best I OFF performances have a TiO 2 laminate in common, as the last stage of the κ-graded structure.To minimize the I OFF , the dielectric permittivity of the gate metal and the neighboring gate oxide laminate should be kept as close as possible.• According to Table 12, the best DIBL performance appeared in the S2T (Si 3 N 4 : TiO 2 ) gate oxide combination.To minimize the DIBL and maximize the I ON /I OFF , both the permittivity difference of the channel material and the neighboring gate oxide laminate, as well as the permittivity difference of the gate material and the neighboring gate oxide laminate should be kept small.In this case, the S2T gate oxide dielectric showed the perfect permittivity-matching behavior in between the neighboring Si and neighboring CrAu alloy.• According to Table 12, at least one two-stage or three-stage κ-graded dielectric combi- nation exists which will behave much better than all of the single-stage counterparts with respect to all our FoMs.

Fabrication Considerations
The deposition processes of the mentioned graded dielectric stack shown in Figure 1 should be achieved using the Atomic Layer Deposition (ALD) method so that thin films of the dielectric stack are obtained in an ALD reactor.ALD, a very slow process, will provide the deposition of thin film oxides with the thickness in order of a few angstroms, excellently uniform, accurate, and a pin-hole free [70,71].Finally, the metal layer should be deposited by using magnetron sputtering or thermal evaporation onto the gate oxide layer [72].

Conclusions
We showed by simulations that it is possible that κ-graded stacked gate oxides could increase I ON and reduce I OFF and I G currents, DIBL, SS, and V TH .A numerical analysis was conducted to show the viability of the usage of κ-graded dielectric structures against conventional single-layer high-κ dielectrics on a 14 nm FinFET geometry.The impact on the key electrical performance parameters is analyzed using SILVACO ATLAS as the device simulation tool.Within 41 different two-and three-stage κ-graded stacked gate oxide combinations, some FinFET structures with κ-graded gate oxides (gκ-FinFET) promise a lower gate leakage current I G of up to 76%, lower drain-induced barrier lowering (DIBL) of up to 37.4%, a lower subthreshold slope (SS) of up to 10.5%, a lower drain-off current, I OFF , of up to 92%, a higher drain-on current, I ON , of up to 35%, a higher I ON /I OFF ratio of up to 11.7 times, and a lower threshold voltage, V TH , of up to 42%, with respect to the FinFET of the same dimensions with a single-layer HfO 2 gate dielectric.It became apparent that adverse interface effects will be minimized when smoother dielectric permittivity transitions are achieved by nanofabrication from the FinFET's channel, up to its gate metal.
o κ-grading and calculation of effective κ of the gate oxide.o Mathematical modeling in ATLAS Software v5.34.0.R. o

Figure 3 .
Figure 3. Two-phase dielectric system connected in series in parallel sheets.

Figure 3 .
Figure 3. Two-phase dielectric system connected in series in parallel sheets.

Figure 5 .
Figure 5. (a) Drain Current I D for gκ-FinFETs with single, two-stage, and three-stage κ-graded gate oxides, (b) I OFF zoomed for V G between −1.6 and −1.4 V, (c) I OFF further zoomed for V G between −1.6 and −1.4 V, best six gκ-FinFETs, (d) I ON zoomed for V G between 1.2 and 1.3 V. See Tables 7, 8 and 12 for summarized results of this figure.

Figure 6 .
Figure 6.(a) Leakage Current IG for gκ-FinFETs with single, two-stage, and three-stage κ-graded gate oxides, (b) IG zoomed for VG between 0.90 and 1.1 V. See Tables 9 and 12 for summarized results of this figure.

Figure 7 Figure 6 .
Figure 7 presents the Drain-Induced Barrier Lowering (DIBL) of FinFETs against their effective dielectric constants of gate oxides within.As DIBL is the short-channel effect where the drain voltage can influence the threshold voltage of the transistor, a lower DIBL value does generally better because it means the device has better control over the threshold voltage and is less susceptible to variations due to changes in the drain voltage.The DIBL plot suggests that as the effective dielectric constant increases, the DIBL effect decreases steeply and significantly from  ≈ 3.35 until  ≈ 35, and then increases back until  ≈ 77, point T (designates FinFET with TiO2 as gate oxide).The DIBL performance of S2T with 41.9 mV/V is 37.4% lower than that of H. S2T, S2LT, AHT, AT, and S2HT, which are the five best-performing gκ-FinFETs in DIBL performance.

4. 3 .
DIBL, SS, I ON , I OFF , I ON /I OFF, and V TH Performance

Figure 7
Figure 7 presents the Drain-Induced Barrier Lowering (DIBL) of FinFETs against their effective dielectric constants of gate oxides within.As DIBL is the short-channel effect where the drain voltage can influence the threshold voltage of the transistor, a lower DIBL value does generally better because it means the device has better control over the threshold voltage and is less susceptible to variations due to changes in the drain voltage.The DIBL plot suggests that as the effective dielectric constant increases, the DIBL effect decreases steeply and significantly from κ EFF ≈ 3.35 until κ EFF ≈ 35, and then increases back until κ EFF ≈ 77, point T (designates FinFET with TiO 2 as gate oxide).The DIBL performance of S2T with 41.9 mV/V is 37.4% lower than that of H. S2T, S2LT, AHT, AT, and S2HT, which are the five best-performing gκ-FinFETs in DIBL performance.

Table 3 .
gκ-FinFET reference designators for single and compound gate oxides of 41 simulations.

Table 4 .
Effective dielectric constants κ EFF of stacked nano-laminated gate oxides.

Table 7 .
Five best-performing gκ-FinFETs with lowest I OFF versus nearest-performing single dielectric FinFET H.

Table 9 .
Five best-performing gκ-FinFETs with lowest I G versus nearest-performing single dielectric FinFET H.

Table 10 .
Five best-performing gκ-FinFETs with lowest ION/IOFF versus nearest-performing single dielectric FinFET H.Figure 13plots the VTH of the gκ-FinFETs against their effective dielectric constants of gate oxides within.Devices with a lower VTH can operate effectively at lower voltages.

Table 10 .
Five best-performing gκ-FinFETs with lowest I ON /I OFF versus nearest-performing single dielectric FinFET H.

Table 11 .
Five best-performing gκ-FinFETs with lowest V TH versus nearest-performing single dielectric FinFET A.

Table 12 .
FoM champions of gκ-FinFETs with two-and three-stage graded gate oxides compared with FinFET with single-layer HfO 2 of t ox 3 nm.Boldface indicates best value among all 41 gκ-FinFET configurations.
• According to Table 8, the best I ON performances have a SiO 2 laminate in common as the first stage of the κ-graded structure.To maximize the I ON , the dielectric permittivity of channel material and neighboring gate oxide laminate should be kept as close as possible.• According to Table 11, the lowest values of V TH appeared in the lowest values of κ EFF .