Research on the Coupling Effect of NBTI and TID for FDSOI pMOSFETs

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.


Introduction
With the development of Moore's Law and the application of integrated circuits in the aerospace field, the non-ideal effects of devices in radiation environments are receiving increasing attention.The stability of bulk silicon technology is poor in radiation environments, and as the process size is scaled down, the short-channel effect of bulk silicon devices becomes increasingly significant [1].The fully depleted silicon on insulator (FD-SOI) technology, due to the presence of its buried oxygen (BOX) layer, has advantages in resisting single particle effect and transient dose rates, and to some extent improves the short-channel effect [2][3][4][5].However, as the process size continues to be scaled down, the gate dielectric layer of the MOS device becomes thinner and thinner, and the FDSOI device still faces reliability issues that exist in bulk silicon devices, including the NBTI effect [6,7]: when the MOS device is under high temperature and high gate voltage stress, the Si-H bonds at the Si/SiO 2 interface will be broken and form interface traps.For PMOS, the interface traps will capture holes and turn into positive interface trap charges, and the oxide trap charge is also generated during this process.In addition, although the gate dielectric layer has become thinner, the FDSOI device still suffers from the TID effect because of the BOX layer [8][9][10].The physical processes of the TID effect are as follows: Radiation causes the peripheral electrons to break free from the atom and become free electrons.When radiation acts on the oxide of the semiconductor device, it will cause the generation of electron-hole pairs.Part of the radiation-induced electron-hole pairs will recombine, and as for the rest of the electron-hole pairs, the electrons drift out of the oxide layer in a very short time under the applied electric field due to their higher mobility, while the holes migrate slowly to the Si/SiO 2 interface.During this process, part of the holes will be captured by traps, and thus, positive oxide trap charges and positive interface trap charges are formed.As the radiation dose continues to increase, the trap charge accumulates, and the degradation of the device becomes more severe; this phenomenon is known as the TID effect.It is worth noting that both the NBTI effect and the TID effect lead to the generation of oxide trap charge and interface trap charge, and the degradation of the device's electrical parameter caused by the NBTI effect and the TID effect are very similar.
The mechanisms of the TID effect and the NBTI effect for SOI devices have been systematically studied [11][12][13].However, the research on the degradation of SOI devices under the combined effect of TID and NBTI is relatively poor.The work of Wang et al. studied the threshold voltage degradation of a bulk silicon device under the combined effect of NBTI and TID [14] and found that the time exponent of the threshold voltage degradation curve of the irradiated device under NBT stress significantly increased compared to the unirradiated device, which means irradiation before NBT stress will accelerate the threshold voltage degradation of the device during NBT stress.Based on the PDSOI device, Peng et al. investigated the impact of BOX Si+ implantation TID hardening technology on the NBTI effect [15] and their work showed that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during NBT stress.The impact of the TID effect on the NBTI effect of the PDSOI device was investigated in a further paper by Peng et al. [16], and it was found that the irradiated device shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage, but the irradiation also increases the time exponent and leads to a significant reduction in the lifetime of the device.The influence of TID irradiation on the NBTI trap characteristics was also analyzed in this paper.Liu et al. investigated not only the impact of the TID effect on the NBTI effect but also the impact of the NBTI effect on the TID effect [17], and in addition to the degradation of the threshold voltage, the degradation of the transconductance and the subthreshold swing were also discussed.In the above works on the coupling effect of NBTI and TID, the method of studying the coupling effect of NBTI and TID is generally to apply NBT stress first and then irradiation, or to apply NBT stress after irradiation to study the degradation of the device after these two successive stresses.However, semiconductor devices used in space face a very harsh and complex operating environment, and in many cases, they are subjected to thermal stress, electrical stress, and radiation at the same time; accordingly, it is necessary to study the degradation of the device under the simultaneous stress of high temperature, high gate voltage, and radiation.
In this paper, the coupling effect of NBTI and TID on FDSOI PMOS is investigated by a simulation.In order to keep the research close to the actual working environment of the device, in addition to studying the influence of the NBTI effect on the TID effect by simulating the situation of irradiation after NBT stress, the situation of simultaneous NBT stress and irradiation on the FDSOI PMOS was also investigated.The threshold voltage shift of FDSOI PMOS under the above stress conditions was extracted and analyzed.The trap charge generation of FDSOI PMOS during stress was also discussed to further understand the coupling effect of NBTI and TID on FDSOI PMOS.For the FDSOI process, the thickness of the gate oxide layer was reduced to around 2 nm, and such a thin gate oxide layer weakens the impact of the gate oxide trap charge on the device, so the discussion of the trap charge in this paper focuses on the front-gate interface trap charge and oxide trap charge in the BOX layer.

Device Model and Electrical Parameter Extraction
The Simulation software used in this work is Sentaurus TCAD (Version: 2018.06).Figure 1 shows the device model of FDSOI PMOS, with a 7 nm top silicon film and a 25 nm BOX layer.The thickness of the gate oxide is 2 nm, and the doping information is listed in Table 1.
Micromachines 2024, 15, x FOR PEER REVIEW 3 of 1 nm BOX layer.The thickness of the gate oxide is 2 nm, and the doping information is listed in Table 1.The bias state of the device during the extraction of I-V characteristics is Vd = −0.9V and Vs = Vb = 0 V, and Vg was swept from 0 V to −0.9 V.The threshold voltage was ex tracted using the constant current method where the drain current reached (W/L) × 10 −7 A Figure 2 shows the simulated and measured [18] Id-Vg characteristics of the FDSOI PMOS device.The error between the simulated Id-Vg curve and the measured Id-Vg curve is very small, which demonstrates the accuracy of the device model.

Physical Model for Simulating NBTI Effect
The Trap Degradation Model (TDM) built in Sentaurus Tcad was used to simulate the NBTI effect.TDM is a simulation model for the NBTI effect developed based on the reaction-diffusion theory [19], which expresses the diffusion of H in the oxide laye through the following equations:  The bias state of the device during the extraction of I-V characteristics is Vd = −0.9V and Vs = Vb = 0 V, and Vg was swept from 0 V to −0.9 V.The threshold voltage was extracted using the constant current method where the drain current reached (W/L) × 10 −7 A. Figure 2 shows the simulated and measured [18] Id-Vg characteristics of the FDSOI PMOS device.The error between the simulated Id-Vg curve and the measured Id-Vg curve is very small, which demonstrates the accuracy of the device model.
nm BOX layer.The thickness of the gate oxide is 2 nm, and the doping information is listed in Table 1.The bias state of the device during the extraction of I-V characteristics is Vd = −0.9V and Vs = Vb = 0 V, and Vg was swept from 0 V to −0.9 V.The threshold voltage was ex tracted using the constant current method where the drain current reached (W/L) × 10 −7 A Figure 2 shows the simulated and measured [18] Id-Vg characteristics of the FDSOI PMOS device.The error between the simulated Id-Vg curve and the measured Id-Vg curve is very small, which demonstrates the accuracy of the device model.

Physical Model for Simulating NBTI Effect
The Trap Degradation Model (TDM) built in Sentaurus Tcad was used to simulate the NBTI effect.TDM is a simulation model for the NBTI effect developed based on the reaction-diffusion theory [19], which expresses the diffusion of H in the oxide laye through the following equations:

Physical Model for Simulating NBTI Effect
The Trap Degradation Model (TDM) built in Sentaurus Tcad was used to simulate the NBTI effect.TDM is a simulation model for the NBTI effect developed based on the reaction-diffusion theory [19], which expresses the diffusion of H in the oxide layer through the following equations: where N H is the concentration of hydrogen in the oxide layer, N hb is the concentration of unbroken Si-H bonds, D is the diffusion coefficient of hydrogen in the oxide layer, which can be expanded as D = D 0 exp(−ε H /kT), characterizing the effect of temperature and activation energy on the diffusion of hydrogen in the oxide layer, N 0 H is the initial concentration of hydrogen in the oxide layer, x = 0 represents the position of the interface between the channel and the oxide layer, and x = xp represents the position of the interface on the other side of the oxide layer (the value of xp should be set equal to the thickness of the oxide layer).k p is the surface recombination velocity at x = x p .
The interface trap density N it meets Equation ( 4), where N is the sum of the densities of all unbroken and broken Si-H bonds at the interface (N it = N − N hb ), N 0 hb is the density of the initial unbroken Si-H bonds, v is the de-passivation rate (the rate of Si-H bond breakage), γ is the passivation rate (the Si-bonds and hydrogen re-form into Si-H bonds), and v 0 and γ 0 are de-passivation and passivation constants, respectively.The physical meaning expressed by Equation ( 4) is straightforward, i.e., the rate of variation of the Si-H bond concentration is equal to the Si-H bonds regenerated due to passivation minus the Si-H bonds broken due to de-passivation.
It can be noted that the influence of stress conditions such as temperature and the electric field on the NBTI effect is not included directly in Equations ( 1)-( 4).This is because it is contained in the de-passivation rate v, which can be expanded as Equation ( 5): where ε 0 A is the activation energy of the Si-H bond breaking without stress, ∆ε A is the variation in the activation energy of the Si-H bond breaking due to the NBT stress, F ⊥ is the electric field perpendicular to the interface between the channel and the oxide layer, ∂ ⊥ , β ⊥ , β 0 , and ρ are the electric field enhancement parameters, k is the Boltzmann constant, and T represents the temperature in Kelvin.
The parameters of TDM were carefully calibrated to ensure the accuracy of the simulation, and Table 2 shows the parameter value of TDM after calibration.Figure 3 is a plot of the threshold voltage shift of the FDSOI PMOS versus NBT stress time obtained from measurements in the literature [18] and simulation with the calibrated TDM, which shows that the TDM can aptly simulate the NBTI effect, and the error between the threshold voltage shift obtained from the simulation and the actual measurement does not exceed 10%.

Physical Model for Simulating TID Effect
The TID effect was simulated by the Gamma Radiation Model (GRM), which is also a built-in model in Sentaurus TCAD.In GRM, the generation of electron-hole pairs due to radiation is an electric field-dependent process [20] and is modeled as follows: where  is the generation rate of electron-hole pairs during irradiation,  is the electron-hole pair generation constant,  is the dose rate, and () is used to model the influence of the electric field on the generation rate of electron-hole pairs during irradiation, which can be expanded as Equation (7): where  ,  , and  are constant parameters.

Physical Model for Simulating TID Effect
The TID effect was simulated by the Gamma Radiation Model (GRM), which is also a built-in model in Sentaurus TCAD.In GRM, the generation of electron-hole pairs due to radiation is an electric field-dependent process [20] and is modeled as follows: where G r is the generation rate of electron-hole pairs during irradiation, g 0 is the electronhole pair generation constant, D is the dose rate, and Y(F) is used to model the influence of the electric field on the generation rate of electron-hole pairs during irradiation, which can be expanded as Equation (7): where E 0 , E 1 , and m are constant parameters.
In addition to GRM, other settings are required to simulate the TID effect.In Sentaurus TCAD, it is assumed that electron-hole pairs will not appear in oxide; however, the degradation due to the TID effect is caused by the trapping of holes in the oxide layer.This problem can be solved by replacing the material of the oxide layers in the device model from SiO 2 to OxideAssemiconductor, which is a material defined by Sentaurus Tcad for such a situation.The capturing of holes by the oxide trap is also a physical process of TID degradation, while the capture rate of holes by the oxide trap is positively correlated with the capture cross-section.The capture cross-section can be expressed as follows [21]: where a 1 , a 2 , p 0 , p 1 , and p 2 are constant parameters and F is the electric field in the oxide layer.From Equation ( 8), it can be found that the capture cross-section is mainly affected by the electric field.
To ensure the accuracy of the simulation, the parameters of the physical model for simulating the TID effect also need to be calibrated, and Table 3 shows the parameter value of the physical model for simulating the TID effect after calibration.Figure 4 is a plot of the threshold voltage shift of the FDSOI PMOS versus irradiation dose obtained from measurements in the literature [22] and simulation with the calibrated model.There is no more than 15% error between the simulation and the measurements.

Parameters
Value Micromachines 2024, 15, x FOR PEER REVIEW 6 of 13 where  ,  ,  ,  , and  are constant parameters and  is the electric field in the oxide layer.From Equation ( 8), it can be found that the capture cross-section is mainly affected by the electric field.
To ensure the accuracy of the simulation, the parameters of the physical model for simulating the TID effect also need to be calibrated, and Table 3 shows the parameter value of the physical model for simulating the TID effect after calibration.Figure 4 is a plot of the threshold voltage shift of the FDSOI PMOS versus irradiation dose obtained from measurements in the literature [22] and simulation with the calibrated model.There is no more than 15% error between the simulation and the measurements.

Results and Discussion
In this section, the coupling effect of NBTI and TID was simulated based on the TDM and GRM.The threshold voltage shift of the devices was extracted from the simulation results, and the variation of trap charges of the devices was also extracted and analyzed.

NBTI after TID
Figure 5 shows the variation curves of the threshold voltage shift percentage during irradiation for the devices without and after 3000 s NBT stress, and the bias conditions of the devices during irradiation are listed in Table 4.The temperature and gate voltage of the NBT stress are 125 • C and −1.8 V, respectively.Figure 5 shows that for the devices under all three bias conditions of OFF, ON, and TG, the threshold voltage shift of the devices after NBT stress is less severe than that of the devices without NBT stress at any irradiation dose from 0 to 1 Mrad.This is because the recovery of the NBTI effect occurs at the same time as the irradiation.Figure 6 shows the variation of the trap charge in the front-gate interface during irradiation for the device after 3000 s NBT stress.As shown in Figure 6, a large amount of interface trap charge was formed at the front-gate interface of the device after 3000 s NBT stress.While subsequent irradiation is carried out under a low temperature and low gate voltage, the Si-H bonds that have been broken during previous NBT stress will be re-passivated and the interface trap charge will slowly decrease with time.The threshold voltage recovery due to the reduced interface trap charge compensates for part of the threshold voltage shift during irradiation.Therefore, the threshold voltage shift of the device after NBT stress is less severe than that of the device without NBT stress.under all three bias conditions of OFF, ON, and TG, the threshold voltage shift of the devices after NBT stress is less severe than that of the devices without NBT stress at any irradiation dose from 0 to 1 Mrad.This is because the recovery of the NBTI effect occurs at the same time as the irradiation.Figure 6 shows the variation of the trap charge in the front-gate interface during irradiation for the device after 3000 s NBT stress.As shown in Figure 6, a large amount of interface trap charge was formed at the front-gate interface of the device after 3000 s NBT stress.While subsequent irradiation is carried out under a low temperature and low gate voltage, the Si-H bonds that have been broken during previous NBT stress will be re-passivated and the interface trap charge will slowly decrease with time.The threshold voltage recovery due to the reduced interface trap charge compensates for part of the threshold voltage shift during irradiation.Therefore, the threshold voltage shift of the device after NBT stress is less severe than that of the device without NBT stress.

Bias State
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Simultaneous Effect of NBTI and TID
NBT stress refers to high temperature and high gate voltage stress, so the simultaneous effect of NBT stress and TID is to bias the device to the ON state with high gate voltage and to irradiate the device under high-temperature conditions.In this section, NBT stress is first decomposed into high gate voltage stress and high-temperature stress, and their effects on FDSOI PMOS in conjunction with irradiation are investigated separately.Finally, the simultaneous effect of high temperature, high gate voltage, and irradiation is investigated and the degradation of the devices under these cases is analyzed comparatively.
Figure 7 presents the threshold voltage degradation during stress for FDSOI PMOS devices under different gate voltages.It can be seen that the devices under high gate voltage exhibit more severe threshold voltage degradation during irradiation compared to devices under low gate voltage.Figure 8a,b shows the variation curves of the front-gate interface trap charge and the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different gate voltages, respectively.Figure 8 shows that after 300 Krad irradiation, the device under Vg = −1.8V has a significant increase in the frontgate interface trap charge compared to the device under Vg = −0.9V.Meanwhile, the oxide trap charge in the BOX layer of the device under Vg = −1.8V increases insignificantly compared to the device under Vg = −0.9V.The above analysis leads to the conclusion that high gate voltage has little impact on the oxide trap charge in the BOX layer generated during irradiation, and the front-gate interface trap charge induced by the high gate voltage contributes to severe threshold voltage degradation.

Simultaneous Effect of NBTI and TID
NBT stress refers to high temperature and high gate voltage stress, so the simultaneous effect of NBT stress and TID is to bias the device to the ON state with high gate voltage and to irradiate the device under high-temperature conditions.In this section, NBT stress is first decomposed into high gate voltage stress and high-temperature stress, and their effects on FDSOI PMOS in conjunction with irradiation are investigated separately.Finally, the simultaneous effect of high temperature, high gate voltage, and irradiation is investigated and the degradation of the devices under these cases is analyzed comparatively.
Figure 7 presents the threshold voltage degradation during stress for FDSOI PMOS devices under different gate voltages.It can be seen that the devices under high gate voltage exhibit more severe threshold voltage degradation during irradiation compared to devices under low gate voltage.Figure 8a,b shows the variation curves of the front-gate interface trap charge and the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different gate voltages, respectively.Figure 8 shows that after 300 Krad irradiation, the device under Vg = −1.8V has a significant increase in the front-gate interface trap charge compared to the device under Vg = −0.9V.Meanwhile, the oxide trap charge in the BOX layer of the device under Vg = −1.8V increases insignificantly compared to the device under Vg = −0.9V.The above analysis leads to the conclusion that high gate voltage has little impact on the oxide trap charge in the BOX layer generated during irradiation, and the front-gate interface trap charge induced by the high gate voltage contributes to severe threshold voltage degradation.
Figure 9 shows the lateral distribution of the carrier generation rate in the BOX layer of FDSOI PMOS devices under different gate voltages during irradiation.By analyzing Figures 8b and 9, it can be noticed that high gate voltage results in an increased carrier generation rate in the BOX layer during irradiation; however, the increase in the number of oxide trap charges in the BOX layer generated during irradiation is very slight.This phenomenon can be explained by Equation (8).In Equation ( 8), p 1 , p 2 are positive values and p 0 is a negative value.Thus, the higher the electric field strength, the smaller the trap's capture cross-section for holes, which means a lower trap capture rate for holes.On the one hand, high gate voltage results in an increased carrier generation rate in the BOX layer during irradiation, which increases the number of oxide trap charges in the BOX layer, but on the other hand, high gate voltage also results in a decreased capture rate of traps for holes, which decreases the number of oxide trap charges in the BOX layer.These two factors compete with each other, which leads to a very slight change in the number of oxide trap charges in the BOX layer.
FDSOI PMOS devices under different gate voltages, respectively.Figure 8 shows that after 300 Krad irradiation, the device under Vg = −1.8V has a significant increase in the frontgate interface trap charge compared to the device under Vg = −0.9V.Meanwhile, the oxide trap charge in the BOX layer of the device under Vg = −1.8V increases insignificantly compared to the device under Vg = −0.9V.The above analysis leads to the conclusion that high gate voltage has little impact on the oxide trap charge in the BOX layer generated during irradiation, and the front-gate interface trap charge induced by the high gate voltage contributes to severe threshold voltage degradation.Figure 9 shows the lateral distribution of the carrier generation rate in the BOX layer of FDSOI PMOS devices under different gate voltages during irradiation.By analyzing Figures 8b and 9, it can be noticed that high gate voltage results in an increased carrier generation rate in the BOX layer during irradiation; however, the increase in the number of oxide trap charges in the BOX layer generated during irradiation is very slight.This phenomenon can be explained by Equation (8).In Equation ( 8),  ,  are positive values and  is a negative value.Thus, the higher the electric field strength, the smaller the trap's capture cross-section for holes, which means a lower trap capture rate for holes.On the one hand, high gate voltage results in an increased carrier generation rate in the BOX layer during irradiation, which increases the number of oxide trap charges in the BOX layer, but on the other hand, high gate voltage also results in a decreased capture rate of traps for holes, which decreases the number of oxide trap charges in the BOX layer.These two factors compete with each other, which leads to a very slight change in the number of oxide trap charges in the BOX layer.Figure 9 shows the lateral distribution of the carrier generation rate in the BOX lay of FDSOI PMOS devices under different gate voltages during irradiation.By analyzi Figures 8b and 9, it can be noticed that high gate voltage results in an increased carr generation rate in the BOX layer during irradiation; however, the increase in the numb of oxide trap charges in the BOX layer generated during irradiation is very slight.Th phenomenon can be explained by Equation (8).In Equation ( 8),  ,  are positive valu and  is a negative value.Thus, the higher the electric field strength, the smaller t trap's capture cross-section for holes, which means a lower trap capture rate for holes.O the one hand, high gate voltage results in an increased carrier generation rate in the BO layer during irradiation, which increases the number of oxide trap charges in the BO layer, but on the other hand, high gate voltage also results in a decreased capture rate traps for holes, which decreases the number of oxide trap charges in the BOX layer.The two factors compete with each other, which leads to a very slight change in the numb of oxide trap charges in the BOX layer.Figure 11a,b, shows the variation curves of the front-gate interface trap charge an the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices unde different temperatures, respectively.The high temperature causes a significant increase i the oxide trap charge in the BOX layer generated during irradiation, which is due to th fact that high temperature leads to a high capture rate of traps to holes.Equation ( 9) is th capture rate ( ) of traps to holes in the oxide layer [21], which clearly demonstrates th positive correlation between the capture rate and the temperature.
where  is a constant between 0 and 1,  is the hole current density, and  is th thermal velocity, which in turn can be expanded as  =  /300.As for the fron gate interface trap charge, it can be derived from Figure 11a that the front-gate interfac trap charges generated under high-temperature irradiation also increased compared t those generated under low-temperature irradiation, which partly contributes to the highe threshold voltage shift of the device irradiated under high temperatures.
(a) (b)  Figure 11a,b, shows the variation curves of the front-gate interface trap charge and the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different temperatures, respectively.The high temperature causes a significant increase in the oxide trap charge in the BOX layer generated during irradiation, which is due to the fact that high temperature leads to a high capture rate of traps to holes.Equation ( 9) is the capture rate (c

√
T/300K.As for the front-gate interface trap charge, it can be derived from Figure 11a that the front-gate interface trap charges generated under high-temperature irradiation also increased compared to those generated under low-temperature irradiation, which partly contributes to the higher threshold voltage shift of the device irradiated under high temperatures.Figure 11a,b, shows the variation curves of the front-gate interface trap charge and the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different temperatures, respectively.The high temperature causes a significant increase in the oxide trap charge in the BOX layer generated during irradiation, which is due to the fact that high temperature leads to a high capture rate of traps to holes.Equation ( 9) is the capture rate ( ) of traps to holes in the oxide layer [21], which clearly demonstrates the positive correlation between the capture rate and the temperature.
where  is a constant between 0 and 1,  is the hole current density, and  is the thermal velocity, which in turn can be expanded as  =  /300.As for the frontgate interface trap charge, it can be derived from Figure 11a that the front-gate interface trap charges generated under high-temperature irradiation also increased compared to those generated under low-temperature irradiation, which partly contributes to the higher threshold voltage shift of the device irradiated under high temperatures.
(a) (b)   Figure 12 shows the threshold voltage degradation during stress for FDSOI PMOS devices under different temperatures and different gate voltages, from which it can be observed that among four combinations of different gate voltages and temperatures, the threshold voltage degradation of the device irradiated under a high temperature and high gate voltage is the most severe one.Figure 13a,b shows the variation curves of the front-gate interface trap charge and the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different stress conditions, respectively.According to Figure 13, under the combined effect of high temperature and high gate voltage, the impact of NBT stress is fully revealed; compared to other stress conditions, the generation of the front-gate interface trap charge increases extremely dramatically, and the oxide trap charge in the BOX layer also increases significantly.The threshold voltage shifts of the FDSOI PMOS irradiated under different stress conditions are displayed in Table 5.The high gate voltage increases the trap charge at the front-gate interface, the high temperature increases both the front-gate interface trap charge and the oxide trap charge in the BOX layer, and the irradiation under high temperature and high gate voltage achieved the effect of "one plus one over two", which makes the degradation of the threshold voltage far more severe.

Conclusions
In this paper, the threshold voltage degradation of FDSOI PMOS under the coupling effect of NBTI and TID is investigated by simulation.The results of the situation of irradiation after NBT stress show that after NBT stress, the threshold voltage degradation during irradiation is weakened, which is caused by the recovery of the NBTI effect.
Then, the situation of the NBT stress and irradiation applied simultaneously to the FDSOI PMOS was investigated.According to the simulation result, both high gate voltage and high temperature make the threshold voltage degradation of the device during irradiation more severe.The high gate voltage results in a significant increase in the front-gate interface trap charge generated during irradiation, while the more severe degradation of the device under high-temperature irradiation is mainly attributed to the significantly increased oxide trap charge in the BOX layer.Under the simultaneous influence of high temperature and high gate voltage, both the front-gate interface trap charge and the oxide trap charge in the BOX layer generated during irradiation increase dramatically, which makes the threshold voltage degradation of the FDSOI PMOS far more severe.

Figure 3 .
Figure 3. Threshold voltage shift of the FDSOI PMOS versus NBT stress time obtained from measurements in the literature and simulation.(a) Linear coordinate.(b) Double-logarithmic coordinate.

Figure 3 .
Figure 3. Threshold voltage shift of the FDSOI PMOS versus NBT stress time obtained from measurements in the literature and simulation.(a) Linear coordinate.(b) Double-logarithmic coordinate.

Figure 4 .
Figure 4. Threshold voltage shift of the FDSOI PMOS versus irradiation dose obtained from measurement in the literature and simulation.

Figure 4 .
Figure 4. Threshold voltage shift of the FDSOI PMOS versus irradiation dose obtained from measurement in the literature and simulation.

Figure 5 .
Figure 5. Threshold voltage shift percentage during irradiation for the devices without and after NBT stress; device is (a) OFF bias, (b) ON bias, and (c) TG bias during irradiation.

Figure 5 .
Figure 5. Threshold voltage shift percentage during irradiation for the devices without and after NBT stress; device is (a) OFF bias, (b) ON bias, and (c) TG bias during irradiation.

Figure 6 .
Figure 6.Variation of the front-gate interface trap charges during irradiation for device after NBT stress.

Figure 6 .
Figure 6.Variation of the front-gate interface trap charges during irradiation for device after NBT stress.

Figure 7 .
Figure 7. Threshold voltage degradation during stress for FDSOI PMOS devices under different gate voltages.

Figure 7 .Figure 8 .
Figure 7. Threshold voltage degradation during stress for FDSOI PMOS devices under different gate voltages.

Figure 8 .Figure 8 .
Figure 8. Variation of (a) front-gate interface trap charge and (b) oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different gate voltages.

Figure 9 .
Figure 9. Lateral distribution of carrier generation rate in the BOX layer of FDSOI PMOS devic under different gate voltages during irradiation.

Figure 10
Figure 10 shows the threshold voltage degradation during stress for FDSOI PMO devices under different temperatures.It shows that the threshold voltage shift is high for the device under 125 °C compared to devices under a low temperature.To understa this phenomenon, it is necessary to observe the trap charge of the device during irrad tion.

Figure 9 .
Figure 9. Lateral distribution of carrier generation rate in the BOX layer of FDSOI PMOS devices under different gate voltages during irradiation.

Figure 10 1 Figure 10 .
Figure 10 shows the threshold voltage degradation during stress for FDSOI PMOS devices under different temperatures.It shows that the threshold voltage shift is higher for

Figure 11 .
Figure 11.Variation of (a) the front-gate interface trap charge and (b) the oxide trap charge in th BOX layer versus stress time for FDSOI PMOS devices under different temperatures.

Figure 10 .
Figure 10.Threshold voltage degradation during stress for FDSOI PMOS devices under different temperatures.

pV
) of traps to holes in the oxide layer[21], which clearly demonstrates the positive correlation between the capture rate and the temperature.
constant between 0 and 1, J p is the hole current density, and v p th is the thermal velocity, which in turn can be expanded as v p th = v p 0

Figure 11 .
Figure 11.Variation of (a) the front-gate interface trap charge and (b) the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different temperatures.

Figure 12
Figure12shows the threshold voltage degradation during stress for FDSOI PMOS devices under different temperatures and different gate voltages, from which it can be observed that among four combinations of different gate voltages and temperatures, the threshold voltage degradation of the device irradiated under a high temperature and high

Figure 11 .
Figure 11.Variation of (a) the front-gate interface trap charge and (b) the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different temperatures.

Micromachines 2024 ,
15,  x FOR PEER REVIEW 11 of 13 gate voltage is the most severe one.Figure13a,b shows the variation curves of the frontgate interface trap charge and the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different stress conditions, respectively.According to Figure13, under the combined effect of high temperature and high gate voltage, the impact of NBT stress is fully revealed; compared to other stress conditions, the generation of the front-gate interface trap charge increases extremely dramatically, and the oxide trap charge in the BOX layer also increases significantly.The threshold voltage shifts of the FDSOI PMOS irradiated under different stress conditions are displayed in Table5.The high gate voltage increases the trap charge at the front-gate interface, the high temperature increases both the front-gate interface trap charge and the oxide trap charge in the BOX layer, and the irradiation under high temperature and high gate voltage achieved the effect of "one plus one over two ", which makes the degradation of the threshold voltage far more severe.

Figure 12 .Figure 13 .
Figure 12.Threshold voltage degradation during stress for FDSOI PMOS devices under different temperatures and different gate voltages.

Figure 12 .
Figure 12.Threshold voltage degradation during stress for FDSOI PMOS devices under different temperatures and different gate voltages.

Figure 12 .
Figure 12.Threshold voltage degradation during stress for FDSOI PMOS devices under different temperatures and different gate voltages.

Figure 13 .Table 5 .
Figure 13.Variation of (a) the front-gate interface trap charge and (b) the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different stress conditions.Table 5.The threshold voltage shift of the FDSOI PMOS irradiated under different stress conditions.Stress Condition ∆Vth Irradiation with Dose = 300 Krad, 11.47 mV

Figure 13 .
Figure 13.Variation of (a) the front-gate interface trap charge and (b) the oxide trap charge in the BOX layer versus stress time for FDSOI PMOS devices under different stress conditions.

Table 1 .
Doping information of the FDSOI PMOS device model.

Table 1 .
Doping information of the FDSOI PMOS device model.

Table 1 .
Doping information of the FDSOI PMOS device model.

Table 2 .
Calibrated parameters of TDM.

Table 4 .
Bias conditions for PMOS during irradiation.

Table 4 .
Bias conditions for PMOS during irradiation.

Table 5 .
The threshold voltage shift of the FDSOI PMOS irradiated under different stress conditions.

Table 5 .
The threshold voltage shift of the FDSOI PMOS irradiated under different stress conditions.