Design of Inner Matching Three-Stage High-Power Doherty Power Amplifier Based on GaN HEMT Model

This paper introduces the structure and characteristics of an internal-matching high-power Doherty power amplifier based on GaN HEMT devices with 0.25 μm process platforms from the Nanjing Electronic Devices Institute. Through parameter extraction and load-pull testing of the model transistor, an EE_HEMT model for the 1.2 mm gate-width GaN HEMT device was established. This model serves as the foundation for designing a high-power three-stage Doherty power amplifier. The amplifier achieved a saturated power gain exceeding 9 dB in continuous wave mode, with a saturated power output of 49.7 dBm. The drain efficiency was greater than 65% at 2.6 GHz. At 9 dB power back-off point, corresponding to an output power of 40.5 dBm, the drain efficiency remained above 55%. The performance of the amplifier remains consistent within the 2.55–2.62 GHz frequency range. The measured power, efficiency, and gain of the designed Doherty power amplifier align closely with the simulation results based on the EE_HEMT model, validating the accuracy of the established model. Furthermore, the in-band matching design reduces the size and weight of the amplifier. The amplifier maintains normal operation even after high and low-temperature testing, demonstrating its reliability. In conjunction with DPD (digital pre-distortion) for the modulated signal test, the amplifier exhibits extremely high linearity (ACLR < −50.93 dBc). This Doherty power amplifier holds potential applications in modern wireless communication scenarios.


Introduction
Fifth-generation communication technology (5G) adopts sophisticated modulation techniques such as QAM (quadrature amplitude modulation) and OFDM (orthogonal frequency division multiplexing), resulting in a high peak-to-average power ratio (PAPR) in its signal waveform [1,2].Doherty power amplifiers can maintain high efficiency both in saturation and power back-off, making them suitable for handling 5G communication signals [3].The schematic diagram of the traditional Doherty architecture is shown in Figure 1.The quarter-wavelength line after the auxiliary amplifier achieves load modulation performance through impedance transformation.The introduction of a 90-degree phase difference at the input ensures phase alignment between the two amplifiers.However, this architecture can only achieve a power back-off range of about 6 dB, which falls short of meeting the requirements for processing signals with high PAPR.
Asymmetric architectures, as illustrated in the literature [4][5][6][7][8][9][10][11][12][13][14], have improved the traditional Doherty power amplifier structure to enhance its power back-off range.The auxiliary amplifier, compared with the main amplifier, has a higher saturated output power, achieving a power back-off range of approximately 7-8 dB.Additionally, two three-stage Doherty structures, as shown in Figure 2a,b, can achieve power back-off ranges greater than 8 dB.The three-stage Doherty architecture in Figure 2a is an extension of the traditional Doherty structure.The carrier amplifier and the first peak amplifier together form a twostage Doherty power amplifier, which then combines with the second peak amplifier to form a new Doherty power amplifier.In 2011, NXP proposed an improved three-stage Doherty power amplifier structure [15], as shown in Figure 2b, which has been widely adopted, as documented in references [16][17][18][19][20]. Compared with the architecture shown in Figure 2a, this design effectively improves the gain compression of the main amplifier and further extends the power backoff range.The load modulation behavior of this architecture is analyzed later.
On the other hand, GaN HEMT (gallium nitride high-electron-mobility transistor) devices, due to their broad frequency response and high power density, are widely used in communication, radar, aerospace, and other fields [21][22][23][24][25].The accuracy of HEMT device models is crucial for MMIC (microwave monolithic integrated circuit) design success and performance.The EE_HEMT model proposed by Agilent Technologies in 1993 is a widely used nonlinear compact model for HEMT devices, providing accurate characterization of the RF properties of the device.Additionally, the EE_HEMT model is a compact model that maintains high accuracy even in scaled applications.In this paper, an EE_HEMT scalable model for a GaN HEMT device with small gate width was established through DC scanning testing, S-parameter testing, and extraction of intrinsic and parasitic parameters.The model was further validated through load-pull testing and simulation, confirming its accuracy in large-signal conditions.The results of testing on the actual circuit indicated close agreement between simulation and measurement, with simulation errors of less than 5% for drain efficiency and less than 1 dB for gain under large-signal excitation, validating the precision of the established EE_HEMT model.

Introduction of GaN HEMT Devices
This design utilizes a 7.2 mm gate-width GaN HEMT device developed by Nanjing Electronic Devices Institute.Under a bias condition with a drain-source voltage (VDS) of 28 V, the device can provide a continuous wave saturated output power density exceeding In 2011, NXP proposed an improved three-stage Doherty power amplifier structure [15], as shown in Figure 2b, which has been widely adopted, as documented in references [16][17][18][19][20]. Compared with the architecture shown in Figure 2a, this design effectively improves the gain compression of the main amplifier and further extends the power backoff range.The load modulation behavior of this architecture is analyzed later.
On the other hand, GaN HEMT (gallium nitride high-electron-mobility transistor) devices, due to their broad frequency response and high power density, are widely used in communication, radar, aerospace, and other fields [21][22][23][24][25].The accuracy of HEMT device models is crucial for MMIC (microwave monolithic integrated circuit) design success and performance.The EE_HEMT model proposed by Agilent Technologies in 1993 is a widely used nonlinear compact model for HEMT devices, providing accurate characterization of the RF properties of the device.Additionally, the EE_HEMT model is a compact model that maintains high accuracy even in scaled applications.In this paper, an EE_HEMT scalable model for a GaN HEMT device with small gate width was established through DC scanning testing, S-parameter testing, and extraction of intrinsic and parasitic parameters.The model was further validated through load-pull testing and simulation, confirming its accuracy in large-signal conditions.The results of testing on the actual circuit indicated close agreement between simulation and measurement, with simulation errors of less than 5% for drain efficiency and less than 1 dB for gain under large-signal excitation, validating the precision of the established EE_HEMT model.

Introduction of GaN HEMT Devices
This design utilizes a 7.2 mm gate-width GaN HEMT device developed by Nanjing Electronic Devices Institute.Under a bias condition with a drain-source voltage (VDS) of 28 V, the device can provide a continuous wave saturated output power density exceeding In 2011, NXP proposed an improved three-stage Doherty power amplifier structure [15], as shown in Figure 2b, which has been widely adopted, as documented in references [16][17][18][19][20]. Compared with the architecture shown in Figure 2a, this design effectively improves the gain compression of the main amplifier and further extends the power back-off range.The load modulation behavior of this architecture is analyzed later.
On the other hand, GaN HEMT (gallium nitride high-electron-mobility transistor) devices, due to their broad frequency response and high power density, are widely used in communication, radar, aerospace, and other fields [21][22][23][24][25].The accuracy of HEMT device models is crucial for MMIC (microwave monolithic integrated circuit) design success and performance.The EE_HEMT model proposed by Agilent Technologies in 1993 is a widely used nonlinear compact model for HEMT devices, providing accurate characterization of the RF properties of the device.Additionally, the EE_HEMT model is a compact model that maintains high accuracy even in scaled applications.In this paper, an EE_HEMT scalable model for a GaN HEMT device with small gate width was established through DC scanning testing, S-parameter testing, and extraction of intrinsic and parasitic parameters.The model was further validated through load-pull testing and simulation, confirming its accuracy in large-signal conditions.The results of testing on the actual circuit indicated close agreement between simulation and measurement, with simulation errors of less than 5% for drain efficiency and less than 1 dB for gain under large-signal excitation, validating the precision of the established EE_HEMT model.

Introduction of GaN HEMT Devices
This design utilizes a 7.2 mm gate-width GaN HEMT device developed by Nanjing Electronic Devices Institute.Under a bias condition with a drain-source voltage (V DS ) of 28 V, the device can provide a continuous wave saturated output power density exceeding 4.5 W/mm [26].Its longitudinal structure, as shown in Figure 3a, includes a SiC substrate, an undoped GaN buffer layer, an AlN insertion layer, and an AlGaN barrier layer.The SiC substrate serves the purposes of support, heat dissipation, and electromagnetic shielding.The AlN insertion layer enhances electron mobility to improve high-frequency characteristics and concurrently reduces scattering effects caused by lattice mismatch.The addition of a gate field plate helps lower the peak electric field, thereby increasing the breakdown voltage of the device.Simultaneously, to minimize thermal resistance and enhance reliability, the SiC substrate is thinned and gold-plated on the reverse, improving heat dissipation capabilities.In addition, the SiN passivation layer covering the entire device surface can effectively enhance the transistor's radiation resistance capability [27].The entire chip is grounded through vias to minimize parasitic capacitance and inductance, thereby enhancing the high-frequency characteristics of the device.Figure 3b shows a photograph of the GaN HEMT used in this design.The device has a single-finger gate width of 200 µm and a total gate width of 7.2 mm.The overall size of the entire chip is 2.62 mm × 0.93 mm.
4.5 W/mm [26].Its longitudinal structure, as shown in Figure 3a, includes a SiC substrate, an undoped GaN buffer layer, an AlN insertion layer, and an AlGaN barrier layer.The SiC substrate serves the purposes of support, heat dissipation, and electromagnetic shielding.The AlN insertion layer enhances electron mobility to improve high-frequency characteristics and concurrently reduces scattering effects caused by lattice mismatch.The addition of a gate field plate helps lower the peak electric field, thereby increasing the breakdown voltage of the device.Simultaneously, to minimize thermal resistance and enhance reliability, the SiC substrate is thinned and gold-plated on the reverse, improving heat dissipation capabilities.In addition, the SiN passivation layer covering the entire device surface can effectively enhance the transistor's radiation resistance capability [27].The entire chip is grounded through vias to minimize parasitic capacitance and inductance, thereby enhancing the high-frequency characteristics of the device.Figure 3b

Parameter Extraction and Model Establishment
The EE_HEMT model was established based on a 1.2 mm gate-width model transistor with the same process technology as the GaN HEMT in this design.It has a singlefinger gate width of 200 µm, with a total of 6 gate fingers, resulting in an overall gate width of 1.2 mm. Figure 4 shows a microscopic photograph of this model transistor.

Parameter Extraction and Model Establishment
The EE_HEMT model was established based on a 1.2 mm gate-width model transistor with the same process technology as the GaN HEMT in this design.It has a single-finger gate width of 200 µm, with a total of 6 gate fingers, resulting in an overall gate width of 1.2 mm. Figure 4 shows a microscopic photograph of this model transistor.
4.5 W/mm [26].Its longitudinal structure, as shown in Figure 3a, includes a SiC substrate, an undoped GaN buffer layer, an AlN insertion layer, and an AlGaN barrier layer.The SiC substrate serves the purposes of support, heat dissipation, and electromagnetic shielding.The AlN insertion layer enhances electron mobility to improve high-frequency characteristics and concurrently reduces scattering effects caused by lattice mismatch.The addition of a gate field plate helps lower the peak electric field, thereby increasing the breakdown voltage of the device.Simultaneously, to minimize thermal resistance and enhance reliability, the SiC substrate is thinned and gold-plated on the reverse, improving heat dissipation capabilities.In addition, the SiN passivation layer covering the entire device surface can effectively enhance the transistor's radiation resistance capability [27].The entire chip is grounded through vias to minimize parasitic capacitance and inductance, thereby enhancing the high-frequency characteristics of the device.Figure 3b

Parameter Extraction and Model Establishment
The EE_HEMT model was established based on a 1.2 mm gate-width model transistor with the same process technology as the GaN HEMT in this design.It has a singlefinger gate width of 200 µm, with a total of 6 gate fingers, resulting in an overall gate width of 1.2 mm. Figure 4 shows a microscopic photograph of this model transistor.Additionally, load-pull testing was conducted on the model transistor to obtain information such as maximum saturated output power and the highest PAE, to validate the accuracy of the model under large-signal conditions.Figures 6 and 7 represent the DC characteristics and S-parameter test results compared with the model simulation results.In Figure 6a,b, the DC simulation and test results for drain current and gate current are presented, respectively.Figure 7b,c show the magnitude and phase errors of the S-parameters within the frequency range of 0.4-35 GHz.The magnitude error is less than ±0.05, while the phase error is distributed within the frequency range of −5 degrees to +8 degrees.Figure 8 displays the test results for load-pull output power and PAE, along with the simulation results.The results indicate a close agreement between simulation data and measured data, confirming the accuracy of the model structure and parameters.Additionally, load-pull testing was conducted on the model transistor to obtain information such as maximum saturated output power and the highest PAE, to validate the accuracy of the model under large-signal conditions.Figures 6 and 7 represent the DC characteristics and S-parameter test results compared with the model simulation results.In Figure 6a,b, the DC simulation and test results for drain current and gate current are presented, respectively.Figure 7b,c show the magnitude and phase errors of the S-parameters within the frequency range of 0.4-35 GHz.The magnitude error is less than ±0.05, while the phase error is distributed within the frequency range of −5 degrees to +8 degrees.Figure 8 displays the test results for load-pull output power and PAE, along with the simulation results.The results indicate a close agreement between simulation data and measured data, confirming the accuracy of the model structure and parameters.
DC scanning testing and S-parameter scanning testing in the frequency range of 0.4 GHz to 35 GHz with a pulse period of 1 ms and a duty cycle of 10% were conducted to extract intrinsic and parasitic parameters of the model transistor described above.By fitting the intrinsic and parasitic parameters, an equivalent circuit for the large-signal EE_HEMT model, as depicted in Figure 5a   Additionally, load-pull testing was conducted on the model transistor to obtain information such as maximum saturated output power and the highest PAE, to validate the accuracy of the model under large-signal conditions.Figures 6 and 7 represent the DC characteristics and S-parameter test results compared with the model simulation results.In Figure 6a,b, the DC simulation and test results for drain current and gate current are presented, respectively.Figure 7b,c show the magnitude and phase errors of the S-parameters within the frequency range of 0.4-35 GHz.The magnitude error is less than ±0.05, while the phase error is distributed within the frequency range of −5 degrees to +8 degrees.Figure 8 displays the test results for load-pull output power and PAE, along with the simulation results.The results indicate a close agreement between simulation data and measured data, confirming the accuracy of the model structure and parameters.

Load Modulation Behavior Analysis of Three-Stage Doherty PA
The Doherty PA structure used in this study is shown in Figure 2b; it is assumed that it is composed of symmetric devices and all cells saturate simultaneously at maximum input power.The relationship between the output and back-off power for the three-stage Doherty PA is derived as follows: where

Load Modulation Behavior Analysis of Three-Stage Doherty PA
The Doherty PA structure used in this study is shown in Figure 2b; it is assumed that it is composed of symmetric devices and all cells saturate simultaneously at maximum input power.The relationship between the output and back-off power for the three-stage Doherty PA is derived as follows: where The Doherty PA structure used in this study is shown in Figure 2b; it is assumed that it is composed of symmetric devices and all cells saturate simultaneously at maximum input power.The relationship between the output and back-off power for the three-stage Doherty PA is derived as follows: where The back-off output power can be expressed in the following form: Combining the equations above, we can determine the values of k 1 and k 2 : Under different biases, the three-stage Doherty PA can have two or three maximum efficiency points.Figure 9 shows the structure of the power-combining network, and according to the principles of dynamic load modulation, the characteristic impedances of the three microstrip lines can all be calculated.
Micromachines 2024, 15, x FOR PEER REVIEW 6 of 15 The back-off output power can be expressed in the following form: Combining the equations above, we can determine the values of k1 and k2: Under different biases, the three-stage Doherty PA can have two or three maximum efficiency points.Figure 9 shows the structure of the power-combining network, and according to the principles of dynamic load modulation, the characteristic impedances of the three microstrip lines can all be calculated.The fundamental drain current ratio between the main amplifier and the peak amplifier can be defined as follows: Table 1 shows the variation in δ1 and δ2 as vin increases.Assuming the load impedance R0 is 50 Ω, and defining the characteristic impedances of each quarter-wavelength line as Z3, Z2, and Z1 for each section as αR0, βR0, and γR0, respectively, the load impedance for each amplifier can be derived as follows: Combining with Table 1, the load impedance for each amplifier can be derived as follows: The fundamental drain current ratio between the main amplifier and the peak amplifier can be defined as follows: Table 1 shows the variation in δ 1 and δ 2 as v in increases.
Table 1.The values of δ 1 and δ 2 as v in increases.
Assuming the load impedance R 0 is 50 Ω, and defining the characteristic impedances of each quarter-wavelength line as Z 3 , Z 2 , and Z 1 for each section as αR 0 , βR 0 , and γR 0 , respectively, the load impedance for each amplifier can be derived as follows: Combining with Table 1, the load impedance for each amplifier can be derived as follows: If each amplifier is matched to 50 Ω when v in /v max = 1, then according to the above equations, Z 1 , Z 2 , and Z 3 can be calculated as follows:

Circuit Design
Load-pull simulation was performed on the transistor with a gate width of 7.2 mm, and the results indicate maximum output power of 46.2 dBm and peak PAE of 75.4%.Striking a balance between power and efficiency, the chosen saturation output impedance of the chip is 5.2 + j × 5.5 Ω.At this point, the output power is 46 dBm, and the PAE is 69.4%, meeting the design requirements.
The output matching employs an L-C-L matching structure implemented through microstrip lines, effectively controlling the circuit's second harmonic.The second harmonic impedance is maximized to make the amplifier operate in class-F −1 mode, thereby enhancing the efficiency of the single amplifier.
The contour of S 11 in the intrinsic current source plane on the Smith chart is depicted in Figure 10a, and the contour of S 11 for output matching network is depicted on the Smith chart in Figure 10b.
If each amplifier is matched to 50 Ω when vin/vmax = 1, then according to the above equations, Z1, Z2, and Z3 can be calculated as follows:

Circuit Design
Load-pull simulation was performed on the transistor with a gate width of 7.2 mm, and the results indicate maximum output power of 46.2 dBm and peak PAE of 75.4%.Striking a balance between power and efficiency, the chosen saturation output impedance of the chip is 5.2 + j × 5.5 Ω.At this point, the output power is 46 dBm, and the PAE is 69.4%, meeting the design requirements.
The output matching employs an L-C-L matching structure implemented through microstrip lines, effectively controlling the circuit's second harmonic.The second harmonic impedance is maximized to make the amplifier operate in class-F −1 mode, thereby enhancing the efficiency of the single amplifier.
The contour of S11 in the intrinsic current source plane on the Smith chart is depicted in Figure 10a, and the contour of S11 for output matching network is depicted on the Smith chart in Figure 10b.Through source-pull simulation, input impedance of the transistor was determined to 0.3 − j × 2.2 Ω.The input matching network structure is similar to the output matching network structure, with a relatively simple design that can match input impedance to 50 Ω.Additionally, a parallel-connected capacitor-resistor stability circuit was added at the input of the transistor to ensure the stable operation of the amplifier.Figure 11 shows the schematic diagram of a single amplifier.
A frequency sweep large-signal simulation was performed on the designed single amplifier under bias conditions of V GS = 28 V and V DS = −2.1 V, with an input power of 34 dBm.The simulation results are presented in Figure 12. Figure 12a displays the large-signal simulation results of input and output return loss and Figure 12b displays the output power and PAE.The simulation results indicate that the saturated output power and PAE of the single amplifier were 45.9 dBm and 68.2%, respectively.These values closely align with the load-pull data, confirming the accuracy of the circuit design.Furthermore, due to the introduction of a grounded circuit, the simulation of the stability factor (K) for the single amplifier within the operating frequency band was consistently greater than 1.This indicates that the amplifier can operate stably within the frequency range, ensuring its stability.Through source-pull simulation, input impedance of the transistor was determined to 0.3 − j × 2.2 Ω.The input matching network structure is similar to the output matching network structure, with a relatively simple design that can match input impedance to 50 Ω.Additionally, a parallel-connected capacitor-resistor stability circuit was added at the input of the transistor to ensure the stable operation of the amplifier.Figure 11  A frequency sweep large-signal simulation was performed on the designed single amplifier under bias conditions of VGS = 28 V and VDS = −2.1 V, with an input power of 34 dBm.The simulation results are presented in Figure 12. Figure 12a displays the largesignal simulation results of input and output return loss and Figure 12b displays the output power and PAE.The simulation results indicate that the saturated output power and PAE of the single amplifier were 45.9 dBm and 68.2%, respectively.These values closely align with the load-pull data, confirming the accuracy of the circuit design.Furthermore, due to the introduction of a grounded circuit, the simulation of the stability factor (K) for the single amplifier within the operating frequency band was consistently greater than 1.This indicates that the amplifier can operate stably within the frequency range, ensuring its stability.In order to reduce the circuit size, the practical microstrip circuit was manufactured on an alumina ceramic substrate with a dielectric constant of 9.9 and thickness of 380 µm, as well as barium titanate ceramic substrates with dielectric constant of 85 and thickness of 180 µm.The microstrip circuit and the chip are sintered onto a molybdenum-copper alloy carrier, and they are interconnected through wire bonding.Additionally, 20 pF chip capacitors were added at the input and output positions of the amplifier to isolate the DC component.Furthermore, 1000 pF chip capacitors were also introduced to filter out high- A frequency sweep large-signal simulation was performed on the designed single amplifier under bias conditions of VGS = 28 V and VDS = −2.1 V, with an input power of 34 dBm.The simulation results are presented in Figure 12. Figure 12a displays the largesignal simulation results of input and output return loss and Figure 12b displays the output power and PAE.The simulation results indicate that the saturated output power and PAE of the single amplifier were 45.9 dBm and 68.2%, respectively.These values closely align with the load-pull data, confirming the accuracy of the circuit design.Furthermore, due to the introduction of a grounded circuit, the simulation of the stability factor (K) for the single amplifier within the operating frequency band was consistently greater than 1.This indicates that the amplifier can operate stably within the frequency range, ensuring its stability.In order to reduce the circuit size, the practical microstrip circuit was manufactured on an alumina ceramic substrate with a dielectric constant of 9.9 and thickness of 380 µm, as well as barium titanate ceramic substrates with dielectric constant of 85 and thickness of 180 µm.The microstrip circuit and the chip are sintered onto a molybdenum-copper alloy carrier, and they are interconnected through wire bonding.Additionally, 20 pF chip capacitors were added at the input and output positions of the amplifier to isolate the DC component.Furthermore, 1000 pF chip capacitors were also introduced to filter out high- In order to reduce the circuit size, the practical microstrip circuit was manufactured on an alumina ceramic substrate with a dielectric constant of 9.9 and thickness of 380 µm, as well as barium titanate ceramic substrates with dielectric constant of 85 and thickness of 180 µm.The microstrip circuit and the chip are sintered onto a molybdenum-copper alloy carrier, and they are interconnected through wire bonding.Additionally, 20 pF chip capacitors were added at the input and output positions of the amplifier to isolate the DC component.Furthermore, 1000 pF chip capacitors were also introduced to filter out highfrequency noise at the feeding point.The amplifier has dimensions of 19.2 mm × 10 mm and is securely fastened to the test fixture using screws.
The input power divider of the Doherty power amplifier adopts a three-way Wilkinson power divider structure with equal power splitting, and the impedance of each port of the power divider is 50 Ω.Additionally, to maintain the phase consistency of the three power amplifiers, 90 • phase compensation lines with characteristic impedance of 50 Ω have been added before the main power amplifier and the second peak power amplifier.The power-combining circuit follows the structure described in Section 2.3.1.Both the power divider and the power-combining circuit have been implemented using microstrip circuits.These circuits were manufactured on PTFE material substrate with low dielectric constant of 2.2 and thickness of 762 µm to ensure that the microstrip widths are sufficiently large to meet the requirements for high power.They are both sintered onto the test fixture and connected to single amplifiers, as described above, using wire bonding.SMA connectors were added at the input and output positions of the power amplifier for test purposes.Properly located pads for feeding and grounding were introduced, and the grounding pads were connected to the test fixture through vias.In addition, capacitors of 100 pF, 1000 pF, and 43 µF were placed between the feeding and grounding pads to filter out high-frequency noise.Figure 13 shows a photograph of the whole Doherty power amplifier.The overall dimensions of the circuit are 66 mm × 60 mm, and its weight is 103.4 g. constant of 2.2 and thickness of 762 µm to ensure that the microstrip widths are sufficiently large to meet the requirements for high power.They are both sintered onto the test fixture and connected to single amplifiers, as described above, using wire bonding.SMA connectors were added at the input and output positions of the power amplifier for test purposes.Properly located pads for feeding and grounding were introduced, and the grounding pads were connected to the test fixture through vias.In addition, capacitors of 100 pF, 1000 pF, and 43 µF were placed between the feeding and grounding pads to filter out high-frequency noise.Figure 13 shows a photograph of the whole Doherty power amplifier.The overall dimensions of the circuit are 66 mm × 60 mm, and its weight is 103.4 g.

RF OUT RF IN
Carrier PA 1 st Peak PA 2 nd Peak PA Single power amplifier

CW Test
As described above, this study employed the Doherty amplifier structure shown in Figure 2b.In this configuration, for each single amplifier, the other two amplifiers act as feedback loops introduced at the input.The introduction of feedback has a significant impact on the Doherty amplifier when a single amplifier experiences self-oscillation, leading to a substantial increase in noise and severe interference with the integrity of the signal.To avoid such occurrences, it is crucial to ensure the stability of the Doherty amplifier.
In Section 2.3.2, the stability of the single amplifier was verified through simulation, and prior to the continuous wave testing of the Doherty amplifier, its stability was experimentally confirmed.Under bias conditions of VDS = 28 V, VGMAIN = −2.1 V, VGPEAK1 = −4.2V, and VGPEAK2 = −6.8V, with no RF signal input, the drain current was zero.As the gate voltage of the main amplifier gradually increased, the drain current also steadily and linearly increased.This observation indicates that the Doherty amplifier does not undergo selfoscillation and can operate stably.
After verifying the stability of the Doherty amplifier under the same bias conditions, continuous-mode power scanning test and frequency scanning test were conducted on

CW Test
As described above, this study employed the Doherty amplifier structure shown in Figure 2b.In this configuration, for each single amplifier, the other two amplifiers act as feedback loops introduced at the input.The introduction of feedback has a significant impact on the Doherty amplifier when a single amplifier experiences self-oscillation, leading to a substantial increase in noise and severe interference with the integrity of the signal.To avoid such occurrences, it is crucial to ensure the stability of the Doherty amplifier.
In Section 2.3.2, the stability of the single amplifier was verified through simulation, and prior to the continuous wave testing of the Doherty amplifier, its stability was experimentally confirmed.Under bias conditions of V DS = 28 V, V GMAIN = −2.1 V, V GPEAK1 = −4.2V, and V GPEAK2 = −6.8V, with no RF signal input, the drain current was zero.As the gate voltage of the main amplifier gradually increased, the drain current also steadily and linearly increased.This observation indicates that the Doherty amplifier does not undergo self-oscillation and can operate stably.
After verifying the stability of the Doherty amplifier under the same bias conditions, continuous-mode power scanning test and frequency scanning test were conducted on the designed Doherty power amplifier.Figure 14a-c depict the results of the power scanning tests; Figure 14a,b show the test results and simulation results for PAE and drain efficiency, while Figure 14c illustrates the gain characteristics of the Doherty power amplifier.
As shown in Figure 14, at 2.6 GHz, the saturated output power was 49.7 dBm, with a drain efficiency exceeding 67% and gain exceeding 9 dB.At the output power of 40.5 dBm, corresponding to a 9 dB power back-off, the drain efficiency remained above 55%, and the gain was above 8 dB.Comparison with simulation results reveals that, under large-signal excitation, the measured drain efficiency and gain exhibit errors of less than 5% and less than 1 dB, respectively.The overall trend is consistent with the simulation results, confirming the accuracy of the model.The sources of error may originate from two aspects: bonding wires and thermal effects.It is challenging to accurately describe the shape of bonding wires, gold ribbons, and the location of pads during the simulation process.Additionally, the heat generated by the Doherty amplifier can reduce the drain efficiency, and the EE_HEMT model has certain limitations in accurately characterizing the self-heating effects of the transistor.This limitation results in an inability to accurately simulate the thermal effects of the transistor.
the designed Doherty power amplifier.Figure 14a-c depict the results of the power scanning tests; Figure 14a,b show the test results and simulation results for PAE and drain efficiency, while Figure 14c illustrates the gain characteristics of the Doherty power amplifier.As shown in Figure 14, at 2.6 GHz, the saturated output power was 49.7 dBm, with a drain efficiency exceeding 67% and gain exceeding 9 dB.At the output power of 40.5 dBm, corresponding to a 9 dB power back-off, the drain efficiency remained above 55%, and the gain was above 8 dB.Comparison with simulation results reveals that, under large-signal excitation, the measured drain efficiency and gain exhibit errors of less than 5% and less than 1 dB, respectively.The overall trend is consistent with the simulation results, confirming the accuracy of the model.The sources of error may originate from two aspects: bonding wires and thermal effects.It is challenging to accurately describe the shape of bonding wires, gold ribbons, and the location of pads during the simulation process.Additionally, the heat generated by the Doherty amplifier can reduce the drain efficiency, and the EE_HEMT model has certain limitations in accurately characterizing the self-heating effects of the transistor.This limitation results in an inability to accurately simulate the thermal effects of the transistor.
We observed that the trends of the curves obtained from simulation and experimentation were similar but not entirely identical.In comparison to the test results, the simulation results show an earlier occurrence of the first maximum efficiency point.This discrepancy arises because the model was established based on parameters extracted in the transistor's on state, introducing errors in describing the transistor's deep Class-C-mode operating state.In model-based simulations, the auxiliary amplifier is entirely shut off during Class-C operation, whereas in reality, a small portion of the main amplifier's power leaks into the auxiliary amplifiers, preventing a complete off state and causing the maximum efficiency point to appear later.
Additionally, according to Figure 14a,b, it is noted that the simulated results for power-added efficiency are slightly lower than the test results, while the relationship of drain efficiency between simulation and test is reversed.The probable cause of this trend is that the actual input signal was smaller than the ideal input signal in the test.The actual We observed that the trends of the curves obtained from simulation and experimentation were similar but not entirely identical.In comparison to the test results, the simulation results show an earlier occurrence of the first maximum efficiency point.This discrepancy arises because the model was established based on parameters extracted in the transistor's on state, introducing errors in describing the transistor's deep Class-C-mode operating state.In model-based simulations, the auxiliary amplifier is entirely shut off during Class-C operation, whereas in reality, a small portion of the main amplifier's power leaks into the auxiliary amplifiers, preventing a complete off state and causing the maximum efficiency point to appear later.
Additionally, according to Figure 14a,b, it is noted that the simulated results for poweradded efficiency are slightly lower than the test results, while the relationship of drain efficiency between simulation and test is reversed.The probable cause of this trend is that the actual input signal was smaller than the ideal input signal in the test.The actual input signal, generated by the signal generator and amplified by the solid-state amplifier, was slightly reduced due to the connection losses between devices and the noise from the signal generator to the solid-state amplifier.In contrast, the simulation uses an ideal input signal.
Figure 15 indicates the relationships between the input power and efficiency of the Doherty power amplifier within a frequency range of 2.55 GHz to 2.62 GHz.As shown in the graph, this Doherty power amplifier exhibits stable performance within bandwidth of 70 MHz.
Table 2 presents a comparison between this work and other three-stage Doherty power amplifiers.Compared with other results, this study demonstrates larger saturated output power, higher drain efficiency, and higher linearity.input signal, generated by the signal generator and amplified by the solid-state amplifier, was slightly reduced due to the connection losses between devices and the noise from the signal generator to the solid-state amplifier.In contrast, the simulation uses an ideal input signal.
Figure 15 indicates the relationships between the input power and efficiency of the Doherty power amplifier within a frequency range of 2.55 GHz to 2.62 GHz.As shown in the graph, this Doherty power amplifier exhibits stable performance within bandwidth of 70 MHz.Table 2 presents a comparison between this work and other three-stage Doherty power amplifiers.Compared with other results, this study demonstrates larger saturated output power, higher drain efficiency, and higher linearity.

Modulated Signal Test
Linearity testing was conducted using a modulation signal test system.A Rohde & Schwarz vector signal generator, model SMW200A, was employed to generate the modulation signal, and a spectrum analyzer, model FSW, was used to test the EVM (error vector magnitude) and ACLR (adjacent-channel leakage ratio).
The vector signal generator generated a 10 MHz bandwidth QPSK signal with PAPR of approximately 8.3 dB.The amplifier was biased in the same way as in the continuous wave test, with VDS = 28 V, VGMAIN = −2.1 V, VGPEAK1 = −4.2V, and VGPEAK2 = −6.8V.The test process incorporated DPD technology, and the ACLR test results are depicted in Figure 16.The ACLRs of lower and upper adjacent channels were −22.19 dBc and −23.66 dBc

Modulated Signal Test
Linearity testing was conducted using a modulation signal test system.A Rohde & Schwarz vector signal generator, model SMW200A, was employed to generate the modulation signal, and a spectrum analyzer, model FSW, was used to test the EVM (error vector magnitude) and ACLR (adjacent-channel leakage ratio).
The vector signal generator generated a 10 MHz bandwidth QPSK signal with PAPR of approximately 8.3 dB.The amplifier was biased in the same way as in the continuous wave test, with V DS = 28 V, V GMAIN = −2.1 V, V GPEAK1 = −4.2V, and V GPEAK2 = −6.8V.The test process incorporated DPD technology, and the ACLR test results are depicted in Figure 16.The ACLRs of lower and upper adjacent channels were −22.19 dBc and −23.66 dBc without DPD, and while using DPD, the ACLRs of lower and upper adjacent channels were 50.93 dBc and 52.0 dBc, indicating the high linearity of the Doherty power amplifier.without DPD, and while using DPD, the ACLRs of lower and upper adjacent channels were 50.93 dBc and 52.0 dBc, indicating the high linearity of the Doherty power amplifier.

Temperature Test and Aging Test
Temperature can significantly impact the DC and microwave characteristics of GaN HEMT devices, with performance degradation being more pronounced at high temperatures.The reasons for this are as follows.Firstly, an increase in junction temperature leads

Temperature Test and Aging Test
Temperature can significantly impact the DC and microwave characteristics of GaN HEMT devices, with performance degradation being more pronounced at high temperatures.The reasons for this are as follows.Firstly, an increase in junction temperature leads to a reduction in the carrier mobility and saturation drift velocity, diminishing the device's switching speed and subsequently affecting its high-frequency performance.Additionally, in HEMT devices, the gate contact to the semiconductor substrate junction is an Ohmic contact, while the source and drain contacts to the semiconductor substrate are Schottky contacts.Elevated temperatures accelerate diffusion between the metal and semiconductor, degrading both ohmic and Schottky contacts.This results in a reduction in the barrier height, lowering the breakdown voltage and power-handling capacity of the device, which is detrimental to stable device operation.Furthermore, prolonged operation at high temperatures may also impact circuit components.Excessive temperatures can lead to wire bond failures, and the Q-value of chip capacitors may decrease, affecting the overall circuit performance.In summary, under high-temperature conditions, the reliability and electrical performance of GaN HEMT devices and circuits tend to degrade, while the opposite is true under low-temperature conditions.
In order to validate the circuit's reliability, high-temperature (+85 • C) and low-temperature (−30 • C) tests were conducted on the Doherty power amplifier under the same conditions as the continuous wave test.Figure 17a,b present the drain efficiency and gain results of power scanning tests at high, room, and low temperatures.In addition, in order to test long-term stable operation capability, aging tests were conducted on the Doherty power amplifier under room-temperature conditions.Under the same bias conditions, the power amplifier worked continuously for 160 h at input power levels of 31 dBm and 40 dBm, corresponding to the back-off and saturated points of the Doherty power amplifier, respectively.The results showed that amplifier could still operate normally after the aging test with almost consistent performance.The designed Doherty power amplifier demonstrates capacity for long-term stable operation, exhibiting a certain degree of reliability.

Discussion
This study conducted a theoretical analysis of a three-stage Doherty power amplifier power-synthesis network and designed a three-stage high-power Doherty power amplifier based on the theoretical analysis.The test results indicate that the designed Doherty power amplifier can effectively extend the power back-off range of traditional Doherty amplifier architectures, consistent with the theoretical analysis.Additionally, as described in Section 2.3.2, the harmonic matching technique employed in the single amplifier enhances the overall efficiency of the Doherty power amplifier to a certain extent.In comparison to recently reported Doherty power amplifiers, this study demonstrates advantages in performance metrics such as output power and efficiency.
Future research will focus on expanding the operational bandwidth of the Doherty power amplifier while ensuring output power.Bandwidth expansion may be achieved by reducing the use of quarter-wavelength lines to improve the power-combining network As depicted in the figures, the designed Doherty power amplifier operates normally at both +85 • C and −30 • C temperatures.In the power back-off range, its drain efficiency changes by less than ±8%, and gain changes are within ±1.5 dB, showing consistent trends.These results indicate that the Doherty power amplifier exhibits high reliability under different temperature conditions.
In addition, in order to test long-term stable operation capability, aging tests were conducted on the Doherty power amplifier under room-temperature conditions.Under the same bias conditions, the power amplifier worked continuously for 160 h at input power levels of 31 dBm and 40 dBm, corresponding to the back-off and saturated points of the Doherty power amplifier, respectively.The results showed that amplifier could still operate normally after the aging test with almost consistent performance.The designed Doherty power amplifier demonstrates capacity for long-term stable operation, exhibiting a certain degree of reliability.

Discussion
This study conducted a theoretical analysis of a three-stage Doherty power amplifier power-synthesis network and designed a three-stage high-power Doherty power amplifier based on the theoretical analysis.The test results indicate that the designed Doherty power amplifier can effectively extend the power back-off range of traditional Doherty amplifier architectures, consistent with the theoretical analysis.Additionally, as described in Section 2.3.2, the harmonic matching technique employed in the single amplifier enhances the overall efficiency of the Doherty power amplifier to a certain extent.In comparison to recently reported Doherty power amplifiers, this study demonstrates advantages in performance metrics such as output power and efficiency.
Future research will focus on expanding the operational bandwidth of the Doherty power amplifier while ensuring output power.Bandwidth expansion may be achieved by reducing the use of quarter-wavelength lines to improve the power-combining network and implementing a wideband matching strategy for the single amplifier.These improvements are expected to further enhance the performance of the Doherty power amplifier across different frequency ranges, better meeting the demands of practical applications.

Figure 1 .
Figure 1.Schematic diagram of traditional Doherty amplifier structure.

Figure 2 .
Figure 2. Schematic diagrams of two three-stage Doherty power amplifier structures, (a) is extension of the traditional Doherty structure and (b) is an improved structure proposed by NXP.

Figure 2 .
Figure 2. Schematic diagrams of two three-stage Doherty power amplifier structures, (a) is extension of the traditional Doherty structure and (b) is an improved structure proposed by NXP.

Figure 3 .
Figure 3. Schematic diagram of the longitudinal structure of GaN HEMT (a) and photograph of (b) its use in this design.

Figure 3 .
Figure 3. Schematic diagram of the longitudinal structure of GaN HEMT (a) and photograph of (b) its use in this design.

Figure 3 .
Figure 3. Schematic diagram of the longitudinal structure of GaN HEMT (a) and photograph of (b) its use in this design.

Figure 4 .
Figure 4. Microscopic photo of 1.2 mm gate-width model transistor.Figure 4. Microscopic photo of 1.2 mm gate-width model transistor.

Figure 4 .
Figure 4. Microscopic photo of 1.2 mm gate-width model transistor.Figure 4. Microscopic photo of 1.2 mm gate-width model transistor.DC scanning testing and S-parameter scanning testing in the frequency range of 0.4 GHz to 35 GHz with a pulse period of 1 ms and a duty cycle of 10% were conducted to extract intrinsic and parasitic parameters of the model transistor described above.By fitting the intrinsic and parasitic parameters, an equivalent circuit for the large-signal EE_HEMT model, as depicted in Figure 5a,b, was established.The extracted intrinsic parameters of

Figure 5 .
Figure 5. Intrinsic equivalent circuit diagram (a) and parasitic parameter equivalent circuit diagram (b) of the large-signal EE_HEMT model.

Figure 6 .
Figure 6.Comparison between simulation and measurement of DC characteristics of 1.2 mm gatewidth model transistor, (a) drain current and (b) gain current.

Figure 5 .
Figure 5. Intrinsic equivalent circuit diagram (a) and parasitic parameter equivalent circuit diagram (b) of the large-signal EE_HEMT model.

Figure 5 .
Figure 5. Intrinsic equivalent circuit diagram (a) and parasitic parameter equivalent circuit diagram (b) of the large-signal EE_HEMT model.

Figure 6 .
Figure 6.Comparison between simulation and measurement of DC characteristics of 1.2 mm gatewidth model transistor, (a) drain current and (b) gain current.Figure 6.Comparison between simulation and measurement of DC characteristics of 1.2 mm gatewidth model transistor, (a) drain current and (b) gain current.

Figure 6 .
Figure 6.Comparison between simulation and measurement of DC characteristics of 1.2 mm gatewidth model transistor, (a) drain current and (b) gain current.Figure 6.Comparison between simulation and measurement of DC characteristics of 1.2 mm gatewidth model transistor, (a) drain current and (b) gain current.

Figure 7 .
Figure 7.Comparison between simulation and measurement of 0.4-35 GHz S-parameters of 1.2 mm gate-width model transistor (a), magnitude error (b) and phase error (c).

Figure 8 .
Figure 8.Comparison between simulation and measurement of output power and PAE of 1.2 mm gate-width model transistor.

Figure 7 .
Figure 7.Comparison between simulation and measurement of 0.4-35 GHz S-parameters of 1.2 mm gate-width model transistor (a), magnitude error (b) and phase error (c).

Figure 7 .
Figure 7.Comparison between simulation and measurement of 0.4-35 GHz S-parameters of 1.2 mm gate-width model transistor (a), magnitude error (b) and phase error (c).

Figure 8 .
Figure 8.Comparison between simulation and measurement of output power and PAE of 1.2 mm gate-width model transistor.

Figure 8 .
Figure 8.Comparison between simulation and measurement of output power and PAE of 1.2 mm gate-width model transistor.2.3.Theory and Circuit 2.3.1.Load Modulation Behavior Analysis of Three-Stage Doherty PA

Figure 10 .
Figure 10.Contour of S 11 in intrinsic current source plane (a) and contour of S 11 for output-matching network (b).

Figure 10 .
Figure 10.Contour of S11 in intrinsic current source plane (a) and contour of S11 for output-matching network (b).

Figure 12 .
Figure 12.Simulation results of single amplifier (a) return loss and (b) output power and PAE.

Figure 12 .
Figure 12.Simulation results of single amplifier (a) return loss and (b) output power and PAE.

Figure 12 .
Figure 12.Simulation results of single amplifier (a) return loss and (b) output power and PAE.

Figure 13 .
Figure 13.Photograph of whole Doherty PA and single PA.

Figure 13 .
Figure 13.Photograph of whole Doherty PA and single PA.

Figure 14 .
Figure 14.CW test results and simulation results of PAE (a), drain efficiency (b), and gain (c).

Figure 14 .
Figure 14.CW test results and simulation results of PAE (a), drain efficiency (b), and gain (c).

Figure 15 .
Figure 15.Test results results of drain efficiency and gain at 2.55 GHz-2.62GHz.

Figure 15 .
Figure 15.Test results results of drain efficiency and gain at 2.55 GHz-2.62GHz.

Figure 16 .
Figure 16.Test results of ACLR with 10 MHz QPSK signal.

Figure 17 .
Figure 17.Test results of drain efficiency (a) and gain (b) at different temperatures.

Figure 17 .
Figure 17.Test results of drain efficiency (a) and gain (b) at different temperatures.

Table 1 .
The values of δ1 and δ2 as vin increases.
shows the schematic diagram of a single amplifier.

Table 2 .
Compared with other three-stage Doherty PAs.

Table 2 .
Compared with other three-stage Doherty PAs.
Test results of ACLR with 10 MHz QPSK signal.